^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Synopsys DesignWare I2C adapter driver (master only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on the TI DAVINCI I2C adapter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2007 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2009 Provigent Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "i2c-designware-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Configure Tx/Rx FIFO threshold levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) regmap_write(dev->map, DW_IC_RX_TL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Configure the I2C master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const char *mode_str, *fp_str = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 comp_param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 sda_falling_time, scl_falling_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct i2c_timings *t = &dev->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 ic_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ret = i2c_dw_acquire_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) i2c_dw_release_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Set standard and fast speed dividers for high/low periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Calculate SCL timing parameters for standard mode if not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!dev->ss_hcnt || !dev->ss_lcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ic_clk = i2c_dw_clk_rate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dev->ss_hcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) i2c_dw_scl_hcnt(ic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 4000, /* tHD;STA = tHIGH = 4.0 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) sda_falling_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0, /* 0: DW default, 1: Ideal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0); /* No offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev->ss_lcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) i2c_dw_scl_lcnt(ic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 4700, /* tLOW = 4.7 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) scl_falling_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0); /* No offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) dev->ss_hcnt, dev->ss_lcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Set SCL timing parameters for fast mode or fast mode plus. Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * difference is the timing parameter values since the registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (t->bus_freq_hz == 1000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Check are Fast Mode Plus parameters available. Calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * SCL timing parameters for Fast Mode Plus if not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (dev->fp_hcnt && dev->fp_lcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev->fs_hcnt = dev->fp_hcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev->fs_lcnt = dev->fp_lcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ic_clk = i2c_dw_clk_rate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev->fs_hcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) i2c_dw_scl_hcnt(ic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 260, /* tHIGH = 260 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sda_falling_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0, /* DW default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0); /* No offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev->fs_lcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) i2c_dw_scl_lcnt(ic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 500, /* tLOW = 500 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) scl_falling_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0); /* No offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) fp_str = " Plus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Calculate SCL timing parameters for fast mode if not set. They are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * needed also in high speed mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!dev->fs_hcnt || !dev->fs_lcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ic_clk = i2c_dw_clk_rate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev->fs_hcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) i2c_dw_scl_hcnt(ic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 600, /* tHD;STA = tHIGH = 0.6 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sda_falling_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0, /* 0: DW default, 1: Ideal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0); /* No offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev->fs_lcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) i2c_dw_scl_lcnt(ic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 1300, /* tLOW = 1.3 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) scl_falling_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0); /* No offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) fp_str, dev->fs_hcnt, dev->fs_lcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Check is high speed possible and fall back to fast mode if not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DW_IC_CON_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_err(dev->dev, "High Speed not supported!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev->master_cfg |= DW_IC_CON_SPEED_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev->hs_hcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev->hs_lcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } else if (!dev->hs_hcnt || !dev->hs_lcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ic_clk = i2c_dw_clk_rate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev->hs_hcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) i2c_dw_scl_hcnt(ic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 160, /* tHIGH = 160 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) sda_falling_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0, /* DW default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0); /* No offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev->hs_lcnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) i2c_dw_scl_lcnt(ic_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 320, /* tLOW = 320 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) scl_falling_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0); /* No offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev->hs_hcnt, dev->hs_lcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = i2c_dw_set_sda_hold(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case DW_IC_CON_SPEED_STD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mode_str = "Standard Mode";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case DW_IC_CON_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mode_str = "High Speed Mode";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mode_str = "Fast Mode";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * i2c_dw_init() - Initialize the designware I2C master hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @dev: device private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * This functions configures and enables the I2C master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * This function is called during I2C init function, and in case of timeout at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * run time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int i2c_dw_init_master(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = i2c_dw_acquire_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Disable the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __i2c_dw_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Write standard speed timing parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Write fast mode/fast mode plus timing parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Write high speed timing parameters if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (dev->hs_hcnt && dev->hs_lcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Write SDA hold time if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (dev->sda_hold_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) i2c_dw_configure_fifo_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) i2c_dw_release_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct i2c_msg *msgs = dev->msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 ic_con = 0, ic_tar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Disable the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __i2c_dw_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* If the slave address is ten bit address, enable 10BITADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ic_con = DW_IC_CON_10BITADDR_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * mode has to be enabled via bit 12 of IC_TAR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * detected from registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ic_tar = DW_IC_TAR_10BITADDR_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ic_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Set the slave (target) address and enable 10-bit addressing mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * if applicable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) regmap_write(dev->map, DW_IC_TAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) msgs[dev->msg_write_idx].addr | ic_tar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Enforce disabled interrupts (due to HW issues) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) i2c_dw_disable_int(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Enable the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __i2c_dw_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Dummy read to avoid the register getting stuck on Bay Trail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Clear and enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Initiate (and continue) low level master read/write transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * This function is only called from i2c_dw_isr, and pumping i2c_msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * messages into the tx buffer. Even if the size of i2c_msg data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * longer than the size of the tx buffer, it handles everything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct i2c_msg *msgs = dev->msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int tx_limit, rx_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 addr = msgs[dev->msg_write_idx].addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 buf_len = dev->tx_buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 *buf = dev->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bool need_restart = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int flr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) intr_mask = DW_IC_INTR_MASTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 flags = msgs[dev->msg_write_idx].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * If target address has changed, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * reprogram the target address in the I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * adapter when we are done with this transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (msgs[dev->msg_write_idx].addr != addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "%s: invalid target address\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev->msg_err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* new i2c_msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) buf = msgs[dev->msg_write_idx].buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) buf_len = msgs[dev->msg_write_idx].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * IC_RESTART_EN are set, we must manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * set restart bit between messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (dev->msg_write_idx > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) need_restart = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) regmap_read(dev->map, DW_IC_TXFLR, &flr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tx_limit = dev->tx_fifo_depth - flr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) regmap_read(dev->map, DW_IC_RXFLR, &flr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rx_limit = dev->rx_fifo_depth - flr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * manually set the stop bit. However, it cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * detected from the registers so we set it always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * when writing/reading the last byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * i2c-core always sets the buffer length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * be adjusted when receiving the first byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Thus we can't stop the transaction here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (dev->msg_write_idx == dev->msgs_num - 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) buf_len == 1 && !(flags & I2C_M_RECV_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cmd |= BIT(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (need_restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cmd |= BIT(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) need_restart = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Avoid rx buffer overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (dev->rx_outstanding >= dev->rx_fifo_depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) regmap_write(dev->map, DW_IC_DATA_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) cmd | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) rx_limit--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev->rx_outstanding++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) regmap_write(dev->map, DW_IC_DATA_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cmd | *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) tx_limit--; buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev->tx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev->tx_buf_len = buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * Because we don't know the buffer length in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * the transaction here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* more bytes to be written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev->status |= STATUS_WRITE_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev->status &= ~STATUS_WRITE_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * If i2c_msg index search is completed, we don't need TX_EMPTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * interrupt any more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (dev->msg_write_idx == dev->msgs_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) intr_mask &= ~DW_IC_INTR_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (dev->msg_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) intr_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct i2c_msg *msgs = dev->msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 flags = msgs[dev->msg_read_idx].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * Adjust the buffer length and mask the flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * after receiving the first byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) msgs[dev->msg_read_idx].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) i2c_dw_read(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct i2c_msg *msgs = dev->msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int rx_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 len, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) len = msgs[dev->msg_read_idx].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) buf = msgs[dev->msg_read_idx].buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) len = dev->rx_buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) buf = dev->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 flags = msgs[dev->msg_read_idx].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Ensure length byte is a valid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (flags & I2C_M_RECV_LEN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) tmp <= I2C_SMBUS_BLOCK_MAX && tmp > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) len = i2c_dw_recv_len(dev, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *buf++ = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev->rx_outstanding--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev->status |= STATUS_READ_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev->rx_buf_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev->rx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev->status &= ~STATUS_READ_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Prepare controller for a transaction and call i2c_dw_xfer_msg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pm_runtime_get_sync(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) goto done_nolock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) reinit_completion(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev->msgs = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev->msgs_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev->cmd_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev->msg_write_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev->msg_read_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev->msg_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev->status = STATUS_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev->abort_source = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev->rx_outstanding = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = i2c_dw_acquire_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto done_nolock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = i2c_dw_wait_bus_not_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Start the transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) i2c_dw_xfer_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Wait for tx to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(dev->dev, "controller timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* i2c_dw_init implicitly disables the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) i2c_recover_bus(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) i2c_dw_init_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * We must disable the adapter before returning and signaling the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * of the current transfer. Otherwise the hardware might continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * generating interrupts which in turn causes a race condition with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * the following transfer. Needs some more investigation if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * additional interrupts are a hardware bug or this driver doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * handle them correctly yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) __i2c_dw_disable_nowait(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (dev->msg_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = dev->msg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* No error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (likely(!dev->cmd_err && !dev->status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* We have an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = i2c_dw_handle_tx_abort(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (dev->status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "transfer terminated early - interrupt latency too high?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) i2c_dw_release_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) done_nolock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pm_runtime_mark_last_busy(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pm_runtime_put_autosuspend(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct i2c_algorithm i2c_dw_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .master_xfer = i2c_dw_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .functionality = i2c_dw_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct i2c_adapter_quirks i2c_dw_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 stat, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * The IC_INTR_STAT register just indicates "enabled" interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * The unmasked raw version of interrupt status bits is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * in the IC_RAW_INTR_STAT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * That is,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * stat = readl(IC_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * equals to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * The raw version might be useful for debugging purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Do not use the IC_CLR_INTR register to clear interrupts, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * you'll miss some interrupts, triggered during the period from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * Instead, use the separately-prepared IC_CLR_* registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (stat & DW_IC_INTR_RX_UNDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (stat & DW_IC_INTR_RX_OVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (stat & DW_IC_INTR_TX_OVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (stat & DW_IC_INTR_RD_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (stat & DW_IC_INTR_TX_ABRT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * The IC_TX_ABRT_SOURCE register is cleared whenever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (stat & DW_IC_INTR_RX_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (stat & DW_IC_INTR_ACTIVITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (stat & DW_IC_INTR_STOP_DET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (stat & DW_IC_INTR_START_DET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (stat & DW_IC_INTR_GEN_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Interrupt service routine. This gets called whenever an I2C master interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) stat = i2c_dw_read_clear_intrbits(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (stat & DW_IC_INTR_TX_ABRT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev->cmd_err |= DW_IC_ERR_TX_ABRT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev->status = STATUS_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Anytime TX_ABRT is set, the contents of the tx/rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * buffers are flushed. Make sure to skip them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) regmap_write(dev->map, DW_IC_INTR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) goto tx_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (stat & DW_IC_INTR_RX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) i2c_dw_read(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (stat & DW_IC_INTR_TX_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) i2c_dw_xfer_msg(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * No need to modify or disable the interrupt mask here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * i2c_dw_xfer_msg() will take care of it according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * the current transmit status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) tx_aborted:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) complete(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Workaround to trigger pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) i2c_dw_disable_int(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) regmap_write(dev->map, DW_IC_INTR_MASK, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct dw_i2c_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u32 stat, enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) regmap_read(dev->map, DW_IC_ENABLE, &enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) i2c_dw_irq_handler_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) void i2c_dw_configure_master(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct i2c_timings *t = &dev->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) DW_IC_CON_RESTART_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev->mode = DW_IC_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) switch (t->bus_freq_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case I2C_MAX_STANDARD_MODE_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev->master_cfg |= DW_IC_CON_SPEED_STD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case I2C_MAX_HIGH_SPEED_MODE_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dev->master_cfg |= DW_IC_CON_SPEED_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) i2c_dw_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) reset_control_assert(dev->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) i2c_dw_prepare_clk(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) i2c_dw_prepare_clk(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) reset_control_deassert(dev->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) i2c_dw_init_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct i2c_adapter *adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct gpio_desc *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (IS_ERR_OR_NULL(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return PTR_ERR_OR_ZERO(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) rinfo->scl_gpiod = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (IS_ERR(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) rinfo->sda_gpiod = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) rinfo->recover_bus = i2c_generic_scl_recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) rinfo->prepare_recovery = i2c_dw_prepare_recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) adap->bus_recovery_info = rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_info(dev->dev, "running with gpio recovery mode! scl%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) rinfo->sda_gpiod ? ",sda" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int i2c_dw_probe_master(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct i2c_adapter *adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) init_completion(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev->init = i2c_dw_init_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev->disable = i2c_dw_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev->disable_int = i2c_dw_disable_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret = i2c_dw_init_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = i2c_dw_set_timings_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = i2c_dw_set_fifo_size(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = dev->init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) snprintf(adap->name, sizeof(adap->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "Synopsys DesignWare I2C adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) adap->retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) adap->algo = &i2c_dw_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) adap->quirks = &i2c_dw_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) adap->dev.parent = dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) i2c_set_adapdata(adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) irq_flags = IRQF_NO_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) i2c_dw_disable_int(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_name(dev->dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev_err(dev->dev, "failure requesting irq %i: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = i2c_dw_init_recovery_info(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * Increment PM usage count during adapter registration in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * avoid possible spurious runtime suspend when adapter device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * registered to the device core and immediate resume in case bus has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * registered I2C slaves that do I2C transfers in their probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pm_runtime_get_noresume(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_err(dev->dev, "failure adding adapter: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pm_runtime_put_noidle(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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