^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Synopsys DesignWare I2C adapter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on the TI DAVINCI I2C adapter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2007 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2009 Provigent Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/swab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "i2c-designware-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static char *abort_sources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [ABRT_7B_ADDR_NOACK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "slave address not acknowledged (7bit mode)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [ABRT_10ADDR1_NOACK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "first address byte not acknowledged (10bit mode)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) [ABRT_10ADDR2_NOACK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "second address byte not acknowledged (10bit mode)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [ABRT_TXDATA_NOACK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "data not acknowledged",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [ABRT_GCALL_NOACK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "no acknowledgement for a general call",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [ABRT_GCALL_READ] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "read after general call",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [ABRT_SBYTE_ACKDET] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "start byte acknowledged",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [ABRT_SBYTE_NORSTRT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "trying to send start byte when restart is disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [ABRT_10B_RD_NORSTRT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "trying to read when restart is disabled (10bit mode)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) [ABRT_MASTER_DIS] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "trying to use disabled adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [ARB_LOST] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "lost arbitration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [ABRT_SLAVE_FLUSH_TXFIFO] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "read command so flush old data in the TX FIFO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [ABRT_SLAVE_ARBLOST] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "slave lost the bus while transmitting data to a remote master",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [ABRT_SLAVE_RD_INTX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "incorrect slave-transmitter mode configuration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct dw_i2c_dev *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *val = readl_relaxed(dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct dw_i2c_dev *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel_relaxed(val, dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct dw_i2c_dev *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *val = swab32(readl_relaxed(dev->base + reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct dw_i2c_dev *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel_relaxed(swab32(val), dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct dw_i2c_dev *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *val = readw_relaxed(dev->base + reg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (readw_relaxed(dev->base + reg + 2) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct dw_i2c_dev *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writew_relaxed(val, dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writew_relaxed(val >> 16, dev->base + reg + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * i2c_dw_init_regmap() - Initialize registers map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @dev: device private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Autodetects needed register access mode and creates the regmap with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * corresponding read/write callbacks. This must be called before doing any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * other register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct regmap_config map_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .disable_locking = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .reg_read = dw_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .reg_write = dw_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .max_register = DW_IC_COMP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Skip detecting the registers map configuration if the regmap has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * already been provided by a higher code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (dev->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = i2c_dw_acquire_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg = readl(dev->base + DW_IC_COMP_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) i2c_dw_release_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) map_cfg.reg_read = dw_reg_read_swab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) map_cfg.reg_write = dw_reg_write_swab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) map_cfg.reg_read = dw_reg_read_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) map_cfg.reg_write = dw_reg_write_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) } else if (reg != DW_IC_COMP_TYPE_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "Unknown Synopsys component type: 0x%08x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Note we'll check the return value of the regmap IO accessors only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * at the probe stage. The rest of the code won't do this because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * basically we have MMIO-based regmap so non of the read/write methods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * can fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (IS_ERR(dev->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(dev->dev, "Failed to init the registers map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return PTR_ERR(dev->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const u32 supported_speeds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) I2C_MAX_HIGH_SPEED_MODE_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) I2C_MAX_FAST_MODE_PLUS_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) I2C_MAX_FAST_MODE_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) I2C_MAX_STANDARD_MODE_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct i2c_timings *t = &dev->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Only standard mode at 100kHz, fast mode at 400kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (t->bus_freq_hz == supported_speeds[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) t->bus_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * The HCNT/LCNT information coming from ACPI should be the most accurate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * for given platform. However, some systems get it wrong. On such systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * we get better results by calculating those based on the input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .ident = "Dell Inspiron 7348",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void i2c_dw_acpi_params(struct device *device, char method[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u16 *hcnt, u16 *lcnt, u32 *sda_hold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) acpi_handle handle = ACPI_HANDLE(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) union acpi_object *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (dmi_check_system(i2c_dw_no_acpi_params))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) obj = (union acpi_object *)buf.pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) const union acpi_object *objs = obj->package.elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *hcnt = (u16)objs[0].integer.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *lcnt = (u16)objs[1].integer.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *sda_hold = (u32)objs[2].integer.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) kfree(buf.pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int i2c_dw_acpi_configure(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct dw_i2c_dev *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct i2c_timings *t = &dev->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Try to get SDA hold time and *CNT values from an ACPI method for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * selected speed modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) switch (t->bus_freq_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case I2C_MAX_STANDARD_MODE_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev->sda_hold_time = ss_ht;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case I2C_MAX_FAST_MODE_PLUS_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev->sda_hold_time = fp_ht;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case I2C_MAX_HIGH_SPEED_MODE_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev->sda_hold_time = hs_ht;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case I2C_MAX_FAST_MODE_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev->sda_hold_time = fs_ht;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 acpi_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) acpi_speed = i2c_acpi_find_bus_speed(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Some DSTDs use a non standard speed, round down to the lowest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * standard speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (acpi_speed >= supported_speeds[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return supported_speeds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #else /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct i2c_timings *t = &dev->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Find bus speed from the "clock-frequency" device property, ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * or by using fast mode if neither is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (acpi_speed && t->bus_freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else if (acpi_speed || t->bus_freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * DesignWare I2C core doesn't seem to have solid strategy to meet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * will result in violation of the tHD;STA spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (cond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Conditional expression:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * This is based on the DW manuals, and represents an ideal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * configuration. The resulting I2C bus speed will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * faster than any of the others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * If your hardware is free from tHD;STA issue, try this one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Conditional expression:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * This is just experimental rule; the tHD;STA period turned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * out to be proportinal to (_HCNT + 3). With this setting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * we could meet both tHIGH and tHD;STA timing specs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * If unsure, you'd better to take this alternative.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * The reason why we need to take into account "tf" here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * is the same as described in i2c_dw_scl_lcnt().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) - 3 + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Conditional expression:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * DW I2C core starts counting the SCL CNTs for the LOW period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * of the SCL clock (tLOW) as soon as it pulls the SCL line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * In order to meet the tLOW timing spec, we need to take into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * account the fall time of SCL signal (tf). Default tf value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * should be 0.3 us, for safety.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = i2c_dw_acquire_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Configure SDA Hold Time if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto err_release_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!dev->sda_hold_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Keep previous hold time setting if no one set it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) &dev->sda_hold_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto err_release_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Workaround for avoiding TX arbitration lost in case I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * slave pulls SDA down "too quickly" after falling edge of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * SCL by enabling non-zero SDA RX hold. Specification says it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * extends incoming SDA low to high transition while SCL is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * high but it appears to help also above issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) } else if (dev->set_sda_hold_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev->set_sda_hold_time(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } else if (dev->sda_hold_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_warn(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "Hardware too old to adjust SDA hold time.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev->sda_hold_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) err_release_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) i2c_dw_release_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) void __i2c_dw_disable(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) __i2c_dw_disable_nowait(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * The enable status register may be unimplemented, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * in that case this test reads zero and exits the loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((status & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * Wait 10 times the signaling period of the highest I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * transfer supported by the driver (for 400KHz this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * 25us) as described in the DesignWare I2C databook.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) usleep_range(25, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } while (timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_warn(dev->dev, "timeout in disabling adapter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Clock is not necessary if we got LCNT/HCNT values directly from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * the platform code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return dev->get_clk_rate_khz(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (IS_ERR(dev->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (prepare) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Optional interface clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = clk_prepare_enable(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) clk_disable_unprepare(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!dev->acquire_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = dev->acquire_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_err(dev->dev, "couldn't acquire bus ownership\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) void i2c_dw_release_lock(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (dev->release_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev->release_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * Waiting for bus not busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) !(status & DW_IC_STATUS_ACTIVITY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 1100, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dev_warn(dev->dev, "timeout waiting for bus ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) i2c_recover_bus(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) regmap_read(dev->map, DW_IC_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!(status & DW_IC_STATUS_ACTIVITY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned long abort_source = dev->abort_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (abort_source & DW_IC_TX_ABRT_NOACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_dbg(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "%s: %s\n", __func__, abort_sources[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (abort_source & DW_IC_TX_ARB_LOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -EINVAL; /* wrong msgs[] data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 param, tx_fifo_depth, rx_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * Try to detect the FIFO depth if not set by interface driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * the depth could be from 2 to 256 from HW spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tx_fifo_depth = ((param >> 16) & 0xff) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) rx_fifo_depth = ((param >> 8) & 0xff) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (!dev->tx_fifo_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev->tx_fifo_depth = tx_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev->rx_fifo_depth = rx_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) } else if (tx_fifo_depth >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) tx_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) rx_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 i2c_dw_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return dev->functionality;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) void i2c_dw_disable(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Disable controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) __i2c_dw_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) regmap_write(dev->map, DW_IC_INTR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) void i2c_dw_disable_int(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) regmap_write(dev->map, DW_IC_INTR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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