^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI DAVINCI I2C adapter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Updated by Vinod & Sudhakar Feb 2005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_data/i2c-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* ----- global defines ----------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DAVINCI_I2C_TIMEOUT (1*HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DAVINCI_I2C_MAX_TRIES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DAVINCI_I2C_OWN_ADDRESS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DAVINCI_I2C_IMR_ARDY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DAVINCI_I2C_IMR_NACK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DAVINCI_I2C_IMR_AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DAVINCI_I2C_OAR_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DAVINCI_I2C_IMR_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DAVINCI_I2C_STR_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DAVINCI_I2C_CLKL_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DAVINCI_I2C_CLKH_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DAVINCI_I2C_CNT_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DAVINCI_I2C_DRR_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DAVINCI_I2C_SAR_REG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DAVINCI_I2C_DXR_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DAVINCI_I2C_MDR_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DAVINCI_I2C_IVR_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DAVINCI_I2C_EMDR_REG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DAVINCI_I2C_PSC_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DAVINCI_I2C_FUNC_REG 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DAVINCI_I2C_DIR_REG 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DAVINCI_I2C_DIN_REG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DAVINCI_I2C_DOUT_REG 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DAVINCI_I2C_DSET_REG 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DAVINCI_I2C_DCLR_REG 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DAVINCI_I2C_IVR_AAS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DAVINCI_I2C_IVR_SCD 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DAVINCI_I2C_IVR_XRDY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DAVINCI_I2C_IVR_RDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DAVINCI_I2C_IVR_ARDY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DAVINCI_I2C_IVR_NACK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DAVINCI_I2C_IVR_AL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DAVINCI_I2C_STR_BB BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DAVINCI_I2C_STR_RSFULL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DAVINCI_I2C_STR_SCD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DAVINCI_I2C_STR_ARDY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DAVINCI_I2C_STR_NACK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DAVINCI_I2C_STR_AL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DAVINCI_I2C_MDR_NACK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DAVINCI_I2C_MDR_STT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DAVINCI_I2C_MDR_STP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DAVINCI_I2C_MDR_MST BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DAVINCI_I2C_MDR_TRX BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DAVINCI_I2C_MDR_XA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DAVINCI_I2C_MDR_RM BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DAVINCI_I2C_MDR_IRS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DAVINCI_I2C_IMR_AAS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DAVINCI_I2C_IMR_SCD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DAVINCI_I2C_IMR_XRDY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DAVINCI_I2C_IMR_RRDY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DAVINCI_I2C_IMR_ARDY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DAVINCI_I2C_IMR_NACK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DAVINCI_I2C_IMR_AL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* set SDA and SCL as GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* set SCL as output when used as GPIO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DAVINCI_I2C_DIR_PDIR0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* set SDA as output when used as GPIO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DAVINCI_I2C_DIR_PDIR1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* read SCL GPIO level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DAVINCI_I2C_DIN_PDIN0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* read SDA GPIO level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DAVINCI_I2C_DIN_PDIN1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*set the SCL GPIO high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DAVINCI_I2C_DSET_PDSET0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*set the SDA GPIO high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DAVINCI_I2C_DSET_PDSET1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* set the SCL GPIO low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* set the SDA GPIO low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* timeout for pm runtime autosuspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct davinci_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct completion cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) size_t buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 terminate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct notifier_block freq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct davinci_i2c_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* default platform data to use if not supplied in the platform_device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .bus_freq = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .bus_delay = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writew_relaxed(val, i2c_dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return readw_relaxed(i2c_dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!val) /* put I2C into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) w &= ~DAVINCI_I2C_MDR_IRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) else /* take I2C out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) w |= DAVINCI_I2C_MDR_IRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct davinci_i2c_platform_data *pdata = dev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 clkh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 clkl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 input_clock = clk_get_rate(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct device_node *of_node = dev->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* NOTE: I2C Clock divider programming info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * As per I2C specs the following formulas provide prescaler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * and low/high divider values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * input clk --> PSC Div -----------> ICCL/H Div --> output clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * module clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Thus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * where if PSC == 0, d = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * if PSC == 1, d = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * if PSC > 1 , d = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * d is always 6 on Keystone I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Both Davinci and current Keystone User Guides recommend a value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * between 7MHz and 12MHz. In reality 7MHz module clock doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * always produce enough margin between SDA and SCL transitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Measurements show that the higher the module clock is, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * bigger is the margin, providing more reliable communication.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * So we better target for 12MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) psc = (input_clock / 12000000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if ((input_clock / (psc + 1)) > 12000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) psc++; /* better to run under spec than over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) d = (psc >= 2) ? 5 : 7 - psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) d = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Avoid driving the bus too fast because of rounding errors above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * to LOW ratio as 1 to 2 is more safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (pdata->bus_freq > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clkl = (clk << 1) / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clkl = (clk >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * It's not always possible to have 1 to 2 ratio when d=7, so fall back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * to minimal possible clkh in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * CLKH is not allowed to be 0, in this case I2C clock is not generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * at all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (clk > clkl + d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clkh = clk - clkl - d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clkl -= d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clkh = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) clkl = clk - (d << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * This function configures I2C and brings I2C out of reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * This function is called during I2C init function. This function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * also gets called if I2C encounters any errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int i2c_davinci_init(struct davinci_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct davinci_i2c_platform_data *pdata = dev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* put I2C into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) davinci_i2c_reset_ctrl(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* compute clock dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) i2c_davinci_calc_clk_dividers(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Respond at reserved "SMBus Host" slave address" (and zero);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * we seem to have no option to not respond...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_dbg(dev->dev, "PSC = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_dbg(dev->dev, "CLKL = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_dbg(dev->dev, "CLKH = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pdata->bus_freq, pdata->bus_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Take the I2C module out of reset: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) davinci_i2c_reset_ctrl(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * This routine does i2c bus recovery by using i2c_generic_scl_recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * which is provided by I2C Bus recovery infrastructure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* put I2C into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) davinci_i2c_reset_ctrl(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) i2c_davinci_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .recover_bus = i2c_generic_scl_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .prepare_recovery = davinci_i2c_prepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .unprepare_recovery = davinci_i2c_unprepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DAVINCI_I2C_DSET_PDSET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DAVINCI_I2C_DCLR_PDCLR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int davinci_i2c_get_scl(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* read the state of SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return val & DAVINCI_I2C_DIN_PDIN0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int davinci_i2c_get_sda(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* read the state of SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return val & DAVINCI_I2C_DIN_PDIN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) davinci_i2c_prepare_recovery(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* SCL output, SDA input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* change to GPIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DAVINCI_I2C_FUNC_PFUNC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* change back to I2C mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) davinci_i2c_unprepare_recovery(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .recover_bus = i2c_generic_scl_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .set_scl = davinci_i2c_set_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .get_scl = davinci_i2c_get_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .get_sda = davinci_i2c_get_sda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .prepare_recovery = davinci_i2c_scl_prepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Waiting for bus not busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long timeout = jiffies + dev->adapter.timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) } while (time_before_eq(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_warn(dev->dev, "timeout waiting for bus ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) i2c_recover_bus(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * if bus is still "busy" here, it's most probably a HW problem like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * short-circuit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Low level master read/write transaction. This function is called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * from i2c_davinci_xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct davinci_i2c_platform_data *pdata = dev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_warn(dev->dev, "transfer to own address aborted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Introduce a delay, required for some boards (e.g Davinci EVM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (pdata->bus_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) udelay(pdata->bus_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* set the slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev->buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev->buf_len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev->stop = stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) reinit_completion(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev->cmd_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Take I2C out of reset and configure it as master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* if the slave address is ten bit address, enable XA bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (msg->flags & I2C_M_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) flag |= DAVINCI_I2C_MDR_XA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!(msg->flags & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) flag |= DAVINCI_I2C_MDR_TRX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (msg->len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) flag |= DAVINCI_I2C_MDR_RM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Enable receive or transmit interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) w |= DAVINCI_I2C_IMR_RRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) w |= DAVINCI_I2C_IMR_XRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev->terminate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Write mode register first as needed for correct behaviour
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * occurring before we have loaded DXR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * First byte should be set here, not after interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * because transmit-data-ready interrupt can come before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * NACK-interrupt during sending of previous message and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * ICDXR may have wrong data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * It also saves us one interrupt, slightly faster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Set STT to begin transmit now DXR is loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) flag |= DAVINCI_I2C_MDR_STT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (stop && msg->len != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) flag |= DAVINCI_I2C_MDR_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) time_left = wait_for_completion_timeout(&dev->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev->adapter.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(dev->dev, "controller timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) i2c_recover_bus(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev->buf_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (dev->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* This should be 0 if all bytes were transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * or dev->cmd_err denotes an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(dev->dev, "abnormal termination buf_len=%zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev->buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev->terminate = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev->buf_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* no error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (likely(!dev->cmd_err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* We have an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) i2c_davinci_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (msg->flags & I2C_M_IGNORE_NAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) w |= DAVINCI_I2C_MDR_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * Prepare controller for a transaction and call i2c_davinci_xfer_msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = pm_runtime_get_sync(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_err(dev->dev, "Failed to runtime_get device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pm_runtime_put_noidle(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = i2c_davinci_wait_bus_not_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_warn(dev->dev, "timeout waiting for bus ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pm_runtime_mark_last_busy(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pm_runtime_put_autosuspend(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static u32 i2c_davinci_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static void terminate_read(struct davinci_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) w |= DAVINCI_I2C_MDR_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Throw away data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!dev->terminate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_err(dev->dev, "RDR IRQ while no data requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void terminate_write(struct davinci_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!dev->terminate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Interrupt service routine. This gets called whenever an I2C interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct davinci_i2c_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (pm_runtime_suspended(dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (count++ == 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_warn(dev->dev, "Too much work in one IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) switch (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case DAVINCI_I2C_IVR_AL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Arbitration lost, must retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev->cmd_err |= DAVINCI_I2C_STR_AL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev->buf_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) complete(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) case DAVINCI_I2C_IVR_NACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev->cmd_err |= DAVINCI_I2C_STR_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev->buf_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) complete(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case DAVINCI_I2C_IVR_ARDY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) davinci_i2c_write_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (((dev->buf_len == 0) && (dev->stop != 0)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) w = davinci_i2c_read_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) DAVINCI_I2C_MDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) w |= DAVINCI_I2C_MDR_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) davinci_i2c_write_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) DAVINCI_I2C_MDR_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) complete(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case DAVINCI_I2C_IVR_RDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (dev->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *dev->buf++ =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) davinci_i2c_read_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) DAVINCI_I2C_DRR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (dev->buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) davinci_i2c_write_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) DAVINCI_I2C_STR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) DAVINCI_I2C_IMR_RRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* signal can terminate transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) terminate_read(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case DAVINCI_I2C_IVR_XRDY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (dev->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *dev->buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (dev->buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) w = davinci_i2c_read_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) DAVINCI_I2C_IMR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) w &= ~DAVINCI_I2C_IMR_XRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) davinci_i2c_write_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) DAVINCI_I2C_IMR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* signal can terminate transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) terminate_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) case DAVINCI_I2C_IVR_SCD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) davinci_i2c_write_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) complete(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case DAVINCI_I2C_IVR_AAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_dbg(dev->dev, "Address as slave interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return count ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned long val, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct davinci_i2c_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) i2c_lock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (val == CPUFREQ_PRECHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) davinci_i2c_reset_ctrl(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } else if (val == CPUFREQ_POSTCHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) i2c_davinci_calc_clk_dividers(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) davinci_i2c_reset_ctrl(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) i2c_unlock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return cpufreq_register_notifier(&dev->freq_transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) cpufreq_unregister_notifier(&dev->freq_transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct i2c_algorithm i2c_davinci_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .master_xfer = i2c_davinci_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .functionality = i2c_davinci_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const struct of_device_id davinci_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {.compatible = "ti,davinci-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {.compatible = "ti,keystone-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static int davinci_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct davinci_i2c_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct i2c_bus_recovery_info *rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int r, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) irq = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (irq != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "can't get irq resource ret=%d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev_err(&pdev->dev, "Memory allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) init_completion(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev->pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!dev->pdata && pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u32 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev->pdata = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!dev->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) memcpy(dev->pdata, &davinci_i2c_platform_data_default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) sizeof(struct davinci_i2c_platform_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) &prop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dev->pdata->bus_freq = prop / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev->pdata->has_pfunc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) of_property_read_bool(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "ti,has-pfunc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) } else if (!dev->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev->pdata = &davinci_i2c_platform_data_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (IS_ERR(dev->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (IS_ERR(dev->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return PTR_ERR(dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pm_runtime_set_autosuspend_delay(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) DAVINCI_I2C_PM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pm_runtime_use_autosuspend(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) pm_runtime_enable(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) r = pm_runtime_get_sync(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev_err(dev->dev, "failed to runtime_get device: %d\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) pm_runtime_put_noidle(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) i2c_davinci_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pdev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) goto err_unuse_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) r = i2c_davinci_cpufreq_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_err(&pdev->dev, "failed to register cpufreq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) goto err_unuse_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) i2c_set_adapdata(adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) adap->class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) adap->algo = &i2c_davinci_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) adap->timeout = DAVINCI_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (dev->pdata->has_pfunc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) else if (dev->pdata->gpio_recovery) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) rinfo = &davinci_i2c_gpio_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) adap->bus_recovery_info = rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) GPIOD_OUT_HIGH_OPEN_DRAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (IS_ERR(rinfo->scl_gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) r = PTR_ERR(rinfo->scl_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) goto err_unuse_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (IS_ERR(rinfo->sda_gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) r = PTR_ERR(rinfo->sda_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) goto err_unuse_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) adap->nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) r = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) goto err_unuse_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) pm_runtime_mark_last_busy(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pm_runtime_put_autosuspend(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) err_unuse_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pm_runtime_dont_use_autosuspend(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) pm_runtime_put_sync(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pm_runtime_disable(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int davinci_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) i2c_davinci_cpufreq_deregister(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) i2c_del_adapter(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) pm_runtime_dont_use_autosuspend(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pm_runtime_put_sync(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) pm_runtime_disable(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int davinci_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* put I2C into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) davinci_i2c_reset_ctrl(i2c_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int davinci_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* take I2C out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) davinci_i2c_reset_ctrl(i2c_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const struct dev_pm_ops davinci_i2c_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .suspend = davinci_i2c_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .resume = davinci_i2c_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define davinci_i2c_pm_ops (&davinci_i2c_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define davinci_i2c_pm_ops NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MODULE_ALIAS("platform:i2c_davinci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static struct platform_driver davinci_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .probe = davinci_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .remove = davinci_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .name = "i2c_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .pm = davinci_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .of_match_table = davinci_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* I2C may be needed to bring up other drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int __init davinci_i2c_init_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return platform_driver_register(&davinci_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) subsys_initcall(davinci_i2c_init_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static void __exit davinci_i2c_exit_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) platform_driver_unregister(&davinci_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) module_exit(davinci_i2c_exit_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) MODULE_AUTHOR("Texas Instruments India");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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