^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale CPM1/CPM2 I2C interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * moved into proper i2c interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Brad Parker (brad@heeltoe.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Parts from dbox2_i2c.c (cvs.tuxbox.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * (C) 2007 Montavista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Vitaly Bordug <vitb@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Converted to of_platform_device. Renamed to i2c-cpm.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/cpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Try to define this if you have an older CPU (earlier than rev D4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* However, better use a GPIO based bitbang driver in this case :/ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #undef I2C_CHIP_ERRATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CPM_MAX_READ 513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPM_MAXBD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_EB (0x10) /* Big endian mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* I2C parameter RAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct i2c_ram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ushort rbase; /* Rx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ushort tbase; /* Tx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u_char rfcr; /* Rx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u_char tfcr; /* Tx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ushort mrblr; /* Max receive buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) uint rstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) uint rdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ushort rbptr; /* Rx Buffer descriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ushort rbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) uint rxtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) uint tstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) uint tdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ushort tbptr; /* Tx Buffer descriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ushort tbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) uint txtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) char res1[4]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ushort rpbase; /* Relocation pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) char res2[2]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* The following elements are only for CPM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) char res3[4]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) uint sdmatmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2COM_START 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I2COM_MASTER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I2CER_TXE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2CER_BUSY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2CER_TXB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I2CER_RXB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2MOD_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* I2C Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct i2c_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 i2mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 res1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 i2add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 res2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 i2brg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 res3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 i2com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 res4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 i2cer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 res5[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 i2cmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct cpm_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) char *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct platform_device *ofdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint dp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int version; /* CPM1=1, CPM2=2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int cp_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct i2c_reg __iomem *i2c_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct i2c_ram __iomem *i2c_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) wait_queue_head_t i2c_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cbd_t __iomem *tbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cbd_t __iomem *rbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u_char *txbuf[CPM_MAXBD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u_char *rxbuf[CPM_MAXBD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dma_addr_t txdma[CPM_MAXBD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dma_addr_t rxdma[CPM_MAXBD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct cpm_i2c *cpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct i2c_reg __iomem *i2c_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct i2c_adapter *adap = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cpm = i2c_get_adapdata(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) i2c_reg = cpm->i2c_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Clear interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) i = in_8(&i2c_reg->i2cer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) out_8(&i2c_reg->i2cer, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_dbg(&adap->dev, "Interrupt: %x\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) wake_up(&cpm->i2c_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return i ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Set up the I2C parameters in the parameter ram. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (cpm->version == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) out_8(&i2c_ram->tfcr, I2C_EB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) out_8(&i2c_ram->rfcr, I2C_EB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) out_be32(&i2c_ram->rstate, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) out_be32(&i2c_ram->rdp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) out_be16(&i2c_ram->rbptr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) out_be16(&i2c_ram->rbc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) out_be32(&i2c_ram->rxtmp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) out_be32(&i2c_ram->tstate, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) out_be32(&i2c_ram->tdp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) out_be16(&i2c_ram->tbptr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) out_be16(&i2c_ram->tbc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) out_be32(&i2c_ram->txtmp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void cpm_i2c_force_close(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct cpm_i2c *cpm = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) out_8(&i2c_reg->i2cer, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void cpm_i2c_parse_message(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct i2c_msg *pmsg, int num, int tx, int rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cbd_t __iomem *tbdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cbd_t __iomem *rbdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u_char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u_char *tb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u_char *rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct cpm_i2c *cpm = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tbdf = cpm->tbase + tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rbdf = cpm->rbase + rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) addr = i2c_8bit_addr_from_msg(pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) tb = cpm->txbuf[tx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) rb = cpm->rxbuf[rx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Align read buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rb = (u_char *) (((ulong) rb + 1) & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tb[0] = addr; /* Device address byte w/rw flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) out_be16(&tbdf->cbd_sc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!(pmsg->flags & I2C_M_NOSTART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) setbits16(&tbdf->cbd_sc, BD_I2C_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (tx + 1 == num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (pmsg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * To read, we need an empty buffer of the proper length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * All that is used is the first byte for address, the remainder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * is just used for timing (and doesn't really have to exist).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) out_be16(&rbdf->cbd_datlen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (rx + 1 == CPM_MAXBD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) eieio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) setbits16(&tbdf->cbd_sc, BD_SC_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) memcpy(tb+1, pmsg->buf, pmsg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) eieio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int cpm_i2c_check_message(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct i2c_msg *pmsg, int tx, int rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cbd_t __iomem *tbdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cbd_t __iomem *rbdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u_char *tb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u_char *rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct cpm_i2c *cpm = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tbdf = cpm->tbase + tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rbdf = cpm->rbase + rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tb = cpm->txbuf[tx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rb = cpm->rxbuf[rx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Align read buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rb = (u_char *) (((uint) rb + 1) & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) eieio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (pmsg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_dbg(&adap->dev, "I2C read; No ack\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "I2C read; complete but rbuf empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(&adap->dev, "I2C read; Overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) memcpy(pmsg->buf, rb, pmsg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) in_be16(&tbdf->cbd_sc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_dbg(&adap->dev, "I2C write; No ack\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(&adap->dev, "I2C write; Underrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(&adap->dev, "I2C write; Collision\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct cpm_i2c *cpm = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct i2c_msg *pmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int tptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) cbd_t __iomem *tbdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) cbd_t __iomem *rbdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Reset to use first buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tbdf = cpm->tbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rbdf = cpm->rbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) rptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * If there was a collision in the last i2c transaction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Set I2COM_MASTER as it was cleared during collision.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) while (tptr < num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pmsg = &msgs[tptr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (pmsg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) rptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) tptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Start transfer now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Enable RX/TX/Error interupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Chip bug, set enable here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Begin transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) setbits8(&i2c_reg->i2com, I2COM_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) while (tptr < num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Check for outstanding messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_dbg(&adap->dev, "test ready.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pmsg = &msgs[tptr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (pmsg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = wait_event_timeout(cpm->i2c_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 1 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = wait_event_timeout(cpm->i2c_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 1 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(&adap->dev, "I2C transfer: timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_dbg(&adap->dev, "ready.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) tptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (pmsg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #ifdef I2C_CHIP_ERRATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Chip errata, clear enable. This is not needed on rev D4 CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Disabling I2C too early may cause too short stop condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) udelay(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) clrbits8(&i2c_reg->i2mod, I2MOD_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return (num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) cpm_i2c_force_close(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef I2C_CHIP_ERRATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Chip errata, clear enable. This is not needed on rev D4 CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) clrbits8(&i2c_reg->i2mod, I2MOD_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static u32 cpm_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* -----exported algorithm data: ------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct i2c_algorithm cpm_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .master_xfer = cpm_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .functionality = cpm_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* CPM_MAX_READ is also limiting writes according to the code! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const struct i2c_adapter_quirks cpm_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .max_num_msgs = CPM_MAXBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .max_read_len = CPM_MAX_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .max_write_len = CPM_MAX_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const struct i2c_adapter cpm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "i2c-cpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .algo = &cpm_i2c_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .quirks = &cpm_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int cpm_i2c_setup(struct cpm_i2c *cpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct platform_device *ofdev = cpm->ofdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) const u32 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int len, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void __iomem *i2c_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cbd_t __iomem *tbdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) cbd_t __iomem *rbdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned char brg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) init_waitqueue_head(&cpm->i2c_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!cpm->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Install interrupt handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &cpm->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* I2C parameter RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) i2c_base = of_iomap(ofdev->dev.of_node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (i2c_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Check for and use a microcode relocation patch. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cpm->i2c_ram = i2c_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Maybe should use cpm_muram_alloc instead of hardcoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * this in micropatch.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (cpm->i2c_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) iounmap(i2c_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) cpm->version = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) out_be16(i2c_base, cpm->i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) iounmap(i2c_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) cpm->version = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) iounmap(i2c_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* I2C control/status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (cpm->i2c_reg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto out_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!data || len != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto out_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cpm->cp_command = *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (data && len == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cpm->adap.class = *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (data && len == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) cpm->freq = *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cpm->freq = 60000; /* use 60kHz i2c clock by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Allocate space for CPM_MAXBD transmit and receive buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * descriptors in the DP ram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!cpm->dp_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto out_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) cpm->tbase = cpm_muram_addr(cpm->dp_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Allocate TX and RX buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) tbdf = cpm->tbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rbdf = cpm->rbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) for (i = 0; i < CPM_MAXBD; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) CPM_MAX_READ + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &cpm->rxdma[i], GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!cpm->rxbuf[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto out_muram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) cpm->txbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) CPM_MAX_READ + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &cpm->txdma[i], GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!cpm->txbuf[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto out_muram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Initialize Tx/Rx parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cpm_reset_i2c_params(cpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) (u8 __iomem *)cpm->tbase - DPRAM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) (u8 __iomem *)cpm->rbase - DPRAM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * Select an invalid address. Just make sure we don't use loopback mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * the actual i2c bus frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) out_8(&cpm->i2c_reg->i2brg, brg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) out_8(&cpm->i2c_reg->i2mod, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Disable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) out_8(&cpm->i2c_reg->i2cmr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) out_8(&cpm->i2c_reg->i2cer, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) out_muram:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (i = 0; i < CPM_MAXBD; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (cpm->rxbuf[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cpm->rxbuf[i], cpm->rxdma[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (cpm->txbuf[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) cpm->txbuf[i], cpm->txdma[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) cpm_muram_free(cpm->dp_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) out_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) iounmap(cpm->i2c_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) out_ram:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if ((cpm->version == 1) && (!cpm->i2c_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) iounmap(cpm->i2c_ram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (cpm->version == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) cpm_muram_free(cpm->i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) out_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) free_irq(cpm->irq, &cpm->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Shut down I2C. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) out_8(&cpm->i2c_reg->i2cmr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) out_8(&cpm->i2c_reg->i2cer, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) free_irq(cpm->irq, &cpm->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Free all memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) for (i = 0; i < CPM_MAXBD; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) cpm->rxbuf[i], cpm->rxdma[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) cpm->txbuf[i], cpm->txdma[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) cpm_muram_free(cpm->dp_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) iounmap(cpm->i2c_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if ((cpm->version == 1) && (!cpm->i2c_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) iounmap(cpm->i2c_ram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (cpm->version == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) cpm_muram_free(cpm->i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int cpm_i2c_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int result, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct cpm_i2c *cpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) const u32 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!cpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) cpm->ofdev = ofdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) platform_set_drvdata(ofdev, cpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cpm->adap = cpm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) i2c_set_adapdata(&cpm->adap, cpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cpm->adap.dev.parent = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) result = cpm_i2c_setup(cpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_err(&ofdev->dev, "Unable to init hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* register new adapter to i2c module... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) result = i2c_add_numbered_adapter(&cpm->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) goto out_shut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) cpm->adap.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) out_shut:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) cpm_i2c_shutdown(cpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) kfree(cpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int cpm_i2c_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct cpm_i2c *cpm = platform_get_drvdata(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) i2c_del_adapter(&cpm->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) cpm_i2c_shutdown(cpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) kfree(cpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const struct of_device_id cpm_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .compatible = "fsl,cpm1-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .compatible = "fsl,cpm2-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MODULE_DEVICE_TABLE(of, cpm_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static struct platform_driver cpm_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .probe = cpm_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .remove = cpm_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .name = "fsl-i2c-cpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .of_match_table = cpm_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) module_platform_driver(cpm_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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