^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * I2C bus driver for the Cadence I2C controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 - 2014 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Register offsets for the I2C device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Control Register Bit mask definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CDNS_I2C_CR_ACK_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CDNS_I2C_CR_NEA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CDNS_I2C_CR_MS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CDNS_I2C_CR_RW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* 1 = Auto init FIFO to zeroes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CDNS_I2C_CR_CLR_FIFO BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CDNS_I2C_CR_DIVA_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CDNS_I2C_CR_DIVB_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CDNS_I2C_CR_ACK_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CDNS_I2C_CR_MS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Status Register Bit mask definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CDNS_I2C_SR_BA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CDNS_I2C_SR_TXDV BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CDNS_I2C_SR_RXDV BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CDNS_I2C_SR_RXRW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * I2C Address Register Bit mask definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * bits. A write access to this register always initiates a transfer if the I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * is in master mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * I2C Interrupt Registers Bit mask definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CDNS_I2C_IXR_ARB_LOST BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CDNS_I2C_IXR_RX_UNF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CDNS_I2C_IXR_TX_OVF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CDNS_I2C_IXR_RX_OVF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CDNS_I2C_IXR_SLV_RDY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CDNS_I2C_IXR_TO BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CDNS_I2C_IXR_NACK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CDNS_I2C_IXR_DATA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CDNS_I2C_IXR_COMP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CDNS_I2C_IXR_RX_UNF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CDNS_I2C_IXR_TX_OVF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) CDNS_I2C_IXR_RX_OVF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CDNS_I2C_IXR_SLV_RDY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) CDNS_I2C_IXR_TO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CDNS_I2C_IXR_NACK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CDNS_I2C_IXR_DATA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CDNS_I2C_IXR_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CDNS_I2C_IXR_RX_UNF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CDNS_I2C_IXR_TX_OVF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) CDNS_I2C_IXR_RX_OVF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CDNS_I2C_IXR_NACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CDNS_I2C_IXR_RX_UNF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CDNS_I2C_IXR_TX_OVF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CDNS_I2C_IXR_RX_OVF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CDNS_I2C_IXR_NACK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CDNS_I2C_IXR_DATA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) CDNS_I2C_IXR_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CDNS_I2C_IXR_TX_OVF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CDNS_I2C_IXR_RX_OVF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CDNS_I2C_IXR_TO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CDNS_I2C_IXR_NACK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CDNS_I2C_IXR_DATA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CDNS_I2C_IXR_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* timeout for pm runtime autosuspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CDNS_I2C_FIFO_DEPTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* FIFO depth at which the DATA interrupt occurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CDNS_I2C_MAX_TRANSFER_SIZE 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Transfer size in multiples of data interrupt depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DRIVER_NAME "cdns-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CDNS_I2C_DIVA_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CDNS_I2C_DIVB_MAX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CDNS_I2C_TIMEOUT_MAX 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * enum cdns_i2c_mode - I2C Controller current operating mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) enum cdns_i2c_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CDNS_I2C_MODE_SLAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CDNS_I2C_MODE_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * enum cdns_i2c_slave_mode - Slave state when I2C is operating in slave mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum cdns_i2c_slave_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CDNS_I2C_SLAVE_STATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CDNS_I2C_SLAVE_STATE_SEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CDNS_I2C_SLAVE_STATE_RECV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * struct cdns_i2c - I2C device private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @dev: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @membase: Base address of the I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @adap: I2C adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @p_msg: Message pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @err_status: Error status in Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @xfer_done: Transfer complete status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @p_send_buf: Pointer to transmit buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @p_recv_buf: Pointer to receive buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @send_count: Number of bytes still expected to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @recv_count: Number of bytes still expected to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @curr_recv_count: Number of bytes to be received in current transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @input_clk: Input clock to I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @i2c_clk: Maximum I2C clock speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @clk: Pointer to struct clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @clk_rate_change_nb: Notifier block for clock rate changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @quirks: flag for broken hold bit usage in r1p10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @slave: Registered slave instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @dev_mode: I2C operating role(master/slave).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @slave_state: I2C Slave state(idle/read/write).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct cdns_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct i2c_msg *p_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct completion xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned char *p_send_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned char *p_recv_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int send_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int recv_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int curr_recv_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long input_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int i2c_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int bus_hold_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct notifier_block clk_rate_change_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u16 ctrl_reg_diva_divb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct i2c_client *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) enum cdns_i2c_mode dev_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum cdns_i2c_slave_state slave_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct cdns_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_rate_change_nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * cdns_i2c_clear_bus_hold - Clear bus hold bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @id: Pointer to driver data struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Helper to clear the controller's bus hold bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (reg & CDNS_I2C_CR_HOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return (hold_wrkaround &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Clear FIFO and transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Update device mode and state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) id->dev_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case CDNS_I2C_MODE_MASTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Enable i2c master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) cdns_i2c_writereg(id->ctrl_reg_diva_divb |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CDNS_I2C_CR_MASTER_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * This delay is needed to give the IP some time to switch to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * the master mode. With lower values(like 110 us) i2cdetect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * will not detect any slave and without this delay, the IP will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * trigger a timeout interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) usleep_range(115, 125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case CDNS_I2C_MODE_SLAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Enable i2c slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cdns_i2c_writereg(id->ctrl_reg_diva_divb &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CDNS_I2C_CR_SLAVE_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Setting slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) CDNS_I2C_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Enable slave send/receive interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) CDNS_I2C_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Prepare backend for data reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Fetch number of bytes to receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Read data and send to backend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) while (bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Prepare backend for data transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Send data over bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * @ptr: Pointer to I2C device private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * This function handles the data interrupt and transfer complete interrupt of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * the I2C device in slave role.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Return: IRQ_HANDLED always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static irqreturn_t cdns_i2c_slave_isr(void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct cdns_i2c *id = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int isr_status, i2c_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Fetch the interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Ignore masked interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Fetch transfer mode (send/receive) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Handle data send/receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (i2c_status & CDNS_I2C_SR_RXRW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Send data to master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (isr_status & CDNS_I2C_IXR_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cdns_i2c_slave_send_data(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (isr_status & CDNS_I2C_IXR_COMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Receive data from master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (isr_status & CDNS_I2C_IXR_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cdns_i2c_slave_rcv_data(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (isr_status & CDNS_I2C_IXR_COMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) cdns_i2c_slave_rcv_data(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Master indicated xfer stop or fifo underflow/overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * @ptr: Pointer to I2C device private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * This function handles the data interrupt, transfer complete interrupt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * the error interrupts of the I2C device in master role.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Return: IRQ_HANDLED always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static irqreturn_t cdns_i2c_master_isr(void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int isr_status, avail_bytes, updatetx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int bytes_to_send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) bool hold_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct cdns_i2c *id = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Signal completion only after everything is updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int done_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) irqreturn_t status = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) id->err_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Handling nack and arbitration lost interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) done_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) status = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Check if transfer size register needs to be updated again for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * large data receive operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) updatetx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (id->recv_count > id->curr_recv_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) updatetx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* When receiving, handle data interrupt and completion interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (id->p_recv_buf &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ((isr_status & CDNS_I2C_IXR_COMP) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (isr_status & CDNS_I2C_IXR_DATA))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Read data if receive data valid is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CDNS_I2C_SR_RXDV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (id->recv_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *(id->p_recv_buf)++ =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) id->recv_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) id->curr_recv_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Clear hold bit that was set for FIFO control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * if RX data left is less than or equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * FIFO DEPTH unless repeated start is selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (id->recv_count <= CDNS_I2C_FIFO_DEPTH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) !id->bus_hold_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) cdns_i2c_clear_bus_hold(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(id->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "xfer_size reg rollover. xfer aborted!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) id->err_status |= CDNS_I2C_IXR_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (cdns_is_holdquirk(id, hold_quirk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * The controller sends NACK to the slave when transfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * register reaches zero without considering the HOLD bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * This workaround is implemented for large data transfers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * maintain transfer size non-zero while performing a large
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * receive operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (cdns_is_holdquirk(id, hold_quirk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* wait while fifo is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Check number of bytes to be received against maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * transfer size and update register accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) CDNS_I2C_TRANSFER_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CDNS_I2C_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) cdns_i2c_writereg(id->recv_count -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CDNS_I2C_FIFO_DEPTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) id->curr_recv_count = id->recv_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } else if (id->recv_count && !hold_quirk &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) !id->curr_recv_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Set the slave address in address register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) CDNS_I2C_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cdns_i2c_writereg(id->recv_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) id->curr_recv_count = id->recv_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Clear hold (if not repeated start) and signal completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!id->bus_hold_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cdns_i2c_clear_bus_hold(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) done_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) status = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* When sending, handle transfer complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * If there is more data to be sent, calculate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * space available in FIFO and fill with that many bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (id->send_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) avail_bytes = CDNS_I2C_FIFO_DEPTH -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (id->send_count > avail_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) bytes_to_send = avail_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bytes_to_send = id->send_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) while (bytes_to_send--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) cdns_i2c_writereg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) (*(id->p_send_buf)++),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CDNS_I2C_DATA_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) id->send_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * Signal the completion of transaction and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * clear the hold bus bit if there are no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * further messages to be processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) done_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!id->send_count && !id->bus_hold_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) cdns_i2c_clear_bus_hold(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) status = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Update the status for errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (id->err_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) status = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (done_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) complete(&id->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * cdns_i2c_isr - Interrupt handler for the I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * @irq: irq number for the I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * @ptr: void pointer to cdns_i2c structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * This function passes the control to slave/master based on current role of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * i2c controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * Return: IRQ_HANDLED always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct cdns_i2c *id = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return cdns_i2c_slave_isr(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return cdns_i2c_master_isr(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * cdns_i2c_mrecv - Prepare and start a master receive operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * @id: pointer to the i2c device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static void cdns_i2c_mrecv(struct cdns_i2c *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned int isr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) id->p_recv_buf = id->p_msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) id->recv_count = id->p_msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Put the controller in master receive mode and clear the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (id->p_msg->flags & I2C_M_RECV_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) id->curr_recv_count = id->recv_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * Check for the message size against FIFO depth and set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * 'hold bus' bit if it is greater than FIFO depth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ctrl_reg |= CDNS_I2C_CR_HOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Clear the interrupts in interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * The no. of bytes to receive is checked against the limit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * max transfer size. Set transfer size register with no of bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * receive if it is less than transfer size and transfer size if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * it is more. Enable the interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Set the slave address in address register - triggers operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) CDNS_I2C_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Clear the bus hold flag if bytes to receive is less than FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!id->bus_hold_flag &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) cdns_i2c_clear_bus_hold(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * cdns_i2c_msend - Prepare and start a master send operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * @id: pointer to the i2c device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static void cdns_i2c_msend(struct cdns_i2c *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int avail_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned int bytes_to_send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned int isr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) id->p_recv_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) id->p_send_buf = id->p_msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) id->send_count = id->p_msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Set the controller in Master transmit mode and clear the FIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ctrl_reg &= ~CDNS_I2C_CR_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Check for the message size against FIFO depth and set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * 'hold bus' bit if it is greater than FIFO depth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (id->send_count > CDNS_I2C_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ctrl_reg |= CDNS_I2C_CR_HOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Clear the interrupts in interrupt status register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * Calculate the space available in FIFO. Check the message length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * against the space available, and fill the FIFO accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Enable the interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) avail_bytes = CDNS_I2C_FIFO_DEPTH -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (id->send_count > avail_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) bytes_to_send = avail_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) bytes_to_send = id->send_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) while (bytes_to_send--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) id->send_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * Clear the bus hold flag if there is no more data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * and if it is the last message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (!id->bus_hold_flag && !id->send_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) cdns_i2c_clear_bus_hold(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Set the slave address in address register - triggers operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) CDNS_I2C_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * cdns_i2c_master_reset - Reset the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * @adap: pointer to the i2c adapter driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * This function cleanup the fifos, clear the hold bit and status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * and disable the interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void cdns_i2c_master_reset(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct cdns_i2c *id = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Disable the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Clear the hold bit and fifos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) regval &= ~CDNS_I2C_CR_HOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) regval |= CDNS_I2C_CR_CLR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Update the transfercount register to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Clear the interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Clear the status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) id->p_msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) id->err_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) reinit_completion(&id->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Check for the TEN Bit mode on each msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (reg & CDNS_I2C_CR_NEA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!(reg & CDNS_I2C_CR_NEA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Check for the R/W flag on each msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cdns_i2c_mrecv(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) cdns_i2c_msend(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* Wait for the signal of completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) cdns_i2c_master_reset(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(id->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "timeout waiting on completion\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) CDNS_I2C_IDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* If it is bus arbitration error, try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * cdns_i2c_master_xfer - The main i2c transfer function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * @adap: pointer to the i2c adapter driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * @msgs: pointer to the i2c message structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * @num: the number of messages to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * Initiates the send/recv activity based on the transfer message received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * Return: number of msgs processed on success, negative error otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) int ret, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct cdns_i2c *id = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) bool hold_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) bool change_role = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = pm_runtime_resume_and_get(id->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Check i2c operating mode and switch if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Set mode to master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Mark flag to change role once xfer is completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) change_role = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Check if the bus is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * Set the flag to one when multiple messages are to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * processed with a repeated start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (num > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * This controller does not give completion interrupt after a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * master receive message if HOLD bit is set (repeated start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * resulting in SW timeout. Hence, if a receive message is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * followed by any other message, an error is returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * indicating that this sequence is not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) for (count = 0; (count < num - 1 && hold_quirk); count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (msgs[count].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_warn(adap->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "Can't do repeated start after a receive message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) id->bus_hold_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) reg |= CDNS_I2C_CR_HOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) id->bus_hold_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Process the msg one by one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) for (count = 0; count < num; count++, msgs++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (count == (num - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) id->bus_hold_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = cdns_i2c_process_msg(id, msgs, adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* Report the other error interrupts to application */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (id->err_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) cdns_i2c_master_reset(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (id->err_status & CDNS_I2C_IXR_NACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Switch i2c mode to slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (change_role)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) pm_runtime_mark_last_busy(id->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) pm_runtime_put_autosuspend(id->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * cdns_i2c_func - Returns the supported features of the I2C driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * @adap: pointer to the i2c adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * Return: 32 bit value, each bit corresponding to a feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static u32 cdns_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) I2C_FUNC_SMBUS_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) func |= I2C_FUNC_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int cdns_reg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (id->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (slave->flags & I2C_CLIENT_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return -EAFNOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = pm_runtime_resume_and_get(id->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* Store slave information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) id->slave = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* Enable I2C slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static int cdns_unreg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) pm_runtime_put(id->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Remove slave information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) id->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Enable I2C master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const struct i2c_algorithm cdns_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .master_xfer = cdns_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .functionality = cdns_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .reg_slave = cdns_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .unreg_slave = cdns_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * cdns_i2c_calc_divs - Calculate clock dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * @f: I2C clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * @input_clk: Input clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * @a: First divider (return value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * @b: Second divider (return value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * f is used as input and output variable. As input it is used as target I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * frequency. On function exit f holds the actually resulting I2C frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * Return: 0 on success, negative errno otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned int *a, unsigned int *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) unsigned int last_error, current_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* calculate (divisor_a+1) x (divisor_b+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) temp = input_clk / (22 * fscl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * If the calculated value is negative or 0, the fscl input is out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * range. Return error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) last_error = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) div_b--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (actual_fscl > fscl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) (fscl - actual_fscl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (last_error > current_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) calc_div_a = div_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) calc_div_b = div_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) best_fscl = actual_fscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) last_error = current_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) *a = calc_div_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) *b = calc_div_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) *f = best_fscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * @clk_in: I2C clock input frequency in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * @id: Pointer to the I2C device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * The device must be idle rather than busy transferring data before setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * these device options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * The data rate is set by values in the control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * The formula for determining the correct register values is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * See the hardware data sheet for a full explanation of setting the serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * clock rate. The clock can not be faster than the input clock divide by 22.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * The two most common clock rates are 100KHz and 400KHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * Return: 0 on success, negative error otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) unsigned int div_a, div_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) unsigned long fscl = id->i2c_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) (div_b << CDNS_I2C_CR_DIVB_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) CDNS_I2C_CR_DIVB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * cdns_i2c_clk_notifier_cb - Clock rate change callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * @nb: Pointer to notifier block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * @event: Notification reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * @data: Pointer to notification data object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * This function is called when the cdns_i2c input clock frequency changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * The callback checks whether a valid bus frequency can be generated after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * change. If so, the change is acknowledged, otherwise the change is aborted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * New dividers are written to the HW in the pre- or post change notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * depending on the scaling direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * to acknowledge the change, NOTIFY_DONE if the notification is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * considered irrelevant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct cdns_i2c *id = to_cdns_i2c(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (pm_runtime_suspended(id->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) unsigned long input_clk = ndata->new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) unsigned long fscl = id->i2c_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) unsigned int div_a, div_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_warn(id->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "clock rate change rejected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return NOTIFY_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* scale up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (ndata->new_rate > ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) cdns_i2c_setclk(ndata->new_rate, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) id->input_clk = ndata->new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* scale down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (ndata->new_rate < ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) cdns_i2c_setclk(ndata->new_rate, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case ABORT_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* scale up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (ndata->new_rate > ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) cdns_i2c_setclk(ndata->old_rate, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * cdns_i2c_runtime_suspend - Runtime suspend method for the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * Put the driver into low power mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct cdns_i2c *xi2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) clk_disable(xi2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * cdns_i2c_runtime_resume - Runtime resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * Runtime resume callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct cdns_i2c *xi2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ret = clk_enable(xi2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dev_err(dev, "Cannot enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) cdns_i2c_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const struct cdns_platform_data r1p10_i2c_def = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static const struct of_device_id cdns_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) { .compatible = "cdns,i2c-r1p14",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) { /* end of table */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * cdns_i2c_probe - Platform registration call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * @pdev: Handle to the platform device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * This function does all the memory allocation and registration for the i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * device. User can modify the address mode to 10 bit address mode using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * ioctl call with option I2C_TENBIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * Return: 0 on success, negative error otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int cdns_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct resource *r_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct cdns_i2c *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) id->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) platform_set_drvdata(pdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (match && match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) const struct cdns_platform_data *data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) id->quirks = data->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (IS_ERR(id->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return PTR_ERR(id->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) id->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) id->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) id->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) id->adap.algo = &cdns_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) id->adap.timeout = CDNS_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) id->adap.retries = 3; /* Default retry value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) id->adap.algo_data = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) id->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) init_completion(&id->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) snprintf(id->adap.name, sizeof(id->adap.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) "Cadence I2C at %08lx", (unsigned long)r_mem->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) id->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (IS_ERR(id->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (PTR_ERR(id->clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_err(&pdev->dev, "input clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return PTR_ERR(id->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = clk_prepare_enable(id->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) dev_err(&pdev->dev, "Unable to enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) pm_runtime_use_autosuspend(id->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) pm_runtime_set_active(id->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pm_runtime_enable(id->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) id->input_clk = clk_get_rate(id->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) &id->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Set initial mode to master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) id->dev_mode = CDNS_I2C_MODE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) cdns_i2c_writereg(CDNS_I2C_CR_MASTER_EN_MASK, CDNS_I2C_CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ret = cdns_i2c_setclk(id->input_clk, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) goto err_clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) DRIVER_NAME, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) goto err_clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * Cadence I2C controller has a bug wherein it generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * invalid read transaction after HW timeout in master receiver mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * HW timeout is not used by this driver and the interrupt is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * But the feature itself cannot be disabled. Hence maximum value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * is written to this register to reduce the chances of error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret = i2c_add_adapter(&id->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) goto err_clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) err_clk_dis:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) clk_disable_unprepare(id->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * cdns_i2c_remove - Unregister the device after releasing the resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * @pdev: Handle to the platform device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * This function frees all the resources allocated to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static int cdns_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct cdns_i2c *id = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) i2c_del_adapter(&id->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) clk_disable_unprepare(id->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static struct platform_driver cdns_i2c_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .of_match_table = cdns_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .pm = &cdns_i2c_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .probe = cdns_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .remove = cdns_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) module_platform_driver(cdns_i2c_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) MODULE_AUTHOR("Xilinx Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) MODULE_DESCRIPTION("Cadence I2C bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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