^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define N_DATA_REGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * data register whereas STB SoCs use 4 byte per data register transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * account for this difference in total count per transaction and mask to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BSC_CNT_REG1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* BSC CTL register field definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BSC_CTL_REG_DTF_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BSC_CTL_REG_SCL_SEL_MASK 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BSC_CTL_REG_SCL_SEL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BSC_CTL_REG_INT_EN_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BSC_CTL_REG_INT_EN_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BSC_CTL_REG_DIV_CLK_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BSC_IIC_EN_RESTART_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BSC_IIC_EN_NOSTART_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BSC_IIC_EN_NOSTOP_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BSC_IIC_EN_NOACK_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BSC_IIC_EN_INTRP_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BSC_IIC_EN_ENABLE_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* BSC_CTLHI control register field definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_TIMEOUT 100 /* msecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Condition mask used for non combined transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define COND_RESTART BSC_IIC_EN_RESTART_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define COND_NOSTART BSC_IIC_EN_NOSTART_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* BSC data transfer direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DTF_WR_MASK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DTF_RD_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* BSC data transfer direction combined format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DTF_RD_WR_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DTF_WR_RD_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define INT_ENABLE true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define INT_DISABLE false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* BSC block register map structure to cache fields to be written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct bsc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 chip_address; /* slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 data_in[N_DATA_REGS]; /* tx data buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 cnt_reg; /* rx/tx data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 ctl_reg; /* control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 iic_enable; /* xfer enable and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 data_out[N_DATA_REGS]; /* rx data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 ctlhi_reg; /* more control fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 scl_param; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct bsc_clk_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 scl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum bsc_xfer_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CMD_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CMD_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CMD_WR_NOACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) CMD_RD_NOACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static char const *cmd_string[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [CMD_WR] = "WR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [CMD_RD] = "RD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [CMD_WR_NOACK] = "WR NOACK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [CMD_RD_NOACK] = "RD NOACK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum bus_speeds {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SPD_375K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SPD_390K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SPD_187K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SPD_200K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SPD_93K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SPD_97K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SPD_46K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SPD_50K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct bsc_clk_param bsc_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [SPD_375K] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .hz = 375000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .div_mask = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [SPD_390K] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .hz = 390000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .div_mask = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [SPD_187K] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .hz = 187500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .div_mask = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [SPD_200K] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .hz = 200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .div_mask = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [SPD_93K] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .hz = 93750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .div_mask = BSC_CTL_REG_DIV_CLK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [SPD_97K] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .hz = 97500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .div_mask = BSC_CTL_REG_DIV_CLK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [SPD_46K] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .hz = 46875,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .div_mask = BSC_CTL_REG_DIV_CLK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [SPD_50K] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .hz = 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .div_mask = BSC_CTL_REG_DIV_CLK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct brcmstb_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct bsc_regs *bsc_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int data_regsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* register accessors for both be and le cpu arch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define __bsc_readl(_reg) ioread32be(_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define __bsc_readl(_reg) ioread32(_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define bsc_readl(_dev, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define bsc_writel(_dev, _val, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return (N_DATA_REGS * dev->data_regsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return dev->data_regsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bool int_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (int_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Enable BSC CTL interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Disable BSC CTL interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct brcmstb_i2c_dev *dev = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 status_iic_intrp = bsc_readl(dev, iic_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) status_bsc_ctl, status_iic_intrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) complete(&dev->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_dbg(dev->device, "isr handled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Wait for device to be ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* i2c xfer completion function, handles both irq and polling mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (dev->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!wait_for_completion_timeout(&dev->done, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* we are in polling mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 bsc_intrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned long time_left = jiffies + timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) bsc_intrp = bsc_readl(dev, iic_enable) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) BSC_IIC_EN_INTRP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (time_after(jiffies, time_left)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } while (!bsc_intrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (dev->irq < 0 || ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Set xfer START/STOP conditions for subsequent transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 cond_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 regval = dev->bsc_regmap->iic_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Send I2C request check completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) enum bsc_xfer_cmd cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct bsc_regs *pi2creg = dev->bsc_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Make sure the hardware is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rc = brcmstb_i2c_wait_if_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* only if we are in interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (dev->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) reinit_completion(&dev->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* enable BSC CTL interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* initiate transfer by setting iic_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bsc_writel(dev, pi2creg->iic_enable, iic_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Wait for transaction to finish or timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rc = brcmstb_i2c_wait_for_completion(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_dbg(dev->device, "intr timeout for cmd %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cmd_string[cmd]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto cmd_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if ((cmd == CMD_RD || cmd == CMD_WR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) rc = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_dbg(dev->device, "controller received NOACK intr for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cmd_string[cmd]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cmd_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bsc_writel(dev, 0, cnt_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) bsc_writel(dev, 0, iic_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Actual data transfer through the BSC master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 *buf, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct i2c_msg *pmsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int cnt, byte, i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enum bsc_xfer_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct bsc_regs *pi2creg = dev->bsc_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int data_regsz = brcmstb_i2c_get_data_regsz(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* see if the transaction needs to check NACK conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (no_ack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) : CMD_WR_NOACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* set data transfer direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* set the read/write length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (len << BSC_CNT_REG1_SHIFT), cnt_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Write data into data_in register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) for (byte = 0; byte < data_regsz; byte++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) word >>= BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if ((cnt + byte) < len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) word |= buf[cnt + byte] <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) (BITS_PER_BYTE * (data_regsz - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) bsc_writel(dev, word, data_in[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Initiate xfer, the function will return on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rc = brcmstb_send_i2c_cmd(dev, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_dbg(dev->device, "%s failure", cmd_string[cmd]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Read data from data_out register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 data = bsc_readl(dev, data_out[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) for (byte = 0; byte < data_regsz &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) (byte + cnt) < len; byte++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) buf[cnt + byte] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) data >>= BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Write a single byte of data to the i2c bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u8 *buf, unsigned int nak_expected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bsc_writel(dev, 1, cnt_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bsc_writel(dev, *buf, data_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return brcmstb_send_i2c_cmd(dev, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Send i2c address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* First byte is 11110XX0 where XX is upper 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) addr = 0xF0 | ((msg->addr & 0x300) >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) bsc_writel(dev, addr, chip_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Second byte is the remaining 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) addr = msg->addr & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* For read, send restart without stop condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) brcmstb_set_i2c_start_stop(dev, COND_RESTART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) | COND_NOSTOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Then re-send the first byte with the read bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) bsc_writel(dev, addr, chip_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Master transfer function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct i2c_msg *pmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int bytes_to_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 *tmp_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int xfersz = brcmstb_i2c_get_xfersz(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 cond, cond_per_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Loop through all messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pmsg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) len = pmsg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) tmp_buf = pmsg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_dbg(dev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "msg# %d/%d flg %x buf %x len %d\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) num - 1, pmsg->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cond = ~COND_START_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cond = COND_RESTART | COND_NOSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) brcmstb_set_i2c_start_stop(dev, cond);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Send slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!(pmsg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) rc = brcmstb_i2c_do_addr(dev, pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_dbg(dev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "NACK for addr %2.2x msg#%d rc = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pmsg->addr, i, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cond_per_msg = cond;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Perform data transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bytes_to_xfer = min(len, xfersz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (len <= xfersz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (i == (num - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) cond_per_msg = cond_per_msg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ~(COND_RESTART | COND_NOSTOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cond_per_msg = cond;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cond_per_msg = (cond_per_msg & ~COND_RESTART) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) COND_NOSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) brcmstb_set_i2c_start_stop(dev, cond_per_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) bytes_to_xfer, pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) len -= bytes_to_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) tmp_buf += bytes_to_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) cond_per_msg = COND_NOSTART | COND_NOSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rc = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const struct i2c_algorithm brcmstb_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .master_xfer = brcmstb_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .functionality = brcmstb_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 clk_freq_hz = dev->clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) for (i = 0; i < num_speeds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (bsc_clk[i].hz == clk_freq_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) | BSC_CTL_REG_DIV_CLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) bsc_clk[i].div_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* in case we did not get find a valid speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (i == num_speeds) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) BSC_CTL_REG_SCL_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) bsc_clk[i].hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* set 4 byte data in/out xfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* set bus speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) brcmstb_i2c_set_bus_speed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define AUTOI2C_CTRL0 0x26c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define AUTOI2C_CTRL0_RELEASE_BSC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int bcm2711_release_bsc(struct brcmstb_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct platform_device *pdev = to_platform_device(dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct resource *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) void __iomem *autoi2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Map hardware registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) iomem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "auto-i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) autoi2c = devm_ioremap_resource(&pdev->dev, iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (IS_ERR(autoi2c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return PTR_ERR(autoi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) writel(AUTOI2C_CTRL0_RELEASE_BSC, autoi2c + AUTOI2C_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) devm_iounmap(&pdev->dev, autoi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* We need to reset the controller after the release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev->bsc_regmap->iic_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) bsc_writel(dev, dev->bsc_regmap->iic_enable, iic_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int brcmstb_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct brcmstb_i2c_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct resource *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) const char *int_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Allocate memory for private data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!dev->bsc_regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev->device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) init_completion(&dev->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Map hardware registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev->base = devm_ioremap_resource(dev->device, iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (IS_ERR(dev->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto probe_errorout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (of_device_is_compatible(dev->device->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "brcm,bcm2711-hdmi-i2c")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) rc = bcm2711_release_bsc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) goto probe_errorout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) rc = of_property_read_string(dev->device->of_node, "interrupt-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) &int_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Get the interrupt number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev->irq = platform_get_irq_optional(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* disable the bsc interrupt line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* register the ISR handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (dev->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int_name ? int_name : pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_dbg(dev->device, "falling back to polling mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (of_property_read_u32(dev->device->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "clock-frequency", &dev->clk_freq_hz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_warn(dev->device, "setting clock-frequency@%dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) bsc_clk[0].hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev->clk_freq_hz = bsc_clk[0].hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* set the data in/out register size for compatible SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (of_device_is_compatible(dev->device->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "brcm,brcmper-i2c"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev->data_regsz = sizeof(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev->data_regsz = sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) brcmstb_i2c_set_bsc_reg_defaults(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Add the i2c adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) i2c_set_adapdata(adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (int_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) strlcat(adap->name, int_name, sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) adap->algo = &brcmstb_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) rc = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) goto probe_errorout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_info(dev->device, "%s@%dhz registered in %s mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int_name ? int_name : " ", dev->clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) (dev->irq >= 0) ? "interrupt" : "polling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) probe_errorout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int brcmstb_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) i2c_del_adapter(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int brcmstb_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) i2c_mark_adapter_suspended(&i2c_dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int brcmstb_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) i2c_mark_adapter_resumed(&i2c_dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) brcmstb_i2c_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const struct of_device_id brcmstb_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {.compatible = "brcm,brcmstb-i2c"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {.compatible = "brcm,brcmper-i2c"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {.compatible = "brcm,bcm2711-hdmi-i2c"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static struct platform_driver brcmstb_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .name = "brcmstb-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .of_match_table = brcmstb_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .pm = &brcmstb_i2c_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .probe = brcmstb_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .remove = brcmstb_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) module_platform_driver(brcmstb_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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