Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * BCM2835 master mode driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define BCM2835_I2C_C		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define BCM2835_I2C_S		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define BCM2835_I2C_DLEN	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define BCM2835_I2C_A		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define BCM2835_I2C_FIFO	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define BCM2835_I2C_DIV		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define BCM2835_I2C_DEL		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * 16-bit field for the number of SCL cycles to wait after rising SCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * before deciding the slave is not responding. 0 disables the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * timeout detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define BCM2835_I2C_CLKT	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define BCM2835_I2C_C_READ	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define BCM2835_I2C_C_CLEAR	BIT(4) /* bits 4 and 5 both clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define BCM2835_I2C_C_ST	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define BCM2835_I2C_C_INTD	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define BCM2835_I2C_C_INTT	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define BCM2835_I2C_C_INTR	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define BCM2835_I2C_C_I2CEN	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define BCM2835_I2C_S_TA	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define BCM2835_I2C_S_DONE	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define BCM2835_I2C_S_TXW	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BCM2835_I2C_S_RXR	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define BCM2835_I2C_S_TXD	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define BCM2835_I2C_S_RXD	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define BCM2835_I2C_S_TXE	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define BCM2835_I2C_S_RXF	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BCM2835_I2C_S_ERR	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define BCM2835_I2C_S_CLKT	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define BCM2835_I2C_S_LEN	BIT(10) /* Fake bit for SW error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BCM2835_I2C_FEDL_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define BCM2835_I2C_REDL_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define BCM2835_I2C_CDIV_MIN	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define BCM2835_I2C_CDIV_MAX	0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct bcm2835_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct i2c_msg *curr_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct clk *bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int num_msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 msg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u8 *msg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	size_t msg_buf_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				      u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	writel(val, i2c_dev->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return readl(i2c_dev->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) struct clk_bcm2835_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct bcm2835_i2c_dev *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int clk_bcm2835_i2c_calc_divider(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 divider = DIV_ROUND_UP(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * Per the datasheet, the register is always interpreted as an even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * number, by rounding down. In other words, the LSB is ignored. So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * if the LSB is set, increment the divider to avoid any issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (divider & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		divider++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if ((divider < BCM2835_I2C_CDIV_MIN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	    (divider > BCM2835_I2C_CDIV_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 redl, fedl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (divider == -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * Number of core clocks to wait after falling edge before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * outputting the next data bit.  Note that both FEDL and REDL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 * can't be greater than CDIV/2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	fedl = max(divider / 16, 1u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * Number of core clocks to wait after rising edge before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * sampling the next incoming data bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	redl = max(divider / 4, 1u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			   (fedl << BCM2835_I2C_FEDL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			   (redl << BCM2835_I2C_REDL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static long clk_bcm2835_i2c_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return DIV_ROUND_UP(*parent_rate, divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 						unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	return DIV_ROUND_UP(parent_rate, divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct clk_ops clk_bcm2835_i2c_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.set_rate = clk_bcm2835_i2c_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.round_rate = clk_bcm2835_i2c_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.recalc_rate = clk_bcm2835_i2c_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct clk *bcm2835_i2c_register_div(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 					struct clk *mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 					struct bcm2835_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct clk_bcm2835_i2c *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	const char *mclk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	snprintf(name, sizeof(name), "%s_div", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	mclk_name = __clk_get_name(mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	init.ops = &clk_bcm2835_i2c_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	init.parent_names = (const char* []) { mclk_name };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	priv->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	priv->i2c_dev = i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return devm_clk_register(dev, &priv->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	while (i2c_dev->msg_buf_remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		if (!(val & BCM2835_I2C_S_TXD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				   *i2c_dev->msg_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		i2c_dev->msg_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		i2c_dev->msg_buf_remaining--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	while (i2c_dev->msg_buf_remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		if (!(val & BCM2835_I2C_S_RXD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		*i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 						      BCM2835_I2C_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		i2c_dev->msg_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		i2c_dev->msg_buf_remaining--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * Repeated Start Condition (Sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  * talks about reading from a slave with 10 bit address. This is achieved by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * issue a read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * firmware actually does it using polling and says that it's a workaround for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  * a problem in the state machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * It turns out that it is possible to use the TXW interrupt to know when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * transfer is active, provided the FIFO has not been prefilled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct i2c_msg *msg = i2c_dev->curr_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	bool last_msg = (i2c_dev->num_msgs == 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (!i2c_dev->num_msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	i2c_dev->num_msgs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	i2c_dev->msg_buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	i2c_dev->msg_buf_remaining = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		c |= BCM2835_I2C_C_INTT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (last_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		c |= BCM2835_I2C_C_INTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	i2c_dev->curr_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	i2c_dev->num_msgs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	i2c_dev->msg_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	i2c_dev->msg_buf_remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * Note about I2C_C_CLEAR on error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * the state machine to send a NACK and a STOP. Since we're setting CLEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * without I2CEN, that NACK will be hanging around queued up for next time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * we start the engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct bcm2835_i2c_dev *i2c_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	u32 val, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		i2c_dev->msg_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		goto complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (val & BCM2835_I2C_S_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (!i2c_dev->curr_msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		} else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			bcm2835_drain_rxfifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			i2c_dev->msg_err = BCM2835_I2C_S_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			i2c_dev->msg_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		goto complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (val & BCM2835_I2C_S_TXW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (!i2c_dev->msg_buf_remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			goto complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		bcm2835_fill_txfifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			i2c_dev->curr_msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			bcm2835_i2c_start_transfer(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (val & BCM2835_I2C_S_RXR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		if (!i2c_dev->msg_buf_remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			goto complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		bcm2835_drain_rxfifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) complete:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			   BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	complete(&i2c_dev->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			    int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	for (i = 0; i < (num - 1); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		if (msgs[i].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			dev_warn_once(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 				      "only one read message supported, has to be last\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	i2c_dev->curr_msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	i2c_dev->num_msgs = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	reinit_completion(&i2c_dev->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	bcm2835_i2c_start_transfer(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	time_left = wait_for_completion_timeout(&i2c_dev->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 						adap->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	bcm2835_i2c_finish_transfer(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 				   BCM2835_I2C_C_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (!i2c_dev->msg_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct i2c_algorithm bcm2835_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.master_xfer	= bcm2835_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.functionality	= bcm2835_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  * The BCM2835 was reported to have problems with clock stretching:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  * https://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)  * https://www.raspberrypi.org/forums/viewtopic.php?p=146272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.flags = I2C_AQ_NO_CLK_STRETCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int bcm2835_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	struct bcm2835_i2c_dev *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	struct resource *mem, *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	u32 bus_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (!i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	platform_set_drvdata(pdev, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	i2c_dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	init_completion(&i2c_dev->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (IS_ERR(i2c_dev->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		return PTR_ERR(i2c_dev->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	mclk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (IS_ERR(mclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		return dev_err_probe(&pdev->dev, PTR_ERR(mclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 				     "Could not get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	i2c_dev->bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	if (IS_ERR(i2c_dev->bus_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		dev_err(&pdev->dev, "Could not register clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		return PTR_ERR(i2c_dev->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 				   &bus_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			 "Could not read clock-frequency property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	ret = clk_set_rate_exclusive(i2c_dev->bus_clk, bus_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		dev_err(&pdev->dev, "Could not set clock frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	ret = clk_prepare_enable(i2c_dev->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		dev_err(&pdev->dev, "Couldn't prepare clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		dev_err(&pdev->dev, "No IRQ resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	i2c_dev->irq = irq->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 			  dev_name(&pdev->dev), i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		dev_err(&pdev->dev, "Could not request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	adap = &i2c_dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	i2c_set_adapdata(adap, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	adap->class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	snprintf(adap->name, sizeof(adap->name), "bcm2835 (%s)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		 of_node_full_name(pdev->dev.of_node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	adap->algo = &bcm2835_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	adap->quirks = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	 * Disable the hardware clock stretching timeout. SMBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	 * specifies a limit for how long the device can stretch the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	 * clock, but core I2C doesn't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_CLKT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		free_irq(i2c_dev->irq, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int bcm2835_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	clk_rate_exclusive_put(i2c_dev->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	clk_disable_unprepare(i2c_dev->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	free_irq(i2c_dev->irq, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	i2c_del_adapter(&i2c_dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct of_device_id bcm2835_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	{ .compatible = "brcm,bcm2711-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	{ .compatible = "brcm,bcm2835-i2c", .data = &bcm2835_i2c_quirks },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static struct platform_driver bcm2835_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	.probe		= bcm2835_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	.remove		= bcm2835_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		.name	= "i2c-bcm2835",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		.of_match_table = bcm2835_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) module_platform_driver(bcm2835_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_ALIAS("platform:i2c-bcm2835");