^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2013 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Hardware register offsets and field defintions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CS_OFFSET 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CS_ACK_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CS_ACK_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CS_ACK_CMD_GEN_START 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CS_ACK_CMD_GEN_RESTART 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CS_CMD_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CS_CMD_CMD_NO_ACTION 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CS_CMD_CMD_START_RESTART 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CS_CMD_CMD_STOP 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CS_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CS_EN_CMD_ENABLE_BSC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TIM_OFFSET 0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TIM_PRESCALE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TIM_P_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TIM_NO_DIV_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TIM_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DAT_OFFSET 0x00000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TOUT_OFFSET 0x0000002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TXFCR_OFFSET 0x0000003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TXFCR_FIFO_FLUSH_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TXFCR_FIFO_EN_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IER_OFFSET 0x00000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IER_READ_COMPLETE_INT_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IER_I2C_INT_EN_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IER_FIFO_INT_EN_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IER_NOACK_EN_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ISR_OFFSET 0x00000048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ISR_RESERVED_MASK 0xffffff60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ISR_CMDBUSY_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ISR_READ_COMPLETE_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ISR_SES_DONE_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ISR_ERR_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ISR_TXFIFOEMPTY_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ISR_NOACK_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLKEN_OFFSET 0x0000004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLKEN_M_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLKEN_N_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLKEN_CLKEN_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FIFO_STATUS_OFFSET 0x00000054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HSTIM_OFFSET 0x00000058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HSTIM_HS_MODE_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HSTIM_HS_HOLD_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HSTIM_HS_HIGH_PHASE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HSTIM_HS_SETUP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PADCTL_OFFSET 0x0000005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PADCTL_PAD_OUT_EN_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RXFCR_OFFSET 0x00000068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RXFCR_NACK_EN_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RXFCR_READ_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RXFIFORDOUT_OFFSET 0x0000006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Locally used constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MAX_RX_FIFO_SIZE 64U /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MAX_TX_FIFO_SIZE 64U /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STD_EXT_CLK_FREQ 13000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HS_EXT_CLK_FREQ 104000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MASTERCODE 0x08 /* Mastercodes are 0000_1xxxb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define I2C_TIMEOUT 100 /* msecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Operations that can be commanded to the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum bcm_kona_cmd_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) BCM_CMD_NOACTION = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) BCM_CMD_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) BCM_CMD_RESTART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) BCM_CMD_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum bus_speed_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) BCM_SPD_100K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) BCM_SPD_400K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BCM_SPD_1MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum hs_bus_speed_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BCM_SPD_3P4MHZ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Internal divider settings for standard mode, fast mode and fast mode plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct bus_speed_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) uint8_t time_m; /* Number of cycles for setup time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint8_t time_n; /* Number of cycles for hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint8_t prescale; /* Prescale divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) uint8_t time_p; /* Timing coefficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uint8_t no_div; /* Disable clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint8_t time_div; /* Post-prescale divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Internal divider settings for high-speed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct hs_bus_speed_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) uint8_t hs_hold; /* Number of clock cycles SCL stays low until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) the end of bit period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) uint8_t hs_high_phase; /* Number of clock cycles SCL stays high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) before it falls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) uint8_t hs_setup; /* Number of clock cycles SCL stays low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) before it rises */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) uint8_t prescale; /* Prescale divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint8_t time_p; /* Timing coefficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) uint8_t no_div; /* Disable clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint8_t time_div; /* Post-prescale divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct bus_speed_cfg std_cfg_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct hs_bus_speed_cfg hs_cfg_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct bcm_kona_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct clk *external_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct bus_speed_cfg *std_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const struct hs_bus_speed_cfg *hs_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) enum bcm_kona_cmd_t cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_dbg(dev->device, "%s, %d\n", __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case BCM_CMD_NOACTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev->base + CS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case BCM_CMD_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev->base + CS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case BCM_CMD_RESTART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev->base + CS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case BCM_CMD_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev->base + CS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(dev->device, "Unknown command %d\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev->base + CLKEN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev->base + CLKEN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static irqreturn_t bcm_kona_i2c_isr(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct bcm_kona_i2c_dev *dev = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) uint32_t status = readl(dev->base + ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if ((status & ~ISR_RESERVED_MASK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Must flush the TX FIFO when NAK detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (status & ISR_NOACK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev->base + TXFCR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) complete(&dev->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Wait for ISR_CMDBUSY_MASK to go low before writing to CS, DAT, or RCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int bcm_kona_i2c_wait_if_busy(struct bcm_kona_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_err(dev->device, "CMDBUSY timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Send command to I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) enum bcm_kona_cmd_t cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Make sure the hardware is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) rc = bcm_kona_i2c_wait_if_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Unmask the session done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Mark as incomplete before sending the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) reinit_completion(&dev->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Send the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Wait for transaction to finish or timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) time_left = wait_for_completion_timeout(&dev->done, time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(0, dev->base + IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(dev->device, "controller timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rc = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Clear command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Read a single RX FIFO worth of data from the i2c bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint8_t *buf, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int last_byte_nak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Mark as incomplete before starting the RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reinit_completion(&dev->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Unmask the read complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Start the RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) (len << RXFCR_READ_COUNT_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev->base + RXFCR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Wait for FIFO read to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) time_left = wait_for_completion_timeout(&dev->done, time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(0, dev->base + IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(dev->device, "RX FIFO time out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Read data from FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) for (; len > 0; len--, buf++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Read any amount of data using the RX FIFO from the i2c bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned int last_byte_nak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int bytes_read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) uint8_t *tmp_buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) while (bytes_read < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) last_byte_nak = 1; /* NAK last byte of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bytes_to_read = msg->len - bytes_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) last_byte_nak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bytes_read += bytes_to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tmp_buf += bytes_to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Write a single byte of data to the i2c bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int nak_expected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int nak_received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Make sure the hardware is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) rc = bcm_kona_i2c_wait_if_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Clear pending session done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Unmask the session done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Mark as incomplete before sending the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) reinit_completion(&dev->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Send one byte of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel(data, dev->base + DAT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Wait for byte to be written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) time_left = wait_for_completion_timeout(&dev->done, time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(0, dev->base + IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_dbg(dev->device, "controller timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (nak_received ^ nak_expected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(dev->device, "unexpected NAK/ACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Write a single TX FIFO worth of data to the i2c bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) uint8_t *buf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Mark as incomplete before sending data to the TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) reinit_completion(&dev->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Unmask the fifo empty and nak interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev->base + IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Disable IRQ to load a FIFO worth of data without interruption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) disable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Write data into FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) for (k = 0; k < len; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) writel(buf[k], (dev->base + DAT_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Enable IRQ now that data has been loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) enable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Wait for FIFO to empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) time_left = wait_for_completion_timeout(&dev->done, time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) writel(0, dev->base + IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Check if there was a NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(dev->device, "unexpected NAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Check if a timeout occured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(dev->device, "completion timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Write any amount of data using TX FIFO to the i2c bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned int bytes_written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) uint8_t *tmp_buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) while (bytes_written < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) bytes_to_write = msg->len - bytes_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bytes_to_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) bytes_written += bytes_to_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) tmp_buf += bytes_to_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Send i2c address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* First byte is 11110XX0 where XX is upper 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) addr = 0xF0 | ((msg->addr & 0x300) >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Second byte is the remaining 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) addr = msg->addr & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* For read, send restart command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Then re-send the first byte with the read bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev->base + CLKEN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev->base + HSTIM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) (dev->std_cfg->time_p << TIM_P_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) (dev->std_cfg->time_div << TIM_DIV_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev->base + TIM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) CLKEN_CLKEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev->base + CLKEN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) (dev->hs_cfg->time_p << TIM_P_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) (dev->hs_cfg->no_div << TIM_NO_DIV_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) (dev->hs_cfg->time_div << TIM_DIV_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev->base + TIM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) (dev->hs_cfg->hs_high_phase << HSTIM_HS_HIGH_PHASE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) (dev->hs_cfg->hs_setup << HSTIM_HS_SETUP_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev->base + HSTIM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev->base + HSTIM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Send mastercode at standard speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) rc = bcm_kona_i2c_write_byte(dev, MASTERCODE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pr_err("High speed handshake failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Configure external clock to higher frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) rc = clk_set_rate(dev->external_clk, HS_EXT_CLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_err(dev->device, "%s: clk_set_rate returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Reconfigure internal dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) bcm_kona_i2c_config_timing_hs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Send a restart command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(dev->device, "High speed restart command failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Reconfigure internal dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) bcm_kona_i2c_config_timing(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Configure external clock to lower frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev_err(dev->device, "%s: clk_set_rate returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Master transfer function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int bcm_kona_i2c_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct bcm_kona_i2c_dev *dev = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct i2c_msg *pmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) rc = clk_prepare_enable(dev->external_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err(dev->device, "%s: peri clock enable failed. err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Enable pad output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) writel(0, dev->base + PADCTL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Enable internal clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) bcm_kona_i2c_enable_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Send start command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_err(dev->device, "Start command failed rc = %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) goto xfer_disable_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Switch to high speed if applicable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (dev->hs_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) rc = bcm_kona_i2c_switch_to_hs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto xfer_send_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Loop through all messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pmsg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Send restart for subsequent messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dev_err(dev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "restart cmd failed rc = %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) goto xfer_send_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Send slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!(pmsg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) rc = bcm_kona_i2c_do_addr(dev, pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_err(dev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "NAK from addr %2.2x msg#%d rc = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pmsg->addr, i, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) goto xfer_send_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Perform data transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (pmsg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) rc = bcm_kona_i2c_read_fifo(dev, pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_err(dev->device, "read failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto xfer_send_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rc = bcm_kona_i2c_write_fifo(dev, pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_err(dev->device, "write failure");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto xfer_send_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) rc = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) xfer_send_stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Send a STOP command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* Return from high speed if applicable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (dev->hs_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int hs_rc = bcm_kona_i2c_switch_to_std(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (hs_rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) rc = hs_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) xfer_disable_pad:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Disable pad output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Stop internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) bcm_kona_i2c_disable_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) clk_disable_unprepare(dev->external_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) I2C_FUNC_NOSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const struct i2c_algorithm bcm_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .master_xfer = bcm_kona_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .functionality = bcm_kona_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned int bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int ret = of_property_read_u32(dev->device->of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) &bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev_err(dev->device, "missing clock-frequency property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) switch (bus_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case I2C_MAX_STANDARD_MODE_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case I2C_MAX_FAST_MODE_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case I2C_MAX_FAST_MODE_PLUS_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case I2C_MAX_HIGH_SPEED_MODE_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Send mastercode at 100k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev->hs_cfg = &hs_cfg_table[BCM_SPD_3P4MHZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) pr_err("%d hz bus speed not supported\n", bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pr_err("Valid speeds are 100khz, 400khz, 1mhz, and 3.4mhz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int bcm_kona_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct bcm_kona_i2c_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Allocate memory for private data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dev->device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) init_completion(&dev->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Map hardware registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (IS_ERR(dev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Get and enable external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dev->external_clk = devm_clk_get(dev->device, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (IS_ERR(dev->external_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dev_err(dev->device, "couldn't get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev_err(dev->device, "%s: clk_set_rate returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) rc = clk_prepare_enable(dev->external_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_err(dev->device, "couldn't enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Parse bus speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) rc = bcm_kona_i2c_assign_bus_speed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) goto probe_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Enable internal clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) bcm_kona_i2c_enable_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* Configure internal dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) bcm_kona_i2c_config_timing(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Disable timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) writel(0, dev->base + TOUT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Enable autosense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) bcm_kona_i2c_enable_autosense(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Enable TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev->base + TXFCR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) writel(0, dev->base + IER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) writel(ISR_CMDBUSY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ISR_READ_COMPLETE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ISR_SES_DONE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ISR_ERR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ISR_TXFIFOEMPTY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ISR_NOACK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev->base + ISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Get the interrupt number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (dev->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) rc = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) goto probe_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* register the ISR handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) rc = devm_request_irq(&pdev->dev, dev->irq, bcm_kona_i2c_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) IRQF_SHARED, pdev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_err(dev->device, "failed to request irq %i\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) goto probe_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Enable the controller but leave it idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Disable pad output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Disable internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) bcm_kona_i2c_disable_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Disable external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) clk_disable_unprepare(dev->external_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Add the i2c adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) i2c_set_adapdata(adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) adap->algo = &bcm_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) rc = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_info(dev->device, "device registered successfully\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) probe_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) bcm_kona_i2c_disable_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) clk_disable_unprepare(dev->external_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int bcm_kona_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct bcm_kona_i2c_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) i2c_del_adapter(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const struct of_device_id bcm_kona_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {.compatible = "brcm,kona-i2c",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) MODULE_DEVICE_TABLE(of, bcm_kona_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static struct platform_driver bcm_kona_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .name = "bcm-kona-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .of_match_table = bcm_kona_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .probe = bcm_kona_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .remove = bcm_kona_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) module_platform_driver(bcm_kona_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) MODULE_DESCRIPTION("Broadcom Kona I2C Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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