^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IDM_CTRL_DIRECT_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CFG_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CFG_RESET_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CFG_EN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CFG_SLAVE_ADDR_0_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CFG_M_RETRY_CNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CFG_M_RETRY_CNT_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TIM_CFG_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TIM_CFG_MODE_400_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TIM_RAND_SLAVE_STRETCH_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S_CFG_SMBUS_ADDR_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S_CFG_NIC_SMB_ADDR3_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S_CFG_NIC_SMB_ADDR2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S_CFG_NIC_SMB_ADDR1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S_CFG_NIC_SMB_ADDR0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define M_FIFO_CTRL_OFFSET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define M_FIFO_RX_FLUSH_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define M_FIFO_TX_FLUSH_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define M_FIFO_RX_CNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define M_FIFO_RX_CNT_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define M_FIFO_RX_THLD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define M_FIFO_RX_THLD_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S_FIFO_CTRL_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S_FIFO_RX_FLUSH_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S_FIFO_TX_FLUSH_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S_FIFO_RX_CNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S_FIFO_RX_CNT_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S_FIFO_RX_THLD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S_FIFO_RX_THLD_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define M_CMD_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define M_CMD_START_BUSY_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define M_CMD_STATUS_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define M_CMD_STATUS_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define M_CMD_STATUS_SUCCESS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define M_CMD_STATUS_LOST_ARB 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define M_CMD_STATUS_NACK_ADDR 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define M_CMD_STATUS_NACK_DATA 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define M_CMD_STATUS_TIMEOUT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define M_CMD_STATUS_FIFO_UNDERRUN 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define M_CMD_STATUS_RX_FIFO_FULL 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define M_CMD_PROTOCOL_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define M_CMD_PROTOCOL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define M_CMD_PROTOCOL_QUICK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define M_CMD_PROTOCOL_BLK_WR 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define M_CMD_PROTOCOL_BLK_RD 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define M_CMD_PROTOCOL_PROCESS 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define M_CMD_PEC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define M_CMD_RD_CNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define M_CMD_RD_CNT_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define S_CMD_OFFSET 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S_CMD_START_BUSY_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define S_CMD_STATUS_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S_CMD_STATUS_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S_CMD_STATUS_SUCCESS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define S_CMD_STATUS_TIMEOUT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IE_OFFSET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IE_M_RX_FIFO_FULL_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IE_M_RX_THLD_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IE_M_START_BUSY_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IE_M_TX_UNDERRUN_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IE_S_RX_FIFO_FULL_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IE_S_RX_THLD_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IE_S_RX_EVENT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IE_S_START_BUSY_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IE_S_TX_UNDERRUN_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IE_S_RD_EVENT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IS_OFFSET 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IS_M_RX_FIFO_FULL_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IS_M_RX_THLD_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IS_M_START_BUSY_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IS_M_TX_UNDERRUN_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IS_S_RX_FIFO_FULL_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IS_S_RX_THLD_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IS_S_RX_EVENT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IS_S_START_BUSY_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IS_S_TX_UNDERRUN_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IS_S_RD_EVENT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define M_TX_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define M_TX_WR_STATUS_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define M_TX_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define M_TX_DATA_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define M_RX_OFFSET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define M_RX_STATUS_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define M_RX_STATUS_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define M_RX_PEC_ERR_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define M_RX_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define M_RX_DATA_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S_TX_OFFSET 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define S_TX_WR_STATUS_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define S_TX_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S_TX_DATA_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define S_RX_OFFSET 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define S_RX_STATUS_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define S_RX_STATUS_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define S_RX_PEC_ERR_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define S_RX_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define S_RX_DATA_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define I2C_TIMEOUT_MSEC 50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define M_TX_RX_FIFO_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define M_RX_MAX_READ_LEN 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define M_RX_FIFO_THLD_VALUE 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IE_M_ALL_INTERRUPT_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IE_M_ALL_INTERRUPT_MASK 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SLAVE_READ_WRITE_BIT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SLAVE_READ_WRITE_BIT_SHIFT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SLAVE_MAX_SIZE_TRANSACTION 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SLAVE_CLOCK_STRETCH_TIME 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IE_S_ALL_INTERRUPT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IE_S_ALL_INTERRUPT_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * It takes ~18us to reading 10bytes of data, hence to keep tasklet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * running for less time, max slave read per tasklet is set to 10 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MAX_SLAVE_RX_PER_INT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum i2c_slave_read_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) I2C_SLAVE_RX_FIFO_EMPTY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) I2C_SLAVE_RX_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) I2C_SLAVE_RX_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) I2C_SLAVE_RX_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) enum bus_speed_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) I2C_SPD_100K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) I2C_SPD_400K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) enum bcm_iproc_i2c_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IPROC_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IPROC_I2C_NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct bcm_iproc_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) enum bcm_iproc_i2c_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void __iomem *idm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 ape_addr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* lock for indirect access through IDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) spinlock_t idm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int xfer_is_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct i2c_client *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* bytes that have been transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* bytes that have been read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int thld_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bool slave_rx_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bool rx_start_rcvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bool slave_read_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 tx_underrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 slave_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct tasklet_struct slave_rx_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* tasklet to process slave rx data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void slave_rx_tasklet_fn(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Can be expanded in the future if more interrupt status bits are utilized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) | BIT(IS_M_RX_THLD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) | BIT(IS_S_RX_THLD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (iproc_i2c->idm_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) spin_lock(&iproc_i2c->idm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel(iproc_i2c->ape_addr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val = readl(iproc_i2c->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spin_unlock(&iproc_i2c->idm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val = readl(iproc_i2c->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (iproc_i2c->idm_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) spin_lock(&iproc_i2c->idm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(iproc_i2c->ape_addr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel(val, iproc_i2c->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spin_unlock(&iproc_i2c->idm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writel(val, iproc_i2c->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void bcm_iproc_i2c_slave_init(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) iproc_i2c->tx_underrun = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (need_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* put controller in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val |= BIT(CFG_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* wait 100 usec per spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* bring controller out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) val &= ~(BIT(CFG_RESET_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* flush TX/RX FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Maximum slave stretch time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Configure the slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* clear all pending slave interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Enable interrupt register to indicate a valid byte in receive fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val = BIT(IE_S_RX_EVENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Enable interrupt register to indicate a Master read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) val |= BIT(IE_S_RD_EVENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Enable interrupt register for the Slave BUSY command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) val |= BIT(IE_S_START_BUSY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) iproc_i2c->slave_int_mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void bcm_iproc_i2c_check_slave_status(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct bcm_iproc_i2c_dev *iproc_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* status is valid only when START_BUSY is cleared after it was set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (val & BIT(S_CMD_START_BUSY_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (val == S_CMD_STATUS_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* re-initialize i2c for recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) bcm_iproc_i2c_enable_disable(iproc_i2c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bcm_iproc_i2c_slave_init(iproc_i2c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bcm_iproc_i2c_enable_disable(iproc_i2c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 rx_data, rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 rx_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (rx_status == I2C_SLAVE_RX_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Start of SMBUS Master write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) i2c_slave_event(iproc_i2c->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) I2C_SLAVE_WRITE_REQUESTED, &rx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) iproc_i2c->rx_start_rcvd = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) iproc_i2c->slave_read_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else if (rx_status == I2C_SLAVE_RX_DATA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) iproc_i2c->rx_start_rcvd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Middle of SMBUS Master write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) i2c_slave_event(iproc_i2c->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) I2C_SLAVE_WRITE_RECEIVED, &rx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else if (rx_status == I2C_SLAVE_RX_END &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) iproc_i2c->rx_start_rcvd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* End of SMBUS Master write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (iproc_i2c->slave_rx_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) i2c_slave_event(iproc_i2c->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) I2C_SLAVE_WRITE_RECEIVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) &rx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) &rx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) iproc_i2c->rx_start_rcvd = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) iproc_i2c->slave_read_complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) rx_bytes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void slave_rx_tasklet_fn(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 int_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) bcm_iproc_i2c_slave_read(iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* clear pending IS_S_RX_EVENT_SHIFT interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int_clr = BIT(IS_S_RX_EVENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * In case of single byte master-read request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * IS_S_TX_UNDERRUN_SHIFT event is generated before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * IS_S_START_BUSY_SHIFT event. Hence start slave data send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * from first IS_S_TX_UNDERRUN_SHIFT event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * This means don't send any data from slave when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * IS_S_RD_EVENT_SHIFT event is generated else it will increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * eeprom or other backend slave driver read pointer twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) iproc_i2c->tx_underrun = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* clear IS_S_RD_EVENT_SHIFT interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* clear slave interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* enable slave interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Slave events in case of master-write, master-write-read and,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * master-read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Master-write : only IS_S_RX_EVENT_SHIFT event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * events or only IS_S_RD_EVENT_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) status & BIT(IS_S_RD_EVENT_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* disable slave interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) val &= ~iproc_i2c->slave_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (status & BIT(IS_S_RD_EVENT_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Master-write-read request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) iproc_i2c->slave_rx_only = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Master-write request only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) iproc_i2c->slave_rx_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* schedule tasklet to read data later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* clear only IS_S_RX_EVENT_SHIFT interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) BIT(IS_S_RX_EVENT_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) iproc_i2c->tx_underrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (iproc_i2c->tx_underrun == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Start of SMBUS for Master Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) i2c_slave_event(iproc_i2c->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) I2C_SLAVE_READ_REQUESTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Master read other than start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) i2c_slave_event(iproc_i2c->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) I2C_SLAVE_READ_PROCESSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* start transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val = BIT(S_CMD_START_BUSY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) BIT(IS_S_TX_UNDERRUN_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Stop received from master in case of master read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (status & BIT(IS_S_START_BUSY_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * Enable interrupt for TX FIFO becomes empty and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * less than PKT_LENGTH bytes were output on the SMBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) iproc_i2c->slave_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* End of SMBUS for Master Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val = BIT(S_TX_WR_STATUS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val = BIT(S_CMD_START_BUSY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* flush TX FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) BIT(IS_S_START_BUSY_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* check slave transmit status only if slave is transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!iproc_i2c->slave_rx_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) bcm_iproc_i2c_check_slave_status(iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct i2c_msg *msg = iproc_i2c->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Read valid data from RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) while (iproc_i2c->rx_bytes < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* rx fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) msg->buf[iproc_i2c->rx_bytes] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) iproc_i2c->rx_bytes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct i2c_msg *msg = iproc_i2c->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* can only fill up to the FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) for (i = 0; i < tx_bytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* start from where we left over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int idx = iproc_i2c->tx_bytes + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) val = msg->buf[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* mark the last byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (idx == msg->len - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) val |= BIT(M_TX_WR_STATUS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (iproc_i2c->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * Since this is the last byte, we should now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * disable TX FIFO underrun interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* load data into TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* update number of transferred bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) iproc_i2c->tx_bytes += tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct i2c_msg *msg = iproc_i2c->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 bytes_left, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) bytes_left = msg->len - iproc_i2c->rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (bytes_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (iproc_i2c->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* finished reading all data, disable rx thld event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) val &= ~BIT(IS_M_RX_THLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } else if (bytes_left < iproc_i2c->thld_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* set bytes left as threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) iproc_i2c->thld_bytes = bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * bytes_left >= iproc_i2c->thld_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * hence no need to change the THRESHOLD SET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * It will remain as iproc_i2c->thld_bytes itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* TX FIFO is empty and we have more data to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) bcm_iproc_i2c_send(iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* RX FIFO threshold is reached and data needs to be read out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (status & BIT(IS_M_RX_THLD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bcm_iproc_i2c_read(iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* transfer is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (status & BIT(IS_M_START_BUSY_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) iproc_i2c->xfer_is_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (iproc_i2c->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) complete(&iproc_i2c->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct bcm_iproc_i2c_dev *iproc_i2c = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 slave_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* process only slave interrupt which are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ISR_MASK_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (slave_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) status &= ISR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* process all master based events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) bcm_iproc_i2c_process_m_event(iproc_i2c, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* put controller in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) val |= BIT(CFG_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val &= ~(BIT(CFG_EN_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* wait 100 usec per spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* bring controller out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val &= ~(BIT(CFG_RESET_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) val &= ~(IE_M_ALL_INTERRUPT_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) IE_M_ALL_INTERRUPT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) val |= BIT(CFG_EN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) val &= ~BIT(CFG_EN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case M_CMD_STATUS_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case M_CMD_STATUS_LOST_ARB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case M_CMD_STATUS_NACK_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case M_CMD_STATUS_NACK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_dbg(iproc_i2c->device, "NAK data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case M_CMD_STATUS_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_dbg(iproc_i2c->device, "bus timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case M_CMD_STATUS_FIFO_UNDERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_dbg(iproc_i2c->device, "FIFO under-run\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case M_CMD_STATUS_RX_FIFO_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev_dbg(iproc_i2c->device, "RX FIFO full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* re-initialize i2c for recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) bcm_iproc_i2c_enable_disable(iproc_i2c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) bcm_iproc_i2c_init(iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) bcm_iproc_i2c_enable_disable(iproc_i2c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u32 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u32 val, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (iproc_i2c->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) time_left = wait_for_completion_timeout(&iproc_i2c->done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* read it back to flush the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* make sure the interrupt handler isn't running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) synchronize_irq(iproc_i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) } else { /* polling mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned long timeout = jiffies + time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) status = iproc_i2c_rd_reg(iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) IS_OFFSET) & ISR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) bcm_iproc_i2c_process_m_event(iproc_i2c, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) time_left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) } while (!iproc_i2c->xfer_is_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!time_left && !iproc_i2c->xfer_is_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_err(iproc_i2c->device, "transaction timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* flush both TX/RX FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* flush both TX/RX FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * If 'process_call' is true, then this is a multi-msg transfer that requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * a repeated start between the messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * More specifically, it must be a write (reg) followed by a read (data).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * The i2c quirks are set to enforce this rule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct i2c_msg *msgs, bool process_call)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 val, tmp, val_intr_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) unsigned int tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct i2c_msg *msg = &msgs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* check if bus is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!!(iproc_i2c_rd_reg(iproc_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_warn(iproc_i2c->device, "bus is busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) iproc_i2c->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* format and load slave address into the TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * For a write transaction, load data into the TX FIFO. Only allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * loading up to TX FIFO size - 1 bytes of data since the first byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * has been used up by the slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!(msg->flags & I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) for (i = 0; i < tx_bytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) val = msg->buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* mark the last byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!process_call && (i == msg->len - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) val |= BIT(M_TX_WR_STATUS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) iproc_i2c->tx_bytes = tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Process the read message if this is process call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (process_call) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) iproc_i2c->msg = msg; /* point to second msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * The last byte to be sent out should be a slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * address with read operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* mark it the last byte out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) val = addr | BIT(M_TX_WR_STATUS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* mark as incomplete before starting the transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (iproc_i2c->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) reinit_completion(&iproc_i2c->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) iproc_i2c->xfer_is_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * Enable the "start busy" interrupt, which will be triggered after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * transaction is done, i.e., the internal start_busy bit, transitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * from 1 to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * If TX data size is larger than the TX FIFO, need to enable TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * underrun interrupt, which will be triggerred when the TX FIFO is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * empty. When that happens we can then pump more data into the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (!process_call && !(msg->flags & I2C_M_RD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) msg->len > iproc_i2c->tx_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * Now we can activate the transfer. For a read operation, specify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * number of bytes to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) val = BIT(M_CMD_START_BUSY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (msg->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* SMBUS QUICK Command (Read/Write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) } else if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u32 protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) iproc_i2c->rx_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) iproc_i2c->thld_bytes = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* set threshold value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* enable the RX threshold interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) protocol = process_call ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) (msg->len << M_CMD_RD_CNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (iproc_i2c->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) bool process_call = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (num == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* Repeated start, use process call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) process_call = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (msgs[1].flags & I2C_M_NOSTART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_err(iproc_i2c->device, "Invalid repeated start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_dbg(iproc_i2c->device, "xfer failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (adap->algo->reg_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) val |= I2C_FUNC_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static struct i2c_algorithm bcm_iproc_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .master_xfer = bcm_iproc_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .functionality = bcm_iproc_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .reg_slave = bcm_iproc_i2c_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .unreg_slave = bcm_iproc_i2c_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .flags = I2C_AQ_COMB_WRITE_THEN_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .max_read_len = M_RX_MAX_READ_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) unsigned int bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int ret = of_property_read_u32(iproc_i2c->device->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) "clock-frequency", &bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dev_info(iproc_i2c->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) "unable to interpret clock-frequency DT property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_err(iproc_i2c->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "valid speeds are 100khz and 400khz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) bus_speed = I2C_MAX_FAST_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) iproc_i2c->bus_speed = bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static int bcm_iproc_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) int irq, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct bcm_iproc_i2c_dev *iproc_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (!iproc_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) platform_set_drvdata(pdev, iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) iproc_i2c->device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) iproc_i2c->type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) init_completion(&iproc_i2c->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (IS_ERR(iproc_i2c->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return PTR_ERR(iproc_i2c->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (iproc_i2c->type == IPROC_I2C_NIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (IS_ERR(iproc_i2c->idm_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return PTR_ERR(iproc_i2c->idm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret = of_property_read_u32(iproc_i2c->device->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "brcm,ape-hsls-addr-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) &iproc_i2c->ape_addr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dev_err(iproc_i2c->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) "'brcm,ape-hsls-addr-mask' missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) spin_lock_init(&iproc_i2c->idm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* no slave support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) bcm_iproc_algo.reg_slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) bcm_iproc_algo.unreg_slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ret = bcm_iproc_i2c_init(iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = devm_request_irq(iproc_i2c->device, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) bcm_iproc_i2c_isr, 0, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dev_err(iproc_i2c->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "unable to request irq %i\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) iproc_i2c->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_warn(iproc_i2c->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "no irq resource, falling back to poll mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) bcm_iproc_i2c_enable_disable(iproc_i2c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) adap = &iproc_i2c->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) i2c_set_adapdata(adap, iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) snprintf(adap->name, sizeof(adap->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) "Broadcom iProc (%s)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) of_node_full_name(iproc_i2c->device->of_node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) adap->algo = &bcm_iproc_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) adap->quirks = &bcm_iproc_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int bcm_iproc_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (iproc_i2c->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * Make sure there's no pending interrupt when we remove the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) synchronize_irq(iproc_i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) i2c_del_adapter(&iproc_i2c->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) bcm_iproc_i2c_enable_disable(iproc_i2c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static int bcm_iproc_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (iproc_i2c->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * Make sure there's no pending interrupt when we go into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) synchronize_irq(iproc_i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* now disable the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) bcm_iproc_i2c_enable_disable(iproc_i2c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static int bcm_iproc_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * Power domain could have been shut off completely in system deep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * sleep, so re-initialize the block here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = bcm_iproc_i2c_init(iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* configure to the desired bus speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) bcm_iproc_i2c_enable_disable(iproc_i2c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .suspend_late = &bcm_iproc_i2c_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .resume_early = &bcm_iproc_i2c_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define BCM_IPROC_I2C_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (iproc_i2c->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (slave->flags & I2C_CLIENT_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return -EAFNOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) iproc_i2c->slave = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) (unsigned long)iproc_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) bcm_iproc_i2c_slave_init(iproc_i2c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (!iproc_i2c->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) disable_irq(iproc_i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* disable all slave interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) IE_S_ALL_INTERRUPT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) tasklet_kill(&iproc_i2c->slave_rx_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* Erase the slave address programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* flush TX/RX FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* clear all pending slave interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) iproc_i2c->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) enable_irq(iproc_i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static const struct of_device_id bcm_iproc_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .compatible = "brcm,iproc-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .data = (int *)IPROC_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .compatible = "brcm,iproc-nic-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .data = (int *)IPROC_I2C_NIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static struct platform_driver bcm_iproc_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .name = "bcm-iproc-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .of_match_table = bcm_iproc_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .pm = BCM_IPROC_I2C_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .probe = bcm_iproc_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .remove = bcm_iproc_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) module_platform_driver(bcm_iproc_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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