^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This driver implements I2C master functionality using the LSI API2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * NOTE: The controller has a limitation in that it can only do transfers of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * maximum 255 bytes at a time. If a larger transfer is attempted, error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (-EINVAL) is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SCL_WAIT_TIMEOUT_NS 25000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FIFO_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SEQ_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GLOBAL_CONTROL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GLOBAL_MST_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GLOBAL_SLV_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GLOBAL_IBML_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define INTERRUPT_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define INTERRUPT_ENABLE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define INT_SLV BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define INT_MST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WAIT_TIMER_CONTROL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define WT_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WT_VALUE(_x) ((_x) & 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IBML_TIMEOUT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IBML_LOW_MEXT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IBML_LOW_SEXT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TIMER_CLOCK_DIV 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_BUS_MONITOR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BM_SDAC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BM_SCLC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BM_SDAS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BM_SCLS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SOFT_RESET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MST_COMMAND 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CMD_BUSY (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CMD_MANUAL (0x00 | CMD_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CMD_AUTO (0x01 | CMD_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CMD_SEQUENCE (0x02 | CMD_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MST_RX_XFER 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MST_TX_XFER 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MST_ADDR_1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MST_ADDR_2 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MST_DATA 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MST_TX_FIFO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MST_RX_FIFO 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MST_INT_ENABLE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MST_INT_STATUS 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MST_STATUS_SNS (1 << 11) /* Manual mode done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MST_STATUS_SS (1 << 10) /* Automatic mode done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MST_STATUS_SCC (1 << 9) /* Stop complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MST_STATUS_IP (1 << 8) /* Invalid parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MST_STATUS_TSS (1 << 7) /* Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MST_STATUS_AL (1 << 6) /* Arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MST_STATUS_ND (1 << 5) /* NAK on data phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MST_STATUS_NA (1 << 4) /* NAK on address phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MST_STATUS_NAK (MST_STATUS_NA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MST_STATUS_ND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MST_STATUS_ERR (MST_STATUS_NAK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MST_STATUS_AL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MST_STATUS_IP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MST_TX_BYTES_XFRD 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MST_RX_BYTES_XFRD 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SLV_ADDR_DEC_CTL 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SLV_ADDR_DEC_GCE BIT(0) /* ACK to General Call Address from own master (loopback) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SLV_ADDR_DEC_OGCE BIT(1) /* ACK to General Call Address from external masters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SLV_ADDR_DEC_SA1E BIT(2) /* ACK to addr_1 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SLV_ADDR_DEC_SA1M BIT(3) /* 10-bit addressing for addr_1 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SLV_ADDR_DEC_SA2E BIT(4) /* ACK to addr_2 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SLV_ADDR_DEC_SA2M BIT(5) /* 10-bit addressing for addr_2 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SLV_ADDR_1 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SLV_ADDR_2 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SLV_RX_CTL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SLV_RX_ACSA1 BIT(0) /* Generate ACK for writes to addr_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SLV_RX_ACSA2 BIT(1) /* Generate ACK for writes to addr_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SLV_RX_ACGCA BIT(2) /* ACK data phase transfers to General Call Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SLV_DATA 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SLV_RX_FIFO 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SLV_FIFO_DV1 BIT(0) /* Data Valid for addr_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SLV_FIFO_DV2 BIT(1) /* Data Valid for addr_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SLV_FIFO_AS BIT(2) /* (N)ACK Sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SLV_FIFO_TNAK BIT(3) /* Timeout NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SLV_FIFO_STRC BIT(4) /* First byte after start condition received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SLV_FIFO_RSC BIT(5) /* Repeated Start Condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SLV_FIFO_STPC BIT(6) /* Stop Condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SLV_FIFO_DV (SLV_FIFO_DV1 | SLV_FIFO_DV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SLV_INT_ENABLE 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SLV_INT_STATUS 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SLV_STATUS_RFH BIT(0) /* FIFO service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SLV_STATUS_WTC BIT(1) /* Write transfer complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SLV_STATUS_SRS1 BIT(2) /* Slave read from addr 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SLV_STATUS_SRRS1 BIT(3) /* Repeated start from addr 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SLV_STATUS_SRND1 BIT(4) /* Read request not following start condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SLV_STATUS_SRC1 BIT(5) /* Read canceled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SLV_STATUS_SRAT1 BIT(6) /* Slave Read timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SLV_STATUS_SRDRE1 BIT(7) /* Data written after timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SLV_READ_DUMMY 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCL_HIGH_PERIOD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SCL_LOW_PERIOD 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SPIKE_FLTR_LEN 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SDA_SETUP_TIME 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDA_HOLD_TIME 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * axxia_i2c_dev - I2C device context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @base: pointer to register struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @msg: pointer to current message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @msg_r: pointer to current read message (sequence transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @msg_xfrd: number of bytes transferred in tx_fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @msg_xfrd_r: number of bytes transferred in rx_fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @msg_err: error code for completed message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @msg_complete: xfer completion object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @dev: device reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @adapter: core i2c abstraction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @i2c_clk: clock reference for i2c input clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @bus_clk_rate: current i2c bus clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @last: a flag indicating is this is last message in transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct axxia_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct i2c_msg *msg_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) size_t msg_xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) size_t msg_xfrd_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int msg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct completion msg_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct clk *i2c_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 bus_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct i2c_client *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int_en = readl(idev->base + MST_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int_en = readl(idev->base + MST_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel(int_en | mask, idev->base + MST_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static u32 ns_to_clk(u64 ns, u32 clk_mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return div_u64(ns * clk_mhz, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int axxia_i2c_init(struct axxia_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 t_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 t_high, t_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 tmo_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) idev->bus_clk_rate, clk_mhz, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Reset controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(0x01, idev->base + SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) timeout = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) while (readl(idev->base + SOFT_RESET) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_warn(idev->dev, "Soft reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Enable Master Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel(0x1, idev->base + GLOBAL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Standard mode SCL 50/50, tSU:DAT = 250 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) t_high = divisor * 1 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) t_low = divisor * 1 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) t_setup = ns_to_clk(250, clk_mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Fast mode SCL 33/66, tSU:DAT = 100 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) t_high = divisor * 1 / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) t_low = divisor * 2 / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) t_setup = ns_to_clk(100, clk_mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* SCL High Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel(t_high, idev->base + SCL_HIGH_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* SCL Low Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel(t_low, idev->base + SCL_LOW_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* SDA Setup Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(t_setup, idev->base + SDA_SETUP_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* SDA Hold Time, 300ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Filter <50ns spikes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Configure Time-Out Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (prescale = 0; prescale < 15; ++prescale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (tmo_clk <= 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) tmo_clk >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (tmo_clk > 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tmo_clk = 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Prescale divider (log2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) writel(prescale, idev->base + TIMER_CLOCK_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Timeout in divided clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Mask all master interrupt bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) i2c_int_disable(idev, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writel(0x01, idev->base + INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int i2c_m_rd(const struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return (msg->flags & I2C_M_RD) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int i2c_m_ten(const struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return (msg->flags & I2C_M_TEN) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int i2c_m_recv_len(const struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return (msg->flags & I2C_M_RECV_LEN) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * transfer length if this is the first byte of such a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct i2c_msg *msg = idev->msg_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) while (bytes_to_transfer-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int c = readl(idev->base + MST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Check length byte for SMBus block read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) idev->msg_err = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) i2c_int_disable(idev, ~MST_STATUS_TSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) complete(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) msg->len = 1 + c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writel(msg->len, idev->base + MST_RX_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) msg->buf[idev->msg_xfrd_r++] = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @return: Number of bytes left to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct i2c_msg *msg = idev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int ret = msg->len - idev->msg_xfrd - bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) while (bytes_to_transfer-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void axxia_i2c_slv_fifo_event(struct axxia_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 fifo_status = readl(idev->base + SLV_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_dbg(idev->dev, "slave irq fifo_status=0x%x\n", fifo_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (fifo_status & SLV_FIFO_DV1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (fifo_status & SLV_FIFO_STRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) i2c_slave_event(idev->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) I2C_SLAVE_WRITE_REQUESTED, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val = readl(idev->base + SLV_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) i2c_slave_event(idev->slave, I2C_SLAVE_WRITE_RECEIVED, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (fifo_status & SLV_FIFO_STPC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) readl(idev->base + SLV_DATA); /* dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (fifo_status & SLV_FIFO_RSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) readl(idev->base + SLV_DATA); /* dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static irqreturn_t axxia_i2c_slv_isr(struct axxia_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 status = readl(idev->base + SLV_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_dbg(idev->dev, "slave irq status=0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (status & SLV_STATUS_RFH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) axxia_i2c_slv_fifo_event(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (status & SLV_STATUS_SRS1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) i2c_slave_event(idev->slave, I2C_SLAVE_READ_REQUESTED, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) writel(val, idev->base + SLV_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (status & SLV_STATUS_SRND1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) i2c_slave_event(idev->slave, I2C_SLAVE_READ_PROCESSED, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) writel(val, idev->base + SLV_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (status & SLV_STATUS_SRC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel(INT_SLV, idev->base + INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct axxia_i2c_dev *idev = _dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) status = readl(idev->base + INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (status & INT_SLV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = axxia_i2c_slv_isr(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!(status & INT_MST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Read interrupt status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) status = readl(idev->base + MST_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!idev->msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_warn(idev->dev, "unexpected interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* RX FIFO needs service? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) axxia_i2c_empty_rx_fifo(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* TX FIFO needs service? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (axxia_i2c_fill_tx_fifo(idev) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) i2c_int_disable(idev, MST_STATUS_TFL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (unlikely(status & MST_STATUS_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Transfer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) i2c_int_disable(idev, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (status & MST_STATUS_AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) idev->msg_err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) else if (status & MST_STATUS_NAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) idev->msg_err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) idev->msg_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) idev->msg->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) readl(idev->base + MST_RX_BYTES_XFRD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) readl(idev->base + MST_RX_XFER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) readl(idev->base + MST_TX_BYTES_XFRD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) readl(idev->base + MST_TX_XFER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) complete(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) } else if (status & MST_STATUS_SCC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Stop completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) i2c_int_disable(idev, ~MST_STATUS_TSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) complete(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Transfer done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int mask = idev->last ? ~0 : ~MST_STATUS_TSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) i2c_int_disable(idev, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) axxia_i2c_empty_rx_fifo(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) complete(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) } else if (status & MST_STATUS_TSS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Transfer timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) idev->msg_err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) i2c_int_disable(idev, ~MST_STATUS_TSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) complete(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) writel(INT_MST, idev->base + INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 addr_1, addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (i2c_m_ten(msg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* 10-bit address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * addr_1: 5'b11110 | addr[9:8] | (R/nW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * addr_2: addr[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (i2c_m_rd(msg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) addr_1 |= 1; /* Set the R/nW bit of the address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) addr_2 = msg->addr & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* 7-bit address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * addr_1: addr[6:0] | (R/nW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * addr_2: dont care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) addr_1 = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) addr_2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) writel(addr_1, idev->base + MST_ADDR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) writel(addr_2, idev->base + MST_ADDR_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* The NAK interrupt will be sent _before_ issuing STOP command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * so the controller might still be busy processing it. No
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * interrupt will be sent at the end so we have to poll for it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long timeout = jiffies + I2C_XFER_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) usleep_range(1, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) axxia_i2c_set_addr(idev, &msgs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) writel(msgs[0].len, idev->base + MST_TX_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) writel(rlen, idev->base + MST_RX_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) idev->msg = &msgs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) idev->msg_r = &msgs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) idev->msg_xfrd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) idev->msg_xfrd_r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) idev->last = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) axxia_i2c_fill_tx_fifo(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reinit_completion(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) i2c_int_enable(idev, int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) time_left = wait_for_completion_timeout(&idev->msg_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) I2C_XFER_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (idev->msg_err == -ENXIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (axxia_i2c_handle_seq_nak(idev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) axxia_i2c_init(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_warn(idev->dev, "busy after xfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) idev->msg_err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) i2c_recover_bus(&idev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) axxia_i2c_init(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) axxia_i2c_init(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return idev->msg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bool last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 int_mask = MST_STATUS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 rx_xfer, tx_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned int wt_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) idev->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) idev->msg_r = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) idev->msg_xfrd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) idev->msg_xfrd_r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) idev->last = last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) reinit_completion(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) axxia_i2c_set_addr(idev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (i2c_m_rd(msg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* I2C read transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) tx_xfer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* I2C write transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rx_xfer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) tx_xfer = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writel(rx_xfer, idev->base + MST_RX_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writel(tx_xfer, idev->base + MST_TX_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (i2c_m_rd(msg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int_mask |= MST_STATUS_RFL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) else if (axxia_i2c_fill_tx_fifo(idev) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int_mask |= MST_STATUS_TFL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Disable wait timer temporarly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Check if timeout error happened */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (idev->msg_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) writel(CMD_MANUAL, idev->base + MST_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int_mask |= MST_STATUS_SNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) writel(CMD_AUTO, idev->base + MST_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int_mask |= MST_STATUS_SS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) i2c_int_enable(idev, int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) time_left = wait_for_completion_timeout(&idev->msg_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) I2C_XFER_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) i2c_int_disable(idev, int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_warn(idev->dev, "busy after xfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) idev->msg_err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) i2c_recover_bus(&idev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) axxia_i2c_init(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) idev->msg_err != -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) axxia_i2c_init(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return idev->msg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* This function checks if the msgs[] array contains messages compatible with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Sequence mode of operation. This mode assumes there will be exactly one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * write of non-zero length followed by exactly one read of non-zero length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * both targeted at the same client device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) msgs[1].len > 0 && msgs[0].addr == msgs[1].addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) idev->msg_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (axxia_i2c_sequence_ok(msgs, num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = axxia_i2c_xfer_seq(idev, msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret ? : SEQ_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) i2c_int_enable(idev, MST_STATUS_TSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) for (i = 0; ret == 0 && i < num; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret ? : i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int axxia_i2c_get_scl(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Preserve SDA Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) tmp |= BM_SCLC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) writel(tmp, idev->base + I2C_BUS_MONITOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int axxia_i2c_get_sda(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static struct i2c_bus_recovery_info axxia_i2c_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .recover_bus = i2c_generic_scl_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .get_scl = axxia_i2c_get_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .set_scl = axxia_i2c_set_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .get_sda = axxia_i2c_get_sda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static u32 axxia_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int axxia_i2c_reg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 slv_int_mask = SLV_STATUS_RFH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 dec_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (idev->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) idev->slave = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Enable slave mode as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Set slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dec_ctl = SLV_ADDR_DEC_SA1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (slave->flags & I2C_CLIENT_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dec_ctl |= SLV_ADDR_DEC_SA1M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) writel(slave->addr, idev->base + SLV_ADDR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) slv_int_mask |= SLV_STATUS_SRS1 | SLV_STATUS_SRRS1 | SLV_STATUS_SRND1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) slv_int_mask |= SLV_STATUS_SRC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) writel(slv_int_mask, idev->base + SLV_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int axxia_i2c_unreg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Disable slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) writel(INT_MST, idev->base + INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) synchronize_irq(idev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) idev->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const struct i2c_algorithm axxia_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .master_xfer = axxia_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .functionality = axxia_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .reg_slave = axxia_i2c_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .unreg_slave = axxia_i2c_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const struct i2c_adapter_quirks axxia_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .max_read_len = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .max_write_len = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int axxia_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct axxia_i2c_dev *idev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) idev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (idev->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return idev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (IS_ERR(idev->i2c_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_err(&pdev->dev, "missing clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return PTR_ERR(idev->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) idev->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) idev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) init_completion(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (idev->bus_clk_rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = clk_prepare_enable(idev->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_err(&pdev->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret = axxia_i2c_init(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_err(&pdev->dev, "failed to initialize\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) goto error_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = devm_request_irq(&pdev->dev, idev->irq, axxia_i2c_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pdev->name, idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_err(&pdev->dev, "failed to claim IRQ%d\n", idev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) goto error_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) i2c_set_adapdata(&idev->adapter, idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) idev->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) idev->adapter.algo = &axxia_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) idev->adapter.quirks = &axxia_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) idev->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) idev->adapter.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) platform_set_drvdata(pdev, idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = i2c_add_adapter(&idev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) goto error_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) error_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) clk_disable_unprepare(idev->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int axxia_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct axxia_i2c_dev *idev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) clk_disable_unprepare(idev->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) i2c_del_adapter(&idev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Match table for of_platform binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const struct of_device_id axxia_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { .compatible = "lsi,api2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MODULE_DEVICE_TABLE(of, axxia_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static struct platform_driver axxia_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .probe = axxia_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .remove = axxia_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .name = "axxia-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .of_match_table = axxia_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) module_platform_driver(axxia_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) MODULE_DESCRIPTION("Axxia I2C Bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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