^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The documentation describes this as an SMBus controller, but it doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * understand any of the SMBus protocol in hardware. It's really an I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * controller that could emulate most of the SMBus in software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This is just a skeleton adapter to use with the Au1550 PSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * algorithm. It was developed for the Pb1550, but will work with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * any Au1550 board that has a similar PSC configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach-au1x00/au1xxx_psc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PSC_SEL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PSC_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PSC_SMBCFG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PSC_SMBMSK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PSC_SMBPCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PSC_SMBSTAT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PSC_SMBEVNT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PSC_SMBTXRX 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PSC_SMBTMR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct i2c_au1550_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __iomem *psc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int xfer_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __raw_writel(v, a->psc_base + r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline unsigned long RD(struct i2c_au1550_data *a, int r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return __raw_readl(a->psc_base + r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int wait_xfer_done(struct i2c_au1550_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Wait for Tx Buffer Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (i = 0; i < adap->xfer_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int wait_ack(struct i2c_au1550_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (wait_xfer_done(adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) stat = RD(adap, PSC_SMBEVNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int wait_master_done(struct i2c_au1550_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Wait for Master Done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) for (i = 0; i < 2 * adap->xfer_timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned long stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Reset the FIFOs, clear events. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) stat = RD(adap, PSC_SMBSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Write out the i2c chip address and specify operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) addr <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) addr |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* zero-byte xfers stop immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) addr |= PSC_SMBTXRX_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Put byte into fifo, start up master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) WR(adap, PSC_SMBTXRX, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (wait_ack(adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return (q) ? wait_master_done(adap) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (wait_xfer_done(adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) j = adap->xfer_timeout * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) j--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (j <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } while (j > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *out = RD(adap, PSC_SMBTXRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* A read is performed by stuffing the transmit fifo with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * zero bytes for timing, waiting for bytes to appear in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * receive fifo, then reading the bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) while (i < (len - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) WR(adap, PSC_SMBTXRX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (wait_for_rx_byte(adap, &buf[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* The last byte has to indicate transfer done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (wait_master_done(adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) while (i < (len-1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) data = buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) WR(adap, PSC_SMBTXRX, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (wait_ack(adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* The last byte has to indicate transfer done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) data = buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data |= PSC_SMBTXRX_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) WR(adap, PSC_SMBTXRX, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (wait_master_done(adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct i2c_au1550_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct i2c_msg *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (i = 0; !err && i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) p = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) err = do_address(adap, p->addr, p->flags & I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (p->len == 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (err || !p->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (p->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) err = i2c_read(adap, p->buf, p->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) err = i2c_write(adap, p->buf, p->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Return the number of messages processed, or the error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (err == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static u32 au1550_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct i2c_algorithm au1550_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .master_xfer = au1550_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .functionality = au1550_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void i2c_au1550_setup(struct i2c_au1550_data *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) WR(priv, PSC_SMBCFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) WR(priv, PSC_SMBCFG, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Divide by 8 to get a 6.25 MHz clock. The later protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * timings are based on this clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) WR(priv, PSC_SMBCFG, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Set the protocol timer values. See Table 71 in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Au1550 Data Book for standard timing values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PSC_SMBTMR_SET_PU(20) | PSC_SMBTMR_SET_SH(20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PSC_SMBTMR_SET_SU(20) | PSC_SMBTMR_SET_CL(20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PSC_SMBTMR_SET_CH(20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cfg |= PSC_SMBCFG_DE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) WR(priv, PSC_SMBCFG, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void i2c_au1550_disable(struct i2c_au1550_data *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) WR(priv, PSC_SMBCFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * registering functions to load algorithms at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Prior to calling us, the 50MHz clock frequency and routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * must have been set up for the PSC indicated by the adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) i2c_au1550_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct i2c_au1550_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_au1550_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) priv->psc_base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (IS_ERR(priv->psc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return PTR_ERR(priv->psc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) priv->xfer_timeout = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) priv->adap.nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) priv->adap.algo = &au1550_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) priv->adap.algo_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) priv->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Now, set up the PSC for SMBus PIO mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) i2c_au1550_setup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = i2c_add_numbered_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) i2c_au1550_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int i2c_au1550_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) i2c_au1550_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int i2c_au1550_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct i2c_au1550_data *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) i2c_au1550_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int i2c_au1550_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct i2c_au1550_data *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) i2c_au1550_setup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct dev_pm_ops i2c_au1550_pmops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .suspend = i2c_au1550_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .resume = i2c_au1550_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define AU1XPSC_SMBUS_PMOPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct platform_driver au1xpsc_smbus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "au1xpsc_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .pm = AU1XPSC_SMBUS_PMOPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .probe = i2c_au1550_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .remove = i2c_au1550_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) module_platform_driver(au1xpsc_smbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MODULE_ALIAS("platform:au1xpsc_smbus");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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