^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Weinmann Medical GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Nikolaus Voss <n.voss@weinmann.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Evolved from original work by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2004 Rick Bronson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Borrowed heavily from original work by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_data/dma-atmel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AUTOSUSPEND_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AT91_I2C_MAX_ALT_CMD_DATA_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* AT91 TWI register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AT91_TWI_CR 0x0000 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AT91_TWI_START BIT(0) /* Send a Start Condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AT91_TWI_SWRST BIT(7) /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AT91_TWI_CLEAR BIT(15) /* Bus clear command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AT91_TWI_MMR 0x0004 /* Master Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AT91_TWI_MREAD BIT(12) /* Master Read Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AT91_TWI_SMR 0x0008 /* Slave Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AT91_TWI_SMR_SADR_MAX 0x007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AT91_TWI_SMR_SADR(x) (((x) & AT91_TWI_SMR_SADR_MAX) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AT91_TWI_IADR 0x000c /* Internal Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AT91_TWI_CWGR_HOLD_MAX 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AT91_TWI_SR 0x0020 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AT91_TWI_SVREAD BIT(3) /* Slave Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AT91_TWI_SVACC BIT(4) /* Slave Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AT91_TWI_OVRE BIT(6) /* Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AT91_TWI_UNRE BIT(7) /* Underrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AT91_TWI_EOSACC BIT(11) /* End Of Slave Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AT91_TWI_SCL BIT(24) /* TWI SCL status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AT91_TWI_SDA BIT(25) /* TWI SDA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AT91_TWI_INT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) | AT91_TWI_SVACC | AT91_TWI_EOSACC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AT91_TWI_ACR_DATAL_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AT91_TWI_ACR_DATAL(len) ((len) & AT91_TWI_ACR_DATAL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AT91_TWI_ACR_DIR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AT91_TWI_FILTR 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AT91_TWI_FILTR_FILT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AT91_TWI_FILTR_PADFEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AT91_TWI_FILTR_THRES(v) ((v) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AT91_TWI_FILTR_THRES_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AT91_TWI_FILTR_THRES_MASK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AT91_TWI_ONE_DATA 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AT91_TWI_TWO_DATA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AT91_TWI_FOUR_DATA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AT91_TWI_FLR 0x0054 /* FIFO Level Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AT91_TWI_FSR 0x0060 /* FIFO Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AT91_TWI_VER 0x00fc /* Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct at91_twi_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned clk_max_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned clk_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bool has_unre_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bool has_alt_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bool has_hold_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool has_dig_filtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool has_adv_dig_filtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bool has_ana_filtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) bool has_clear_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct at_dma_slave dma_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct at91_twi_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct dma_chan *chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct dma_chan *chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct scatterlist sg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct dma_async_tx_descriptor *data_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum dma_data_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool buf_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool xfer_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct at91_twi_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct completion cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) size_t buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned transfer_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned twi_cwgr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct at91_twi_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bool use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool use_alt_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool recv_len_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct at91_twi_dma dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bool slave_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct i2c_bus_recovery_info rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned smr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct i2c_client *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool enable_dig_filt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bool enable_ana_filt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 filter_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void at91_disable_twi_interrupts(struct at91_twi_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void at91_twi_irq_save(struct at91_twi_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void at91_twi_irq_restore(struct at91_twi_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void at91_init_twi_bus(struct at91_twi_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void at91_init_twi_bus_master(struct at91_twi_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int at91_twi_probe_master(struct platform_device *pdev, u32 phy_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct at91_twi_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void at91_init_twi_bus_slave(struct at91_twi_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int at91_twi_probe_slave(struct platform_device *pdev, u32 phy_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct at91_twi_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static inline void at91_init_twi_bus_slave(struct at91_twi_dev *dev) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline int at91_twi_probe_slave(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 phy_addr, struct at91_twi_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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