^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Aspeed 24XX/25XX I2C Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012-2017 ASPEED Technology Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2017 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2017 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* I2C Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ASPEED_I2C_FUN_CTRL_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ASPEED_I2C_AC_TIMING_REG1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ASPEED_I2C_AC_TIMING_REG2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ASPEED_I2C_INTR_CTRL_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ASPEED_I2C_INTR_STS_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ASPEED_I2C_CMD_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ASPEED_I2C_DEV_ADDR_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ASPEED_I2C_BYTE_BUF_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Global Register Definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* 0x00 : I2C Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* 0x08 : I2C Interrupt Target Assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Device Register Definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* 0x00 : I2CD Function Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ASPEED_I2CD_SLAVE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ASPEED_I2CD_MASTER_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ASPEED_NO_TIMEOUT_CTRL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* 0x0c : I2CD Interrupt Control Register &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 0x10 : I2CD Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * These share bit definitions, so use the same values for the enable &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * status bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ASPEED_I2CD_INTR_RECV_MASK 0xf000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ASPEED_I2CD_INTR_ABNORMAL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ASPEED_I2CD_INTR_RX_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ASPEED_I2CD_INTR_TX_NAK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ASPEED_I2CD_INTR_TX_ACK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ASPEED_I2CD_INTR_MASTER_ERRORS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ASPEED_I2CD_INTR_SCL_TIMEOUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ASPEED_I2CD_INTR_ABNORMAL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ASPEED_I2CD_INTR_ARBIT_LOSS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ASPEED_I2CD_INTR_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ASPEED_I2CD_INTR_SCL_TIMEOUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ASPEED_I2CD_INTR_ABNORMAL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ASPEED_I2CD_INTR_NORMAL_STOP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ASPEED_I2CD_INTR_ARBIT_LOSS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ASPEED_I2CD_INTR_RX_DONE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ASPEED_I2CD_INTR_TX_NAK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ASPEED_I2CD_INTR_TX_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* 0x14 : I2CD Command/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ASPEED_I2CD_SCL_LINE_STS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ASPEED_I2CD_SDA_LINE_STS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ASPEED_I2CD_BUS_BUSY_STS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Command Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ASPEED_I2CD_M_STOP_CMD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ASPEED_I2CD_M_RX_CMD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ASPEED_I2CD_S_TX_CMD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ASPEED_I2CD_M_TX_CMD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ASPEED_I2CD_M_START_CMD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ASPEED_I2CD_MASTER_CMDS_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (ASPEED_I2CD_M_STOP_CMD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ASPEED_I2CD_M_S_RX_CMD_LAST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ASPEED_I2CD_M_RX_CMD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ASPEED_I2CD_M_TX_CMD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ASPEED_I2CD_M_START_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* 0x18 : I2CD Slave Device Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum aspeed_i2c_master_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ASPEED_I2C_MASTER_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ASPEED_I2C_MASTER_PENDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ASPEED_I2C_MASTER_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ASPEED_I2C_MASTER_TX_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ASPEED_I2C_MASTER_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ASPEED_I2C_MASTER_RX_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ASPEED_I2C_MASTER_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ASPEED_I2C_MASTER_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum aspeed_i2c_slave_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ASPEED_I2C_SLAVE_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ASPEED_I2C_SLAVE_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ASPEED_I2C_SLAVE_READ_REQUESTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ASPEED_I2C_SLAVE_READ_PROCESSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ASPEED_I2C_SLAVE_WRITE_REQUESTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ASPEED_I2C_SLAVE_WRITE_RECEIVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ASPEED_I2C_SLAVE_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct aspeed_i2c_bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Synchronizes I/O mem access to base. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct completion cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 (*get_clk_reg_val)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long parent_clk_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 bus_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Transaction state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) enum aspeed_i2c_master_state master_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct i2c_msg *msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) size_t buf_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) size_t msgs_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) size_t msgs_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bool send_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Protected only by i2c_lock_bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int master_xfer_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Multi-master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bool multi_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct i2c_client *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum aspeed_i2c_slave_state slave_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif /* CONFIG_I2C_SLAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long time_left, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) command = readl(bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (command & ASPEED_I2CD_SDA_LINE_STS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Bus is idle: no recovery needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (command & ASPEED_I2CD_SCL_LINE_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reinit_completion(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) time_left = wait_for_completion_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) &bus->cmd_complete, bus->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (time_left == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else if (bus->cmd_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Recovery failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ASPEED_I2CD_SCL_LINE_STS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Bus error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) reinit_completion(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Writes 1 to 8 SCL clock cycles until SDA is released. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) writel(ASPEED_I2CD_BUS_RECOVER_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) time_left = wait_for_completion_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) &bus->cmd_complete, bus->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (time_left == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else if (bus->cmd_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Recovery failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ASPEED_I2CD_SDA_LINE_STS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) reset_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return aspeed_i2c_reset(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 command, irq_handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct i2c_client *slave = bus->slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) command = readl(bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Slave was requested, restart state machine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) irq_handled |= ASPEED_I2CD_INTR_SLAVE_MATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bus->slave_state = ASPEED_I2C_SLAVE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Slave is not currently active, irq was for someone else. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return irq_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) irq_status, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Slave was sent something. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Handle address frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (value & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bus->slave_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ASPEED_I2C_SLAVE_READ_REQUESTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bus->slave_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ASPEED_I2C_SLAVE_WRITE_REQUESTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Slave was asked to stop. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bus->slave_state = ASPEED_I2C_SLAVE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (irq_status & ASPEED_I2CD_INTR_TX_NAK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) bus->slave_state = ASPEED_I2C_SLAVE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) switch (bus->slave_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case ASPEED_I2C_SLAVE_READ_REQUESTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(bus->dev, "Unexpected ACK on read request.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case ASPEED_I2C_SLAVE_READ_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "Expected ACK after processed read.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case ASPEED_I2C_SLAVE_WRITE_REQUESTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case ASPEED_I2C_SLAVE_WRITE_RECEIVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case ASPEED_I2C_SLAVE_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case ASPEED_I2C_SLAVE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Slave was just started. Waiting for the next event. */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_err(bus->dev, "unknown slave_state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) bus->slave_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return irq_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif /* CONFIG_I2C_SLAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* precondition: bus.lock has been acquired. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 slave_addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * If it's requested in the middle of a slave session, set the master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * state to 'pending' then H/W will continue handling this master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * command when the bus comes back to the idle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) bus->master_state = ASPEED_I2C_MASTER_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif /* CONFIG_I2C_SLAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) bus->master_state = ASPEED_I2C_MASTER_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bus->buf_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) command |= ASPEED_I2CD_M_RX_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Need to let the hardware know to NACK after RX. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) writel(command, bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* precondition: bus.lock has been acquired. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bus->master_state = ASPEED_I2C_MASTER_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* precondition: bus.lock has been acquired. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (bus->msgs_index + 1 < bus->msgs_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) bus->msgs_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) aspeed_i2c_do_start(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) aspeed_i2c_do_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int aspeed_i2c_is_irq_error(u32 irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ASPEED_I2CD_INTR_SCL_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 irq_handled = 0, command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u8 recv_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto out_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * We encountered an interrupt that reports an error: the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * should clear the command queue effectively taking us back to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * INACTIVE state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = aspeed_i2c_is_irq_error(irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) bus->cmd_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) goto out_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Master is not currently active, irq was for someone else. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) bus->master_state == ASPEED_I2C_MASTER_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* We are in an invalid state; reset bus to a known state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!bus->msgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(bus->dev, "bus in unknown state. irq_status: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) bus->cmd_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (bus->master_state != ASPEED_I2C_MASTER_STOP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) bus->master_state != ASPEED_I2C_MASTER_INACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) aspeed_i2c_do_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) msg = &bus->msgs[bus->msgs_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * START is a special case because we still have to handle a subsequent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * TX or RX immediately after we handle it, so we handle it here and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * then update the state and handle the new state below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (bus->master_state == ASPEED_I2C_MASTER_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * If a peer master starts a xfer immediately after it queues a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * master command, clear the queued master command and change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * its state to 'pending'. To simplify handling of pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * cases, it uses S/W solution instead of H/W command queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (unlikely(irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) writel(readl(bus->base + ASPEED_I2C_CMD_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ~ASPEED_I2CD_MASTER_CMDS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bus->master_state = ASPEED_I2C_MASTER_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_dbg(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "master goes pending due to a slave start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif /* CONFIG_I2C_SLAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bus->cmd_err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) goto out_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pr_devel("no slave present at %02x\n", msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) bus->cmd_err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) aspeed_i2c_do_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (msg->len == 0) { /* SMBUS_QUICK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) aspeed_i2c_do_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) bus->master_state = ASPEED_I2C_MASTER_RX_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) bus->master_state = ASPEED_I2C_MASTER_TX_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) switch (bus->master_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case ASPEED_I2C_MASTER_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_dbg(bus->dev, "slave NACKed TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto error_and_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_err(bus->dev, "slave failed to ACK TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) goto error_and_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case ASPEED_I2C_MASTER_TX_FIRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (bus->buf_index < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) bus->master_state = ASPEED_I2C_MASTER_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) writel(msg->buf[bus->buf_index++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bus->base + ASPEED_I2C_BYTE_BUF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) writel(ASPEED_I2CD_M_TX_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) aspeed_i2c_next_msg_or_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case ASPEED_I2C_MASTER_RX_FIRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* RX may not have completed yet (only address cycle) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case ASPEED_I2C_MASTER_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_err(bus->dev, "master failed to RX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) goto error_and_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msg->buf[bus->buf_index++] = recv_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (msg->flags & I2C_M_RECV_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) bus->cmd_err = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) aspeed_i2c_do_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) msg->len = recv_byte +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) msg->flags &= ~I2C_M_RECV_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (bus->buf_index < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) bus->master_state = ASPEED_I2C_MASTER_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) command = ASPEED_I2CD_M_RX_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (bus->buf_index + 1 == msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writel(command, bus->base + ASPEED_I2C_CMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) aspeed_i2c_next_msg_or_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case ASPEED_I2C_MASTER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "master failed to STOP. irq_status:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) bus->cmd_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Do not STOP as we have already tried. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) goto out_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case ASPEED_I2C_MASTER_INACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "master received interrupt 0x%08x, but is inactive\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) bus->cmd_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Do not STOP as we should be inactive. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) goto out_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) WARN(1, "unknown master state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) bus->cmd_err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto out_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) error_and_stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) bus->cmd_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) aspeed_i2c_do_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) goto out_no_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) out_complete:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) bus->msgs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (bus->cmd_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) bus->master_xfer_result = bus->cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) bus->master_xfer_result = bus->msgs_index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) complete(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) out_no_complete:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return irq_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct aspeed_i2c_bus *bus = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 irq_received, irq_remaining, irq_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) spin_lock(&bus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Ack all interrupts except for Rx done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) bus->base + ASPEED_I2C_INTR_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) readl(bus->base + ASPEED_I2C_INTR_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) irq_received &= ASPEED_I2CD_INTR_RECV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) irq_remaining = irq_received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * In most cases, interrupt bits will be set one by one, although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * multiple interrupt bits could be set at the same time. It's also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * possible that master interrupt bits could be set along with slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * interrupt bits. Each case needs to be handled using corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * handlers depending on the current state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) bus->master_state != ASPEED_I2C_MASTER_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) irq_remaining &= ~irq_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (irq_remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) irq_handled |= aspeed_i2c_slave_irq(bus, irq_remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) irq_handled = aspeed_i2c_slave_irq(bus, irq_remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) irq_remaining &= ~irq_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (irq_remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) irq_handled |= aspeed_i2c_master_irq(bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) irq_remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Start a pending master command at here if a slave operation is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (bus->master_state == ASPEED_I2C_MASTER_PENDING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) aspeed_i2c_do_start(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #endif /* CONFIG_I2C_SLAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) irq_remaining &= ~irq_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (irq_remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) "irq handled != irq. expected 0x%08x, but was 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) irq_received, irq_handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Ack Rx done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (irq_received & ASPEED_I2CD_INTR_RX_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel(ASPEED_I2CD_INTR_RX_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) bus->base + ASPEED_I2C_INTR_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) readl(bus->base + ASPEED_I2C_INTR_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) spin_unlock(&bus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return irq_remaining ? IRQ_NONE : IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned long time_left, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) bus->cmd_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* If bus is busy in a single master environment, attempt recovery. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!bus->multi_master &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) (readl(bus->base + ASPEED_I2C_CMD_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ASPEED_I2CD_BUS_BUSY_STS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = aspeed_i2c_recover_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) bus->cmd_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) bus->msgs = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) bus->msgs_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) bus->msgs_count = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) reinit_completion(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) aspeed_i2c_do_start(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) time_left = wait_for_completion_timeout(&bus->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) bus->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * If timed out and bus is still busy in a multi master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * environment, attempt recovery at here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (bus->multi_master &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) (readl(bus->base + ASPEED_I2C_CMD_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ASPEED_I2CD_BUS_BUSY_STS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) aspeed_i2c_recover_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * If timed out and the state is still pending, drop the pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * master command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (bus->master_state == ASPEED_I2C_MASTER_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return bus->master_xfer_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* precondition: bus.lock has been acquired. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 addr_reg_val, func_ctrl_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Set slave addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Turn on slave mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int aspeed_i2c_reg_slave(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (bus->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) __aspeed_i2c_reg_slave(bus, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) bus->slave = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int aspeed_i2c_unreg_slave(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 func_ctrl_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!bus->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Turn off slave mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) bus->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #endif /* CONFIG_I2C_SLAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const struct i2c_algorithm aspeed_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .master_xfer = aspeed_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .functionality = aspeed_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .reg_slave = aspeed_i2c_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .unreg_slave = aspeed_i2c_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #endif /* CONFIG_I2C_SLAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 clk_high_low_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * SCL_high and SCL_low represent a value 1 greater than what is stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * since a zero divider is meaningless. Thus, the max value each can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * store is every bit set + 1. Since SCL_high and SCL_low are added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * together (see below), the max value of both is the max value of one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * them times two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) clk_high_low_max = (clk_high_low_mask + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * The actual clock frequency of SCL is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * = APB_freq / divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * where base_freq is a programmable clock divider; its value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * base_freq = 1 << base_clk_divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * SCL_high is the number of base_freq clock cycles that SCL stays high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * and SCL_low is the number of base_freq clock cycles that SCL stays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * low for a period of SCL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * The actual register has a minimum SCL_high and SCL_low minimum of 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * thus, they start counting at zero. So
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * SCL_high = clk_high + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * SCL_low = clk_low + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * Thus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * SCL_freq = APB_freq /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * The documentation recommends clk_high >= clk_high_max / 2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * gives us the following solution:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) base_clk_divisor = divisor > clk_high_low_max ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) clk_low = clk_high_low_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) clk_high = clk_high_low_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) divisor, (1 << base_clk_divisor) * clk_high_low_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) tmp = (divisor + (1 << base_clk_divisor) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) >> base_clk_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) clk_low = tmp / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) clk_high = tmp - clk_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (clk_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) clk_high--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (clk_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) clk_low--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) & ASPEED_I2CD_TIME_SCL_HIGH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) & ASPEED_I2CD_TIME_SCL_LOW_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) | (base_clk_divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * clk_high and clk_low are each 3 bits wide, so each can hold a max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * value of 8 giving a clk_high_low_max of 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * clk_high and clk_low are each 4 bits wide, so each can hold a max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * value of 16 giving a clk_high_low_max of 32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* precondition: bus.lock has been acquired. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 divisor, clk_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ASPEED_I2CD_TIME_THDSTA_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ASPEED_I2CD_TIME_TACST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* precondition: bus.lock has been acquired. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Disable everything. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret = aspeed_i2c_init_clk(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (of_property_read_bool(pdev->dev.of_node, "multi-master"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) bus->multi_master = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Enable Master Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) bus->base + ASPEED_I2C_FUN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* If slave has already been registered, re-enable it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (bus->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) __aspeed_i2c_reg_slave(bus, bus->slave->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #endif /* CONFIG_I2C_SLAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Set interrupt generation of I2C controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct platform_device *pdev = to_platform_device(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Disable and ack all interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ret = aspeed_i2c_init(bus, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const struct of_device_id aspeed_i2c_bus_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .compatible = "aspeed,ast2400-i2c-bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .data = aspeed_i2c_24xx_get_clk_reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .compatible = "aspeed,ast2500-i2c-bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .data = aspeed_i2c_25xx_get_clk_reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .compatible = "aspeed,ast2600-i2c-bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .data = aspeed_i2c_25xx_get_clk_reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int aspeed_i2c_probe_bus(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct aspeed_i2c_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct clk *parent_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) bus->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (IS_ERR(bus->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return PTR_ERR(bus->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) parent_clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (IS_ERR(parent_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return PTR_ERR(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) bus->parent_clk_frequency = clk_get_rate(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* We just need the clock rate, we don't actually use the clk object. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) devm_clk_put(&pdev->dev, parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (IS_ERR(bus->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) "missing or invalid reset controller device tree entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return PTR_ERR(bus->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) reset_control_deassert(bus->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret = of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) "bus-frequency", &bus->bus_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) "Could not read bus-frequency property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) bus->bus_frequency = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) bus->get_clk_reg_val = (u32 (*)(struct device *, u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Initialize the I2C adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) spin_lock_init(&bus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) init_completion(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) bus->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) bus->adap.retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) bus->adap.algo = &aspeed_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) bus->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) bus->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) i2c_set_adapdata(&bus->adap, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) bus->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Clean up any left over interrupt state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * bus.lock does not need to be held because the interrupt handler has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * not been enabled yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ret = aspeed_i2c_init(bus, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) 0, dev_name(&pdev->dev), bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret = i2c_add_adapter(&bus->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) platform_set_drvdata(pdev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) bus->adap.nr, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int aspeed_i2c_remove_bus(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* Disable everything. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) reset_control_assert(bus->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) i2c_del_adapter(&bus->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static struct platform_driver aspeed_i2c_bus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .probe = aspeed_i2c_probe_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .remove = aspeed_i2c_remove_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .name = "aspeed-i2c-bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .of_match_table = aspeed_i2c_bus_of_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) module_platform_driver(aspeed_i2c_bus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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