Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)     Copyright (c) 1999-2002 Merlin Hughes <merlin@merlin.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)     Shamelessly ripped from i2c-piix4.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)     Copyright (c) 1998, 1999  Frodo Looijaard <frodol@dds.nl> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)     Philip Edelbrock <phil@netroedge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)     2002-04-08: Added nForce support. (Csaba Halasz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)     2002-10-03: Fixed nForce PnP I/O port. (Michael Steil)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)     2002-12-28: Rewritten into something that resembles a Linux driver (hch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)     2003-11-29: Added back AMD8111 removed by the previous rewrite.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)                 (Philip Pokorny)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)    Supports AMD756, AMD766, AMD768, AMD8111 and nVidia nForce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)    Note: we assume there can only be one device, with one SMBus interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* AMD756 SMBus address offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SMB_ADDR_OFFSET		0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SMB_IOSIZE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SMB_GLOBAL_STATUS	(0x0 + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SMB_GLOBAL_ENABLE	(0x2 + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SMB_HOST_ADDRESS	(0x4 + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SMB_HOST_DATA		(0x6 + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SMB_HOST_COMMAND	(0x8 + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SMB_HOST_BLOCK_DATA	(0x9 + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SMB_HAS_DATA		(0xA + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SMB_HAS_DEVICE_ADDRESS	(0xC + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SMB_HAS_HOST_ADDRESS	(0xE + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SMB_SNOOP_ADDRESS	(0xF + amd756_ioport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* PCI Address Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* address of I/O space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SMBBA		0x058		/* mh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SMBBANFORCE	0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* general configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SMBGCFG		0x041		/* mh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* silicon revision code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SMBREV		0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* Other settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MAX_TIMEOUT	500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* AMD756 constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AMD756_QUICK		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AMD756_BYTE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AMD756_BYTE_DATA	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define AMD756_WORD_DATA	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AMD756_PROCESS_CALL	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AMD756_BLOCK_DATA	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static struct pci_driver amd756_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static unsigned short amd756_ioport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)   SMBUS event = I/O 28-29 bit 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)      see E0 for the status bits and enabled in E2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)      
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define GS_ABRT_STS	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define GS_COL_STS	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define GS_PRERR_STS	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define GS_HST_STS	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define GS_HCYC_STS	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define GS_TO_STS	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define GS_SMB_STS	(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GS_CLEAR_STS	(GS_ABRT_STS | GS_COL_STS | GS_PRERR_STS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			 GS_HCYC_STS | GS_TO_STS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define GE_CYC_TYPE_MASK	(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define GE_HOST_STC		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define GE_ABORT		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static int amd756_transaction(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	dev_dbg(&adap->dev, "Transaction (pre): GS=%04x, GE=%04x, ADD=%04x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		"DAT=%04x\n", inw_p(SMB_GLOBAL_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		inw_p(SMB_GLOBAL_ENABLE), inw_p(SMB_HOST_ADDRESS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		inb_p(SMB_HOST_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* Make sure the SMBus host is ready to start transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if ((temp = inw_p(SMB_GLOBAL_STATUS)) & (GS_HST_STS | GS_SMB_STS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		dev_dbg(&adap->dev, "SMBus busy (%04x). Waiting...\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			temp = inw_p(SMB_GLOBAL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		} while ((temp & (GS_HST_STS | GS_SMB_STS)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		         (timeout++ < MAX_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		/* If the SMBus is still busy, we give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (timeout > MAX_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			dev_dbg(&adap->dev, "Busy wait timeout (%04x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* start the transaction by setting the start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	outw_p(inw(SMB_GLOBAL_ENABLE) | GE_HOST_STC, SMB_GLOBAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* We will always wait for a fraction of a second! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		temp = inw_p(SMB_GLOBAL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	} while ((temp & GS_HST_STS) && (timeout++ < MAX_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* If the SMBus is still busy, we give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (timeout > MAX_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		dev_dbg(&adap->dev, "Completion timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (temp & GS_PRERR_STS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		result = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		dev_dbg(&adap->dev, "SMBus Protocol error (no response)!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (temp & GS_COL_STS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		dev_warn(&adap->dev, "SMBus collision!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (temp & GS_TO_STS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		dev_dbg(&adap->dev, "SMBus protocol timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (temp & GS_HCYC_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		dev_dbg(&adap->dev, "SMBus protocol success!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (((temp = inw_p(SMB_GLOBAL_STATUS)) & GS_CLEAR_STS) != 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			"Failed reset at end of transaction (%04x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		"Transaction (post): GS=%04x, GE=%04x, ADD=%04x, DAT=%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		inw_p(SMB_GLOBAL_STATUS), inw_p(SMB_GLOBAL_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		inw_p(SMB_HOST_ADDRESS), inb_p(SMB_HOST_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	dev_warn(&adap->dev, "Sending abort\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	outw_p(inw(SMB_GLOBAL_ENABLE) | GE_ABORT, SMB_GLOBAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Return negative errno on error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static s32 amd756_access(struct i2c_adapter * adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		  unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		  u8 command, int size, union i2c_smbus_data * data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		       SMB_HOST_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		size = AMD756_QUICK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		       SMB_HOST_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			outb_p(command, SMB_HOST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		size = AMD756_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		       SMB_HOST_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		outb_p(command, SMB_HOST_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			outw_p(data->byte, SMB_HOST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		size = AMD756_BYTE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		       SMB_HOST_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		outb_p(command, SMB_HOST_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			outw_p(data->word, SMB_HOST_DATA);	/* TODO: endian???? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		size = AMD756_WORD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		       SMB_HOST_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		outb_p(command, SMB_HOST_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			if (len < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			if (len > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				len = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			outw_p(len, SMB_HOST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			for (i = 1; i <= len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				outb_p(data->block[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				       SMB_HOST_BLOCK_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		size = AMD756_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* How about enabling interrupts... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	outw_p(size & GE_CYC_TYPE_MASK, SMB_GLOBAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	status = amd756_transaction(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if ((read_write == I2C_SMBUS_WRITE) || (size == AMD756_QUICK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	case AMD756_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		data->byte = inw_p(SMB_HOST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	case AMD756_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		data->byte = inw_p(SMB_HOST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	case AMD756_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		data->word = inw_p(SMB_HOST_DATA);	/* TODO: endian???? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	case AMD756_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		if(data->block[0] > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			data->block[0] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		for (i = 1; i <= data->block[0]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			data->block[i] = inb_p(SMB_HOST_BLOCK_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static u32 amd756_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	    I2C_FUNC_SMBUS_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.smbus_xfer	= amd756_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.functionality	= amd756_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct i2c_adapter amd756_smbus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.algo		= &smbus_algorithm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) enum chiptype { AMD756, AMD766, AMD768, NFORCE, AMD8111 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const char* chipname[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	"AMD756", "AMD766", "AMD768",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	"nVidia nForce", "AMD8111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct pci_device_id amd756_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	  .driver_data = AMD756 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	  .driver_data = AMD766 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7443),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	  .driver_data = AMD768 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	  .driver_data = AMD8111 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	  .driver_data = NFORCE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	{ 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_DEVICE_TABLE (pci, amd756_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int amd756_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	int nforce = (id->driver_data == NFORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (amd756_ioport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		dev_err(&pdev->dev, "Only one device supported "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		       "(you have a strange motherboard, btw)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (nforce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		if (PCI_FUNC(pdev->devfn) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		pci_read_config_word(pdev, SMBBANFORCE, &amd756_ioport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		amd756_ioport &= 0xfffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	} else { /* amd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		if (PCI_FUNC(pdev->devfn) != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		pci_read_config_byte(pdev, SMBGCFG, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		if ((temp & 128) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				"Error: SMBus controller I/O not enabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		/* Determine the address of the SMBus areas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		/* Technically it is a dword but... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		pci_read_config_word(pdev, SMBBA, &amd756_ioport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		amd756_ioport &= 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		amd756_ioport += SMB_ADDR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	error = acpi_check_region(amd756_ioport, SMB_IOSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 				  amd756_driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (!request_region(amd756_ioport, SMB_IOSIZE, amd756_driver.name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		dev_err(&pdev->dev, "SMB region 0x%x already in use!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			amd756_ioport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	pci_read_config_byte(pdev, SMBREV, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	dev_dbg(&pdev->dev, "SMBREV = 0x%X\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	dev_dbg(&pdev->dev, "AMD756_smba = 0x%X\n", amd756_ioport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	/* set up the sysfs linkage to our parent device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	amd756_smbus.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	snprintf(amd756_smbus.name, sizeof(amd756_smbus.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		 "SMBus %s adapter at %04x", chipname[id->driver_data],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		 amd756_ioport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	error = i2c_add_adapter(&amd756_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)  out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	release_region(amd756_ioport, SMB_IOSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void amd756_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	i2c_del_adapter(&amd756_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	release_region(amd756_ioport, SMB_IOSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct pci_driver amd756_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	.name		= "amd756_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	.id_table	= amd756_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	.probe		= amd756_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	.remove		= amd756_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) module_pci_driver(amd756_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_AUTHOR("Merlin Hughes <merlin@merlin.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_DESCRIPTION("AMD756/766/768/8111 and nVidia nForce SMBus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) EXPORT_SYMBOL(amd756_smbus);