^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AMD MP2 I2C adapter driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Elie Morisse <syniurge@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef I2C_AMD_PCI_MP2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define I2C_AMD_PCI_MP2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCI_DEVICE_ID_AMD_MP2 0x15E6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct amd_i2c_common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct amd_mp2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* MP2 C2P Message Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) AMD_C2P_MSG0 = 0x10500, /* MP2 Message for I2C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) AMD_C2P_MSG1 = 0x10504, /* MP2 Message for I2C1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) AMD_C2P_MSG2 = 0x10508, /* DRAM Address Lo / Data 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) AMD_C2P_MSG3 = 0x1050c, /* DRAM Address HI / Data 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) AMD_C2P_MSG4 = 0x10510, /* Data 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) AMD_C2P_MSG5 = 0x10514, /* Data 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) AMD_C2P_MSG6 = 0x10518, /* Data 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) AMD_C2P_MSG7 = 0x1051c, /* Data 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) AMD_C2P_MSG8 = 0x10520, /* Data 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) AMD_C2P_MSG9 = 0x10524, /* Data 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* MP2 P2C Message Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) AMD_P2C_MSG0 = 0x10680, /* Do not use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) AMD_P2C_MSG1 = 0x10684, /* I2C0 interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) AMD_P2C_MSG2 = 0x10688, /* I2C1 interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) AMD_P2C_MSG3 = 0x1068C, /* MP2 debug info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) AMD_P2C_MSG_INTEN = 0x10690, /* MP2 interrupt gen register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) AMD_P2C_MSG_INTSTS = 0x10694, /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Command register data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define i2c_none (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum i2c_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) i2c_read = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) i2c_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) i2c_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) i2c_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) number_of_sensor_discovered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) is_mp2_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) invalid_cmd = 0xF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum speed_enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) speed100k = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) speed400k = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) speed1000k = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) speed1400k = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) speed3400k = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) enum mem_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) use_dram = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) use_c2pmsg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * union i2c_cmd_base : bit access of C2P commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @i2c_cmd: bit 0..3 i2c R/W command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @bus_id: bit 4..7 i2c bus index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @slave_addr: bit 8..15 slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @length: bit 16..27 read/write length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @i2c_speed: bit 28..30 bus speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @mem_type: bit 31 0-DRAM; 1-C2P msg o/p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) union i2c_cmd_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum i2c_cmd i2c_cmd : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 bus_id : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 slave_addr : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 length : 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum speed_enum i2c_speed : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enum mem_type mem_type : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum response_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) invalid_response = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) command_success = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) command_failed = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum status_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) i2c_readcomplete_event = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) i2c_readfail_event = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) i2c_writecomplete_event = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) i2c_writefail_event = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) i2c_busenable_complete = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) i2c_busenable_failed = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) i2c_busdisable_complete = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) i2c_busdisable_failed = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) invalid_data_length = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) invalid_slave_address = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) invalid_i2cbus_id = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) invalid_dram_addr = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) invalid_command = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mp2_active = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) numberof_sensors_discovered_resp = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) i2c_bus_notinitialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * union i2c_event : bit access of P2C events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @response: bit 0..1 i2c response type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @status: bit 2..6 status_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @mem_type: bit 7 0-DRAM; 1-C2P msg o/p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @bus_id: bit 8..11 i2c bus id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @length: bit 12..23 message length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @slave_addr: bit 24-31 slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) union i2c_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum response_type response : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum status_type status : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum mem_type mem_type : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 bus_id : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 length : 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 slave_addr : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * struct amd_i2c_common - per bus/i2c adapter context, shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * between the pci and the platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @eventval: MP2 event value set by the IRQ handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @mp2_dev: MP2 pci device this adapter is part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @msg: i2c message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @cmd_completion: function called by the IRQ handler to signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * the platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @reqcmd: requested i2c command type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @cmd_success: set to true if the MP2 responded to a command with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * the expected status and response type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @bus_id: bus index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @i2c_speed: i2c bus speed determined by the slowest slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @dma_buf: if msg length > 32, holds the DMA buffer virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @dma_addr: if msg length > 32, holds the DMA buffer address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct amd_i2c_common {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) union i2c_event eventval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct amd_mp2_dev *mp2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void (*cmd_completion)(struct amd_i2c_common *i2c_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enum i2c_cmd reqcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 cmd_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enum speed_enum i2c_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 *dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int (*suspend)(struct amd_i2c_common *i2c_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int (*resume)(struct amd_i2c_common *i2c_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * struct amd_mp2_dev - per PCI device context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @pci_dev: PCI driver node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @busses: MP2 devices may have up to two busses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * each bus corresponding to an i2c adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @mmio: iommapped registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @c2p_lock: controls access to the C2P mailbox shared between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * the two adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @c2p_lock_busid: id of the adapter which locked c2p_lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct amd_mp2_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct amd_i2c_common *busses[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct mutex c2p_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 c2p_lock_busid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int probed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ndev_pdev(ndev) ((ndev)->pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ndev_name(ndev) pci_name(ndev_pdev(ndev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define work_amd_i2c_common(__work) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) container_of(__work, struct amd_i2c_common, work.work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* PCIe communication driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int amd_mp2_rw(struct amd_i2c_common *i2c_common, enum i2c_cmd reqcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int amd_mp2_bus_enable_set(struct amd_i2c_common *i2c_common, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void amd_mp2_process_event(struct amd_i2c_common *i2c_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void amd_mp2_rw_timeout(struct amd_i2c_common *i2c_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int amd_mp2_register_cb(struct amd_i2c_common *i2c_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int amd_mp2_unregister_cb(struct amd_i2c_common *i2c_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct amd_mp2_dev *amd_mp2_find_device(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline void amd_mp2_pm_runtime_get(struct amd_mp2_dev *mp2_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pm_runtime_get_sync(&mp2_dev->pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline void amd_mp2_pm_runtime_put(struct amd_mp2_dev *mp2_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pm_runtime_mark_last_busy(&mp2_dev->pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pm_runtime_put_autosuspend(&mp2_dev->pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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