^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright Intel Corporation (C) 2017.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on the i2c-axxia.c driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ALTR_I2C_TFR_CMD 0x00 /* Transfer Command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ALTR_I2C_TFR_CMD_STA BIT(9) /* send START before byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ALTR_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ALTR_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ALTR_I2C_RX_DATA 0x04 /* RX data FIFO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ALTR_I2C_CTRL 0x08 /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ALTR_I2C_CTRL_RXT_SHFT 4 /* RX FIFO Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ALTR_I2C_CTRL_TCT_SHFT 2 /* TFER CMD FIFO Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ALTR_I2C_CTRL_BSPEED BIT(1) /* Bus Speed (1=Fast) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ALTR_I2C_CTRL_EN BIT(0) /* Enable Core (1=Enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ALTR_I2C_ISER 0x0C /* Interrupt Status Enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ALTR_I2C_ISER_RXOF_EN BIT(4) /* Enable RX OVERFLOW IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ALTR_I2C_ISER_ARB_EN BIT(3) /* Enable ARB LOST IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ALTR_I2C_ISER_NACK_EN BIT(2) /* Enable NACK DET IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ALTR_I2C_ISER_RXRDY_EN BIT(1) /* Enable RX Ready IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ALTR_I2C_ISER_TXRDY_EN BIT(0) /* Enable TX Ready IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ALTR_I2C_ISR 0x10 /* Interrupt Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ALTR_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ALTR_I2C_ISR_ARB BIT(3) /* ARB LOST IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ALTR_I2C_ISR_NACK BIT(2) /* NACK DET IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ALTR_I2C_ISR_RXRDY BIT(1) /* RX Ready IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ALTR_I2C_ISR_TXRDY BIT(0) /* TX Ready IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ALTR_I2C_STATUS 0x14 /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ALTR_I2C_STAT_CORE BIT(0) /* Core Status (0=idle) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ALTR_I2C_TC_FIFO_LVL 0x18 /* Transfer FIFO LVL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ALTR_I2C_RX_FIFO_LVL 0x1C /* Receive FIFO LVL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ALTR_I2C_SCL_LOW 0x20 /* SCL low count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ALTR_I2C_SCL_HIGH 0x24 /* SCL high count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ALTR_I2C_SDA_HOLD 0x28 /* SDA hold count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ALTR_I2C_ALL_IRQ (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ALTR_I2C_ISR_TXRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ALTR_I2C_THRESHOLD 0 /* IRQ Threshold at 1 element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ALTR_I2C_DFLT_FIFO_SZ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ALTR_I2C_TIMEOUT 100000 /* 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ALTR_I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * altr_i2c_dev - I2C device context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @base: pointer to register struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @msg: pointer to current message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @msg_len: number of bytes transferred in msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @msg_err: error code for completed message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @msg_complete: xfer completion object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @dev: device reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @adapter: core i2c abstraction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @i2c_clk: clock reference for i2c input clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @bus_clk_rate: current i2c bus clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @buf: ptr to msg buffer for easier use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @fifo_size: size of the FIFO passed in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @isr_mask: cached copy of local ISR enables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @isr_status: cached copy of local ISR status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @isr_mutex: mutex for IRQ thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct altr_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) size_t msg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int msg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct completion msg_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk *i2c_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 bus_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 isr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 isr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mutex isr_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int_en = readl(idev->base + ALTR_I2C_ISER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) idev->isr_mask = int_en | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) idev->isr_mask = int_en & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 int_en = readl(idev->base + ALTR_I2C_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel(int_en | mask, idev->base + ALTR_I2C_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void altr_i2c_core_disable(struct altr_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void altr_i2c_core_enable(struct altr_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void altr_i2c_reset(struct altr_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) altr_i2c_core_disable(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) altr_i2c_core_enable(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline void altr_i2c_stop(struct altr_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void altr_i2c_init(struct altr_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 t_high, t_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tmp &= ~ALTR_I2C_CTRL_BSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Standard mode SCL 50/50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) t_high = divisor * 1 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) t_low = divisor * 1 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tmp |= ALTR_I2C_CTRL_BSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Fast mode SCL 33/66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) t_high = divisor * 1 / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) t_low = divisor * 2 / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel(tmp, idev->base + ALTR_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) idev->bus_clk_rate, clk_mhz, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Reset controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) altr_i2c_reset(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* SCL High Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel(t_high, idev->base + ALTR_I2C_SCL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* SCL Low Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* SDA Hold Time, 300ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(3 * clk_mhz / 10, idev->base + ALTR_I2C_SDA_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Mask all master interrupt bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * altr_i2c_transfer - On the last byte to be transmitted, send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * a Stop bit on the last byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* On the last byte to be transmitted, send STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (idev->msg_len == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) data |= ALTR_I2C_TFR_CMD_STO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (idev->msg_len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(data, idev->base + ALTR_I2C_TFR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * transfer. Send a Stop bit on the last byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) while (bytes_to_transfer-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) idev->msg_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) altr_i2c_transfer(idev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @return: Number of bytes left to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) size_t tx_fifo_avail = idev->fifo_size - readl(idev->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ALTR_I2C_TC_FIFO_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ret = idev->msg_len - bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) while (bytes_to_transfer-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) altr_i2c_transfer(idev, *idev->buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) idev->msg_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct altr_i2c_dev *idev = _dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) irqreturn_t ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Read IRQ status but only interested in Enabled IRQs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (idev->isr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static irqreturn_t altr_i2c_isr(int irq, void *_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bool read, finish = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct altr_i2c_dev *idev = _dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 status = idev->isr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mutex_lock(&idev->isr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!idev->msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_warn(idev->dev, "unexpected interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) read = (idev->msg->flags & I2C_M_RD) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* handle Lost Arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (unlikely(status & ALTR_I2C_ISR_ARB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) idev->msg_err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) finish = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else if (unlikely(status & ALTR_I2C_ISR_NACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_dbg(idev->dev, "Could not get ACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) idev->msg_err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) altr_i2c_int_clear(idev, ALTR_I2C_ISR_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) altr_i2c_stop(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) finish = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else if (read && unlikely(status & ALTR_I2C_ISR_RXOF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* handle RX FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) altr_i2c_empty_rx_fifo(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) altr_i2c_stop(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(idev->dev, "RX FIFO Overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) finish = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else if (read && (status & ALTR_I2C_ISR_RXRDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* RX FIFO needs service? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) altr_i2c_empty_rx_fifo(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!idev->msg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) finish = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else if (!read && (status & ALTR_I2C_ISR_TXRDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* TX FIFO needs service? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) altr_i2c_int_clear(idev, ALTR_I2C_ISR_TXRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (idev->msg_len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) altr_i2c_fill_tx_fifo(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) finish = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_warn(idev->dev, "Unexpected interrupt: 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (finish) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Wait for the Core to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) !(status & ALTR_I2C_STAT_CORE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 1, ALTR_I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(idev->dev, "message timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) complete(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_dbg(idev->dev, "Message Complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mutex_unlock(&idev->isr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int altr_i2c_xfer_msg(struct altr_i2c_dev *idev, struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 imask = ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | ALTR_I2C_ISR_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mutex_lock(&idev->isr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) idev->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) idev->msg_len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) idev->buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) idev->msg_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) reinit_completion(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) altr_i2c_core_enable(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Make sure RX FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) readl(idev->base + ALTR_I2C_RX_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if ((msg->flags & I2C_M_RD) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) imask |= ALTR_I2C_ISER_RXOF_EN | ALTR_I2C_ISER_RXRDY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) altr_i2c_int_enable(idev, imask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* write the first byte to start the RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) altr_i2c_transfer(idev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) imask |= ALTR_I2C_ISR_TXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) altr_i2c_int_enable(idev, imask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) altr_i2c_fill_tx_fifo(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mutex_unlock(&idev->isr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) time_left = wait_for_completion_timeout(&idev->msg_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ALTR_I2C_XFER_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mutex_lock(&idev->isr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) altr_i2c_int_enable(idev, imask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_err(idev->dev, "Core Status not IDLE...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) idev->msg_err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_dbg(idev->dev, "Transaction timed out.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) altr_i2c_core_disable(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mutex_unlock(&idev->isr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return idev->msg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) altr_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct altr_i2c_dev *idev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = altr_i2c_xfer_msg(idev, msgs++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static u32 altr_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct i2c_algorithm altr_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .master_xfer = altr_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .functionality = altr_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int altr_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct altr_i2c_dev *idev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) idev->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (IS_ERR(idev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return PTR_ERR(idev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (IS_ERR(idev->i2c_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(&pdev->dev, "missing clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return PTR_ERR(idev->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) idev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) init_completion(&idev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mutex_init(&idev->isr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = device_property_read_u32(idev->dev, "fifo-size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) &idev->fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(&pdev->dev, "FIFO size set to default of %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ALTR_I2C_DFLT_FIFO_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) idev->fifo_size = ALTR_I2C_DFLT_FIFO_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = device_property_read_u32(idev->dev, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) &idev->bus_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(&pdev->dev, "Default to 100kHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (idev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(&pdev->dev, "invalid clock-frequency %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) idev->bus_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = devm_request_threaded_irq(&pdev->dev, irq, altr_i2c_isr_quick,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) altr_i2c_isr, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pdev->name, idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(&pdev->dev, "failed to claim IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = clk_prepare_enable(idev->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(&pdev->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mutex_lock(&idev->isr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) altr_i2c_init(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mutex_unlock(&idev->isr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) i2c_set_adapdata(&idev->adapter, idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) idev->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) idev->adapter.algo = &altr_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) idev->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) idev->adapter.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) platform_set_drvdata(pdev, idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = i2c_add_adapter(&idev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) clk_disable_unprepare(idev->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_info(&pdev->dev, "Altera SoftIP I2C Probe Complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int altr_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct altr_i2c_dev *idev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clk_disable_unprepare(idev->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) i2c_del_adapter(&idev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Match table for of_platform binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct of_device_id altr_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { .compatible = "altr,softip-i2c-v1.0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_DEVICE_TABLE(of, altr_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct platform_driver altr_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .probe = altr_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .remove = altr_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .name = "altera-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .of_match_table = altr_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) module_platform_driver(altr_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MODULE_DESCRIPTION("Altera Soft IP I2C bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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