^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright (c) 1999 Frodo Looijaard <frodol@dds.nl> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Philip Edelbrock <phil@netroedge.com> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Mark D. Studebaker <mdsxyz123@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) This is the driver for the SMB Host controller on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Acer Labs Inc. (ALI) M1541 and M1543C South Bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) The M1543C is a South bridge for desktop systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) The M1533 is a South bridge for portable systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) They are part of the following ALI chipsets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "Aladdin Pro 2": Includes the M1621 Slot 1 North bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) with AGP and 100MHz CPU Front Side bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "Aladdin V": Includes the M1541 Socket 7 North bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) with AGP and 100MHz CPU Front Side bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "Aladdin IV": Includes the M1541 Socket 7 North bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) with host bus up to 83.3 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) For an overview of these chips see http://www.acerlabs.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) The M1533/M1543C devices appear as FOUR separate devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) on the PCI bus. An output of lspci will show something similar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) to the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 00:02.0 USB Controller: Acer Laboratories Inc. M5237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 00:03.0 Bridge: Acer Laboratories Inc. M7101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 00:07.0 ISA bridge: Acer Laboratories Inc. M1533
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 00:0f.0 IDE interface: Acer Laboratories Inc. M5229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) The SMB controller is part of the 7101 device, which is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ACPI-compliant Power Management Unit (PMU).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) The whole 7101 device has to be enabled for the SMB to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) You can't just enable the SMB alone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) The SMB and the ACPI have separate I/O spaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) We make sure that the SMB is enabled. We leave the ACPI alone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) This driver controls the SMB Host only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) The SMB Slave controller on the M15X3 is not enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) This driver does not use interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Note: we assume there can only be one ALI15X3, with one SMBus interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* ALI15X3 SMBus address offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SMBHSTSTS (0 + ali15x3_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SMBHSTCNT (1 + ali15x3_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SMBHSTSTART (2 + ali15x3_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SMBHSTCMD (7 + ali15x3_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SMBHSTADD (3 + ali15x3_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SMBHSTDAT0 (4 + ali15x3_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SMBHSTDAT1 (5 + ali15x3_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SMBBLKDAT (6 + ali15x3_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* PCI Address Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SMBCOM 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SMBBA 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SMBATPC 0x05B /* used to unlock xxxBA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SMBHSTCFG 0x0E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SMBSLVC 0x0E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SMBCLK 0x0E2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SMBREV 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Other settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MAX_TIMEOUT 200 /* times 1/100 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ALI15X3_SMB_IOSIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* this is what the Award 1004 BIOS sets them to on a ASUS P5A MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) We don't use these here. If the bases aren't set to some value we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) tell user to upgrade BIOS and we fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ALI15X3_SMB_DEFAULTBASE 0xE800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* ALI15X3 address lock bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ALI15X3_LOCK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* ALI15X3 command constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ALI15X3_ABORT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ALI15X3_T_OUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ALI15X3_QUICK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ALI15X3_BYTE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ALI15X3_BYTE_DATA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ALI15X3_WORD_DATA 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ALI15X3_BLOCK_DATA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ALI15X3_BLOCK_CLR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* ALI15X3 status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ALI15X3_STS_IDLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ALI15X3_STS_BUSY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ALI15X3_STS_DONE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ALI15X3_STS_DEV 0x20 /* device error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ALI15X3_STS_COLL 0x40 /* collision or no response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ALI15X3_STS_TERM 0x80 /* terminated by abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ALI15X3_STS_ERR 0xE0 /* all the bad error bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* If force_addr is set to anything different from 0, we forcibly enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) the device at the given address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static u16 force_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) module_param_hw(force_addr, ushort, ioport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MODULE_PARM_DESC(force_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "Initialize the base address of the i2c controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct pci_driver ali15x3_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static unsigned short ali15x3_smba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int ali15x3_setup(struct pci_dev *ALI15X3_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u16 a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned char temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Check the following things:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) - SMB I/O address is initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) - Device is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) - We can use the addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Unlock the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) The data sheet says that the address registers are read-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if the lock bits are 1, but in fact the address registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) are zero unless you clear the lock bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_read_config_byte(ALI15X3_dev, SMBATPC, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (temp & ALI15X3_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) temp &= ~ALI15X3_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pci_write_config_byte(ALI15X3_dev, SMBATPC, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Determine the address of the SMBus area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pci_read_config_word(ALI15X3_dev, SMBBA, &ali15x3_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ali15x3_smba &= (0xffff & ~(ALI15X3_SMB_IOSIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ali15x3_smba == 0 && force_addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(&ALI15X3_dev->dev, "ALI15X3_smb region uninitialized "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "- upgrade BIOS or use force_addr=0xaddr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if(force_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ali15x3_smba = force_addr & ~(ALI15X3_SMB_IOSIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (acpi_check_region(ali15x3_smba, ALI15X3_SMB_IOSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ali15x3_driver.name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!request_region(ali15x3_smba, ALI15X3_SMB_IOSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ali15x3_driver.name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(&ALI15X3_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "ALI15X3_smb region 0x%x already in use!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ali15x3_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if(force_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_info(&ALI15X3_dev->dev, "forcing ISA address 0x%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ali15x3_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (PCIBIOS_SUCCESSFUL != pci_write_config_word(ALI15X3_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SMBBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ali15x3_smba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (PCIBIOS_SUCCESSFUL != pci_read_config_word(ALI15X3_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SMBBA, &a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if ((a & ~(ALI15X3_SMB_IOSIZE - 1)) != ali15x3_smba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* make sure it works */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_err(&ALI15X3_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "force address failed - not supported?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* check if whole device is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pci_read_config_byte(ALI15X3_dev, SMBCOM, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if ((temp & 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_info(&ALI15X3_dev->dev, "enabling SMBus device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pci_write_config_byte(ALI15X3_dev, SMBCOM, temp | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Is SMB Host controller enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pci_read_config_byte(ALI15X3_dev, SMBHSTCFG, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if ((temp & 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_info(&ALI15X3_dev->dev, "enabling SMBus controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pci_write_config_byte(ALI15X3_dev, SMBHSTCFG, temp | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* set SMB clock to 74KHz as recommended in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pci_write_config_byte(ALI15X3_dev, SMBCLK, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) The interrupt routing for SMB is set up in register 0x77 in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 1533 ISA Bridge device, NOT in the 7101 device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) Don't bother with finding the 1533 device and reading the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if ((....... & 0x0F) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_dbg(&ALI15X3_dev->dev, "ALI15X3 using Interrupt 9 for SMBus.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pci_read_config_byte(ALI15X3_dev, SMBREV, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_dbg(&ALI15X3_dev->dev, "SMBREV = 0x%X\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_dbg(&ALI15X3_dev->dev, "iALI15X3_smba = 0x%X\n", ali15x3_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) release_region(ali15x3_smba, ALI15X3_SMB_IOSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Another internally used function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int ali15x3_transaction(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_dbg(&adap->dev, "Transaction (pre): STS=%02x, CNT=%02x, CMD=%02x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTSTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* get status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) temp = inb_p(SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Make sure the SMBus host is ready to start transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Check the busy bit first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (temp & ALI15X3_STS_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) If the host controller is still busy, it may have timed out in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) previous transaction, resulting in a "SMBus Timeout" Dev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) I've tried the following to reset a stuck busy bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 1. Reset the controller with an ABORT command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) (this doesn't seem to clear the controller if an external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) device is hung)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 2. Reset the controller and the other SMBus devices with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) T_OUT command. (this clears the host busy bit if an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) external device is hung, but it comes back upon a new access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) to a device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 3. Disable and reenable the controller in SMBHSTCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) Worst case, nothing seems to work except power reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Abort - reset the host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) Try resetting entire SMB bus, including other devices -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) This may not work either - it clears the BUSY bit but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) then the BUSY bit may come back on when you try and use the chip again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) If that's the case you are stuck.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_info(&adap->dev, "Resetting entire SMB Bus to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "clear busy condition (%02x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) outb_p(ALI15X3_T_OUT, SMBHSTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) temp = inb_p(SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* now check the error bits and the busy bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (temp & (ALI15X3_STS_ERR | ALI15X3_STS_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* do a clear-on-write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) outb_p(0xFF, SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if ((temp = inb_p(SMBHSTSTS)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) (ALI15X3_STS_ERR | ALI15X3_STS_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* this is probably going to be correctable only by a power reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) as one of the bits now appears to be stuck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* This may be a bus or device with electrical problems. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_err(&adap->dev, "SMBus reset failed! (0x%02x) - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "controller or device on bus is probably hung\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* check and clear done bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (temp & ALI15X3_STS_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) outb_p(temp, SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* start the transaction by writing anything to the start register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) outb_p(0xFF, SMBHSTSTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* We will always wait for a fraction of a second! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) temp = inb_p(SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) } while ((!(temp & (ALI15X3_STS_ERR | ALI15X3_STS_DONE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) && (timeout++ < MAX_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* If the SMBus is still busy, we give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (timeout > MAX_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(&adap->dev, "SMBus Timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (temp & ALI15X3_STS_TERM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_dbg(&adap->dev, "Error: Failed bus transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) Unfortunately the ALI SMB controller maps "no response" and "bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) collision" into a single bit. No response is the usual case so don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) do a printk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) This means that bus collisions go unreported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (temp & ALI15X3_STS_COLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) result = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "Error: no response or bus collision ADD=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) inb_p(SMBHSTADD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* haven't ever seen this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (temp & ALI15X3_STS_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(&adap->dev, "Error: device error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(&adap->dev, "Transaction (post): STS=%02x, CNT=%02x, CMD=%02x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTSTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Return negative errno on error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static s32 ali15x3_access(struct i2c_adapter * adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned short flags, char read_write, u8 command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int size, union i2c_smbus_data * data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* clear all the bits (clear-on-write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) outb_p(0xFF, SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* make sure SMBus is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) temp = inb_p(SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for (timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (timeout < MAX_TIMEOUT) && !(temp & ALI15X3_STS_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) timeout++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) temp = inb_p(SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (timeout >= MAX_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(&adap->dev, "Idle wait Timeout! STS=0x%02x\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) size = ALI15X3_QUICK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) outb_p(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) size = ALI15X3_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) outb_p(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) outb_p(data->byte, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) size = ALI15X3_BYTE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) outb_p(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) outb_p(data->word & 0xff, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) size = ALI15X3_WORD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) outb_p(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (len < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) data->block[0] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (len > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) len = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) data->block[0] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) outb_p(len, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Reset SMBBLKDAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) outb_p(inb_p(SMBHSTCNT) | ALI15X3_BLOCK_CLR, SMBHSTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) for (i = 1; i <= len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) outb_p(data->block[i], SMBBLKDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) size = ALI15X3_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) outb_p(size, SMBHSTCNT); /* output command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) temp = ali15x3_transaction(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if ((read_write == I2C_SMBUS_WRITE) || (size == ALI15X3_QUICK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case ALI15X3_BYTE: /* Result put in SMBHSTDAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) data->byte = inb_p(SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case ALI15X3_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) data->byte = inb_p(SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case ALI15X3_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case ALI15X3_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) len = inb_p(SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (len > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) len = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) data->block[0] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Reset SMBBLKDAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) outb_p(inb_p(SMBHSTCNT) | ALI15X3_BLOCK_CLR, SMBHSTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) for (i = 1; i <= data->block[0]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) data->block[i] = inb_p(SMBBLKDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_dbg(&adap->dev, "Blk: len=%d, i=%d, data=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) len, i, data->block[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static u32 ali15x3_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) I2C_FUNC_SMBUS_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .smbus_xfer = ali15x3_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .functionality = ali15x3_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct i2c_adapter ali15x3_adapter = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .algo = &smbus_algorithm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct pci_device_id ali15x3_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MODULE_DEVICE_TABLE (pci, ali15x3_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int ali15x3_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ali15x3_setup(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "ALI15X3 not detected, module not inserted.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* set up the sysfs linkage to our parent device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ali15x3_adapter.dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) snprintf(ali15x3_adapter.name, sizeof(ali15x3_adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "SMBus ALI15X3 adapter at %04x", ali15x3_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return i2c_add_adapter(&ali15x3_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void ali15x3_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) i2c_del_adapter(&ali15x3_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) release_region(ali15x3_smba, ALI15X3_SMB_IOSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static struct pci_driver ali15x3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .name = "ali15x3_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .id_table = ali15x3_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .probe = ali15x3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .remove = ali15x3_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) module_pci_driver(ali15x3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODULE_AUTHOR("Philip Edelbrock <phil@netroedge.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MODULE_DESCRIPTION("ALI15X3 SMBus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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