Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) /* i2c-pcf8584.h: PCF 8584 global defines				*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /* -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /*   Copyright (C) 1996 Simon G. Vogl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)                    1999 Hans Berglund
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* --------------------------------------------------------------------	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* With some changes from Frodo Looijaard <frodol@dds.nl> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef I2C_PCF8584_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define I2C_PCF8584_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* ----- Control register bits ----------------------------------------	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define I2C_PCF_PIN	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define I2C_PCF_ESO	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define I2C_PCF_ES1	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define I2C_PCF_ES2	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2C_PCF_ENI	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I2C_PCF_STA	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2C_PCF_STO	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I2C_PCF_ACK	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2C_PCF_START    (I2C_PCF_PIN | I2C_PCF_ESO | I2C_PCF_STA | I2C_PCF_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2C_PCF_STOP     (I2C_PCF_PIN | I2C_PCF_ESO | I2C_PCF_STO | I2C_PCF_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_PCF_REPSTART (              I2C_PCF_ESO | I2C_PCF_STA | I2C_PCF_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C_PCF_IDLE     (I2C_PCF_PIN | I2C_PCF_ESO               | I2C_PCF_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* ----- Status register bits -----------------------------------------	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*#define I2C_PCF_PIN  0x80    as above*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2C_PCF_INI 0x40   /* 1 if not initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_PCF_STS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2C_PCF_BER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_PCF_AD0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_PCF_LRB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_PCF_AAS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_PCF_LAB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2C_PCF_BB  0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* ----- Chip clock frequencies ---------------------------------------	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_PCF_CLK3	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_PCF_CLK443	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_PCF_CLK6	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_PCF_CLK	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_PCF_CLK12	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* ----- transmission frequencies -------------------------------------	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2C_PCF_TRNS90 0x00	/*  90 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2C_PCF_TRNS45 0x01	/*  45 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2C_PCF_TRNS11 0x02	/*  11 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2C_PCF_TRNS15 0x03	/* 1.5 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* ----- Access to internal registers according to ES1,ES2 ------------	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* they are mapped to the data port ( a0 = 0 ) 				*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* available when ESO == 0 :						*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_PCF_OWNADR	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C_PCF_INTREG	I2C_PCF_ES2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2C_PCF_CLKREG	I2C_PCF_ES1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* I2C_PCF8584_H */