^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i2c-algo-pca.c i2c driver algorithms for PCA9564 adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004 Arcom Control Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c-algo-pca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DEB1(fmt, args...) do { if (i2c_debug >= 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) printk(KERN_DEBUG fmt, ## args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DEB2(fmt, args...) do { if (i2c_debug >= 2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) printk(KERN_DEBUG fmt, ## args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DEB3(fmt, args...) do { if (i2c_debug >= 3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) printk(KERN_DEBUG fmt, ## args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int i2c_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define pca_outw(adap, reg, val) adap->write_byte(adap->data, reg, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define pca_inw(adap, reg) adap->read_byte(adap->data, reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define pca_status(adap) pca_inw(adap, I2C_PCA_STA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define pca_clock(adap) adap->i2c_clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define pca_set_con(adap, val) pca_outw(adap, I2C_PCA_CON, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define pca_get_con(adap) pca_inw(adap, I2C_PCA_CON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define pca_wait(adap) adap->wait_for_completion(adap->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void pca_reset(struct i2c_algo_pca_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (adap->chip == I2C_PCA_CHIP_9665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Ignore the reset function from the module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * we can use the parallel bus reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pca_outw(adap, I2C_PCA_INDPTR, I2C_PCA_IPRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pca_outw(adap, I2C_PCA_IND, 0xA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pca_outw(adap, I2C_PCA_IND, 0x5A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * After a reset we need to re-apply any configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * (calculated in pca_init) to get the bus in a working state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pca_outw(adap, I2C_PCA_INDPTR, I2C_PCA_IMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) pca_outw(adap, I2C_PCA_IND, adap->bus_settings.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pca_outw(adap, I2C_PCA_INDPTR, I2C_PCA_ISCLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pca_outw(adap, I2C_PCA_IND, adap->bus_settings.tlow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pca_outw(adap, I2C_PCA_INDPTR, I2C_PCA_ISCLH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pca_outw(adap, I2C_PCA_IND, adap->bus_settings.thi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pca_set_con(adap, I2C_PCA_CON_ENSIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) adap->reset_chip(adap->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pca_set_con(adap, I2C_PCA_CON_ENSIO | adap->bus_settings.clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Generate a start condition on the i2c bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * returns after the start condition has occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int pca_start(struct i2c_algo_pca_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int sta = pca_get_con(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DEB2("=== START\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) sta |= I2C_PCA_CON_STA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pca_set_con(adap, sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return pca_wait(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Generate a repeated start condition on the i2c bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * return after the repeated start condition has occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int pca_repeated_start(struct i2c_algo_pca_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int sta = pca_get_con(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEB2("=== REPEATED START\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sta |= I2C_PCA_CON_STA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pca_set_con(adap, sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return pca_wait(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Generate a stop condition on the i2c bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * returns after the stop condition has been generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * STOPs do not generate an interrupt or set the SI flag, since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * part returns the idle state (0xf8). Hence we don't need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * pca_wait here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void pca_stop(struct i2c_algo_pca_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int sta = pca_get_con(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEB2("=== STOP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) sta |= I2C_PCA_CON_STO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sta &= ~(I2C_PCA_CON_STA|I2C_PCA_CON_SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pca_set_con(adap, sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Send the slave address and R/W bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * returns after the address has been sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int pca_address(struct i2c_algo_pca_data *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int sta = pca_get_con(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEB2("=== SLAVE ADDRESS %#04x+%c=%#04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) msg->addr, msg->flags & I2C_M_RD ? 'R' : 'W', addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pca_outw(adap, I2C_PCA_DAT, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_STA|I2C_PCA_CON_SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pca_set_con(adap, sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return pca_wait(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Transmit a byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Returns after the byte has been transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int pca_tx_byte(struct i2c_algo_pca_data *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __u8 b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int sta = pca_get_con(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEB2("=== WRITE %#04x\n", b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pca_outw(adap, I2C_PCA_DAT, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_STA|I2C_PCA_CON_SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pca_set_con(adap, sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return pca_wait(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Receive a byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * returns immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void pca_rx_byte(struct i2c_algo_pca_data *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) __u8 *b, int ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *b = pca_inw(adap, I2C_PCA_DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEB2("=== READ %#04x %s\n", *b, ack ? "ACK" : "NACK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Setup ACK or NACK for next received byte and wait for it to arrive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Returns after next byte has arrived.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int pca_rx_ack(struct i2c_algo_pca_data *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int sta = pca_get_con(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_STA|I2C_PCA_CON_SI|I2C_PCA_CON_AA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sta |= I2C_PCA_CON_AA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pca_set_con(adap, sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return pca_wait(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int pca_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct i2c_algo_pca_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct i2c_msg *msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int curmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int numbytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int completed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long timeout = jiffies + i2c_adap->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) while ((state = pca_status(adap)) != 0xf8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_dbg(&i2c_adap->dev, "bus is not idle. status is "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "%#04x\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DEB1("{{{ XFER %d messages\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (i2c_debug >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (curmsg = 0; curmsg < num; curmsg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int addr, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) msg = &msgs[curmsg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) addr = (0x7f & msg->addr) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) printk(KERN_INFO " [%02d] RD %d bytes from %#02x [%#02x, ...]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) curmsg, msg->len, addr, (addr << 1) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) printk(KERN_INFO " [%02d] WR %d bytes to %#02x [%#02x%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) curmsg, msg->len, addr, addr << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) msg->len == 0 ? "" : ", ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (i = 0; i < msg->len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) printk("%#04x%s", msg->buf[i], i == msg->len - 1 ? "" : ", ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) curmsg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) while (curmsg < num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) state = pca_status(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) DEB3("STATE is 0x%02x\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) msg = &msgs[curmsg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case 0xf8: /* On reset or stop the bus is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) completed = pca_start(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case 0x08: /* A START condition has been transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case 0x10: /* A repeated start condition has been transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) completed = pca_address(adap, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case 0x18: /* SLA+W has been transmitted; ACK has been received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 0x28: /* Data byte in I2CDAT has been transmitted; ACK has been received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (numbytes < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) completed = pca_tx_byte(adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) msg->buf[numbytes]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) numbytes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) curmsg++; numbytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (curmsg == num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pca_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) completed = pca_repeated_start(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case 0x20: /* SLA+W has been transmitted; NOT ACK has been received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DEB2("NOT ACK received after SLA+W\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pca_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case 0x40: /* SLA+R has been transmitted; ACK has been received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) completed = pca_rx_ack(adap, msg->len > 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case 0x50: /* Data bytes has been received; ACK has been returned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (numbytes < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pca_rx_byte(adap, &msg->buf[numbytes], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) numbytes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) completed = pca_rx_ack(adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) numbytes < msg->len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) curmsg++; numbytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (curmsg == num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pca_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) completed = pca_repeated_start(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case 0x48: /* SLA+R has been transmitted; NOT ACK has been received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DEB2("NOT ACK received after SLA+R\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pca_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case 0x30: /* Data byte in I2CDAT has been transmitted; NOT ACK has been received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DEB2("NOT ACK received after data byte\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pca_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case 0x38: /* Arbitration lost during SLA+W, SLA+R or data bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DEB2("Arbitration lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * The PCA9564 data sheet (2006-09-01) says "A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * START condition will be transmitted when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * bus becomes free (STOP or SCL and SDA high)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * when the STA bit is set (p. 11).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * In case this won't work, try pca_reset()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pca_start(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case 0x58: /* Data byte has been received; NOT ACK has been returned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (numbytes == msg->len - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pca_rx_byte(adap, &msg->buf[numbytes], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) curmsg++; numbytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (curmsg == num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pca_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) completed = pca_repeated_start(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DEB2("NOT ACK sent after data byte received. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "Not final byte. numbytes %d. len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) numbytes, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pca_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case 0x70: /* Bus error - SDA stuck low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DEB2("BUS ERROR - SDA Stuck low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pca_reset(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case 0x78: /* Bus error - SCL stuck low (PCA9665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case 0x90: /* Bus error - SCL stuck low (PCA9564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) DEB2("BUS ERROR - SCL Stuck low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pca_reset(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case 0x00: /* Bus error during master or slave mode due to illegal START or STOP condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) DEB2("BUS ERROR - Illegal START or STOP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pca_reset(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(&i2c_adap->dev, "unhandled SIO state 0x%02x\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!completed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = curmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DEB1("}}} transferred %d/%d messages. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "status is %#04x. control is %#04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) curmsg, num, pca_status(adap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pca_get_con(adap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static u32 pca_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct i2c_algorithm pca_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .master_xfer = pca_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .functionality = pca_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static unsigned int pca_probe_chip(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct i2c_algo_pca_data *pca_data = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* The trick here is to check if there is an indirect register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * available. If there is one, we will read the value we first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * wrote on I2C_PCA_IADR. Otherwise, we will read the last value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * we wrote on I2C_PCA_ADR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pca_outw(pca_data, I2C_PCA_INDPTR, I2C_PCA_IADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pca_outw(pca_data, I2C_PCA_IND, 0xAA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pca_outw(pca_data, I2C_PCA_INDPTR, I2C_PCA_ITO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pca_outw(pca_data, I2C_PCA_IND, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pca_outw(pca_data, I2C_PCA_INDPTR, I2C_PCA_IADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (pca_inw(pca_data, I2C_PCA_IND) == 0xAA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) printk(KERN_INFO "%s: PCA9665 detected.\n", adap->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pca_data->chip = I2C_PCA_CHIP_9665;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) printk(KERN_INFO "%s: PCA9564 detected.\n", adap->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pca_data->chip = I2C_PCA_CHIP_9564;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return pca_data->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int pca_init(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct i2c_algo_pca_data *pca_data = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) adap->algo = &pca_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (pca_probe_chip(adap) == I2C_PCA_CHIP_9564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int freqs[] = {330, 288, 217, 146, 88, 59, 44, 36};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (pca_data->i2c_clock > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) switch (pca_data->i2c_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case 330000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pca_data->i2c_clock = I2C_PCA_CON_330kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case 288000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pca_data->i2c_clock = I2C_PCA_CON_288kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case 217000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pca_data->i2c_clock = I2C_PCA_CON_217kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case 146000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pca_data->i2c_clock = I2C_PCA_CON_146kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case 88000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pca_data->i2c_clock = I2C_PCA_CON_88kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case 59000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pca_data->i2c_clock = I2C_PCA_CON_59kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case 44000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pca_data->i2c_clock = I2C_PCA_CON_44kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case 36000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pca_data->i2c_clock = I2C_PCA_CON_36kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "%s: Invalid I2C clock speed selected."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) " Using default 59kHz.\n", adap->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pca_data->i2c_clock = I2C_PCA_CON_59kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) printk(KERN_WARNING "%s: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "Choosing the clock frequency based on "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "index is deprecated."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) " Use the nominal frequency.\n", adap->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) clock = pca_clock(pca_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) printk(KERN_INFO "%s: Clock frequency is %dkHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) adap->name, freqs[clock]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Store settings as these will be needed when the PCA chip is reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pca_data->bus_settings.clock_freq = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pca_reset(pca_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int tlow, thi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Values can be found on PCA9665 datasheet section 7.3.2.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int min_tlow, min_thi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* These values are the maximum raise and fall values allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * by the I2C operation mode (Standard, Fast or Fast+)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * They are used (added) below to calculate the clock dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * of PCA9665. Note that they are slightly different of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * real maximum, to allow the change on mode exactly on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * maximum clock rate for each mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int raise_fall_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (pca_data->i2c_clock > 1265800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) printk(KERN_WARNING "%s: I2C clock speed too high."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) " Using 1265.8kHz.\n", adap->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pca_data->i2c_clock = 1265800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (pca_data->i2c_clock < 60300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) printk(KERN_WARNING "%s: I2C clock speed too low."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) " Using 60.3kHz.\n", adap->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pca_data->i2c_clock = 60300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* To avoid integer overflow, use clock/100 for calculations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) clock = pca_clock(pca_data) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (pca_data->i2c_clock > I2C_MAX_FAST_MODE_PLUS_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mode = I2C_PCA_MODE_TURBO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) min_tlow = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) min_thi = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) raise_fall_time = 22; /* Raise 11e-8s, Fall 11e-8s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) } else if (pca_data->i2c_clock > I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mode = I2C_PCA_MODE_FASTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) min_tlow = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) min_thi = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) raise_fall_time = 22; /* Raise 11e-8s, Fall 11e-8s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } else if (pca_data->i2c_clock > I2C_MAX_STANDARD_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mode = I2C_PCA_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) min_tlow = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) min_thi = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) raise_fall_time = 58; /* Raise 29e-8s, Fall 29e-8s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mode = I2C_PCA_MODE_STD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) min_tlow = 157;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) min_thi = 134;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) raise_fall_time = 127; /* Raise 29e-8s, Fall 98e-8s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* The minimum clock that respects the thi/tlow = 134/157 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * 64800 Hz. Below that, we have to fix the tlow to 255 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * calculate the thi factor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (clock < 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) tlow = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) thi = 1000000 - clock * raise_fall_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) thi /= (I2C_PCA_OSC_PER * clock) - tlow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) tlow = (1000000 - clock * raise_fall_time) * min_tlow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) tlow /= I2C_PCA_OSC_PER * clock * (min_thi + min_tlow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) thi = tlow * min_thi / min_tlow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Store settings as these will be needed when the PCA chip is reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pca_data->bus_settings.mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pca_data->bus_settings.tlow = tlow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pca_data->bus_settings.thi = thi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pca_reset(pca_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "%s: Clock frequency is %dHz\n", adap->name, clock * 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) udelay(500); /* 500 us for oscillator to stabilise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * registering functions to load algorithms at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int i2c_pca_add_bus(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rval = pca_init(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) EXPORT_SYMBOL(i2c_pca_add_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int i2c_pca_add_numbered_bus(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) rval = pca_init(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) EXPORT_SYMBOL(i2c_pca_add_numbered_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MODULE_AUTHOR("Ian Campbell <icampbell@arcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MODULE_DESCRIPTION("I2C-Bus PCA9564/PCA9665 algorithm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) module_param(i2c_debug, int, 0);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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