^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i2c-algo-bit.c: i2c driver algorithms for bit-shift adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995-2000 Simon G. Vogl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * With some changes from Frodo Looijaard <frodol@dds.nl>, Kyösti Mälkki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * <kmalkki@cc.hut.fi> and Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c-algo-bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* ----- global defines ----------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define bit_dbg(level, dev, format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (i2c_debug >= level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) dev_dbg(dev, format, ##args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define bit_dbg(level, dev, format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif /* DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* ----- global variables --------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int bit_test; /* see if the line-setting functions work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) module_param(bit_test, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MODULE_PARM_DESC(bit_test, "lines testing - 0 off; 1 report; 2 fail if stuck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int i2c_debug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) module_param(i2c_debug, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_PARM_DESC(i2c_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "debug level - 0 off; 1 normal; 2 verbose; 3 very verbose");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* --- setting states on the bus with the right timing: --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define setsda(adap, val) adap->setsda(adap->data, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define setscl(adap, val) adap->setscl(adap->data, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define getsda(adap) adap->getsda(adap->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define getscl(adap) adap->getscl(adap->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline void sdalo(struct i2c_algo_bit_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) setsda(adap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) udelay((adap->udelay + 1) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline void sdahi(struct i2c_algo_bit_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) setsda(adap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) udelay((adap->udelay + 1) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline void scllo(struct i2c_algo_bit_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) setscl(adap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) udelay(adap->udelay / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Raise scl line, and do checking for delays. This is necessary for slower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int sclhi(struct i2c_algo_bit_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) setscl(adap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Not all adapters have scl sense line... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!adap->getscl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) while (!getscl(adap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* This hw knows how to read the clock line, so we wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * until it actually gets high. This is safer as some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * chips may hold it low ("clock stretching") while they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * are processing data internally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (time_after(jiffies, start + adap->timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Test one last time, as we may have been preempted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * between last check and timeout test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (getscl(adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (jiffies != start && i2c_debug >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pr_debug("i2c-algo-bit: needed %ld jiffies for SCL to go high\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) jiffies - start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) udelay(adap->udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* --- other auxiliary functions -------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void i2c_start(struct i2c_algo_bit_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* assert: scl, sda are high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) setsda(adap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) udelay(adap->udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) scllo(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void i2c_repstart(struct i2c_algo_bit_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* assert: scl is low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) sdahi(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sclhi(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) setsda(adap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) udelay(adap->udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) scllo(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void i2c_stop(struct i2c_algo_bit_data *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* assert: scl is low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) sdalo(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) sclhi(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) setsda(adap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) udelay(adap->udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* send a byte without start cond., look for arbitration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) check ackn. from slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * 1 if the device acknowledged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * 0 if the device did not ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * -ETIMEDOUT if an error occurred (while raising the scl line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int i2c_outb(struct i2c_adapter *i2c_adap, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* assert: scl is low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (i = 7; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) sb = (c >> i) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) setsda(adap, sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) udelay((adap->udelay + 1) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (sclhi(adap) < 0) { /* timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bit_dbg(1, &i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "i2c_outb: 0x%02x, timeout at bit #%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) (int)c, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* FIXME do arbitration here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * if (sb && !getsda(adap)) -> ouch! Get out of here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Report a unique code, so higher level code can retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * the whole (combined) message and *NOT* issue STOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) scllo(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sdahi(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (sclhi(adap) < 0) { /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bit_dbg(1, &i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "i2c_outb: 0x%02x, timeout at ack\n", (int)c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* read ack: SDA should be pulled down by slave, or it may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * NAK (usually to report problems with the data we wrote).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ack = !getsda(adap); /* ack: sda is pulled low -> success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bit_dbg(2, &i2c_adap->dev, "i2c_outb: 0x%02x %s\n", (int)c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ack ? "A" : "NA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) scllo(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* assert: scl is low (sda undef) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int i2c_inb(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* read byte via i2c port, without start/stop sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* acknowledge is sent in i2c_read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned char indata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* assert: scl is low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sdahi(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (sclhi(adap) < 0) { /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bit_dbg(1, &i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "i2c_inb: timeout at bit #%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 7 - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) indata *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (getsda(adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) indata |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) setscl(adap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) udelay(i == 7 ? adap->udelay / 2 : adap->udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* assert: scl is low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return indata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Sanity check for the adapter hardware - check the reaction of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * the bus lines only if it seems to be idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int test_bus(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const char *name = i2c_adap->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int scl, sda, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (adap->pre_xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = adap->pre_xfer(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (adap->getscl == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pr_info("%s: Testing SDA only, SCL is not readable\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) sda = getsda(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) scl = (adap->getscl == NULL) ? 1 : getscl(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!scl || !sda) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "%s: bus seems to be busy (scl=%d, sda=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) name, scl, sda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sdalo(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) sda = getsda(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) scl = (adap->getscl == NULL) ? 1 : getscl(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (sda) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) printk(KERN_WARNING "%s: SDA stuck high!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!scl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "%s: SCL unexpected low while pulling SDA low!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) sdahi(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sda = getsda(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) scl = (adap->getscl == NULL) ? 1 : getscl(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!sda) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) printk(KERN_WARNING "%s: SDA stuck low!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!scl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "%s: SCL unexpected low while pulling SDA high!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) scllo(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) sda = getsda(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) scl = (adap->getscl == NULL) ? 0 : getscl(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (scl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) printk(KERN_WARNING "%s: SCL stuck high!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!sda) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "%s: SDA unexpected low while pulling SCL low!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) sclhi(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sda = getsda(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) scl = (adap->getscl == NULL) ? 1 : getscl(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!scl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) printk(KERN_WARNING "%s: SCL stuck low!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!sda) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "%s: SDA unexpected low while pulling SCL high!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (adap->post_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) adap->post_xfer(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pr_info("%s: Test OK\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) bailout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) sdahi(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) sclhi(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (adap->post_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) adap->post_xfer(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* ----- Utility functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* try_address tries to contact a chip for a number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * times before it gives up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * return values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * 1 chip answered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * 0 chip did not answer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * -x transmission error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int try_address(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned char addr, int retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) for (i = 0; i <= retries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = i2c_outb(i2c_adap, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret == 1 || i == retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bit_dbg(3, &i2c_adap->dev, "emitting stop condition\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) i2c_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) udelay(adap->udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) yield();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bit_dbg(3, &i2c_adap->dev, "emitting start condition\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) i2c_start(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (i && ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) bit_dbg(1, &i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "Used %d tries to %s client at 0x%02x: %s\n", i + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) addr & 1 ? "read from" : "write to", addr >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ret == 1 ? "success" : "failed, timeout?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int sendbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) const unsigned char *temp = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int count = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int wrcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) while (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) retval = i2c_outb(i2c_adap, *temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* OK/ACK; or ignored NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if ((retval > 0) || (nak_ok && (retval == 0))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) temp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) wrcount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* A slave NAKing the master means the slave didn't like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * something about the data it saw. For example, maybe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * the SMBus PEC was wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } else if (retval == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(&i2c_adap->dev, "sendbytes: NAK bailout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Timeout; or (someday) lost arbitration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * FIXME Lost ARB implies retrying the transaction from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * the first message, after the "winning" master issues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * its STOP. As a rule, upper layer code has no reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * to know or care about this ... it is *NOT* an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(&i2c_adap->dev, "sendbytes: error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return wrcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int acknak(struct i2c_adapter *i2c_adap, int is_ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* assert: sda is high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (is_ack) /* send ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) setsda(adap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) udelay((adap->udelay + 1) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (sclhi(adap) < 0) { /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(&i2c_adap->dev, "readbytes: ack/nak timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) scllo(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int inval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int rdcount = 0; /* counts bytes read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned char *temp = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int count = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) const unsigned flags = msg->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) while (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) inval = i2c_inb(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (inval >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *temp = inval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rdcount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } else { /* read timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) temp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Some SMBus transactions require that we receive the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) transaction length as the first read byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (rdcount == 1 && (flags & I2C_M_RECV_LEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (inval <= 0 || inval > I2C_SMBUS_BLOCK_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!(flags & I2C_M_NO_RD_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) acknak(i2c_adap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(&i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "readbytes: invalid block length (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) inval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* The original count value accounts for the extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) bytes, that is, either 1 for a regular transaction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) or 2 for a PEC transaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) count += inval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) msg->len += inval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) bit_dbg(2, &i2c_adap->dev, "readbytes: 0x%02x %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) inval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) (flags & I2C_M_NO_RD_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ? "(no ack/nak)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) : (count ? "A" : "NA"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!(flags & I2C_M_NO_RD_ACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) inval = acknak(i2c_adap, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (inval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return inval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return rdcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* doAddress initiates the transfer by generating the start condition (in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * try_address) and transmits the address in the necessary format to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * reads, writes as well as 10bit-addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * 0 everything went okay, the chip ack'ed, or IGNORE_NAK flag was set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * -x an error occurred (like: -ENXIO if the device did not answer, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * -ETIMEDOUT, for example if the lines are stuck...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int bit_doAddress(struct i2c_adapter *i2c_adap, struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned short flags = msg->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int ret, retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) retries = nak_ok ? 0 : i2c_adap->retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* a ten bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) addr = 0xf0 | ((msg->addr >> 7) & 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) bit_dbg(2, &i2c_adap->dev, "addr0: %d\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* try extended address code...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = try_address(i2c_adap, addr, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if ((ret != 1) && !nak_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(&i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "died at extended address code\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* the remaining 8 bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = i2c_outb(i2c_adap, msg->addr & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if ((ret != 1) && !nak_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* the chip did not ack / xmission error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_err(&i2c_adap->dev, "died at 2nd address code\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bit_dbg(3, &i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "emitting repeated start condition\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) i2c_repstart(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* okay, now switch into reading mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) addr |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = try_address(i2c_adap, addr, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if ((ret != 1) && !nak_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(&i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "died at repeated address code\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) } else { /* normal 7bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (flags & I2C_M_REV_DIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) addr ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = try_address(i2c_adap, addr, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if ((ret != 1) && !nak_ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int bit_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct i2c_msg *pmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned short nak_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (adap->pre_xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = adap->pre_xfer(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) bit_dbg(3, &i2c_adap->dev, "emitting start condition\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) i2c_start(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pmsg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) nak_ok = pmsg->flags & I2C_M_IGNORE_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!(pmsg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (msgs[i - 1].flags & I2C_M_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) bit_dbg(3, &i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "emitting enforced stop/start condition\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) i2c_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) i2c_start(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bit_dbg(3, &i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "emitting repeated start condition\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) i2c_repstart(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = bit_doAddress(i2c_adap, pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if ((ret != 0) && !nak_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) bit_dbg(1, &i2c_adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "NAK from device addr 0x%02x msg #%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) msgs[i].addr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (pmsg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* read bytes into buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = readbytes(i2c_adap, pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) bit_dbg(2, &i2c_adap->dev, "read %d byte%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret, ret == 1 ? "" : "s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret < pmsg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* write bytes from buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = sendbytes(i2c_adap, pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) bit_dbg(2, &i2c_adap->dev, "wrote %d byte%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret, ret == 1 ? "" : "s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret < pmsg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) bailout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) bit_dbg(3, &i2c_adap->dev, "emitting stop condition\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) i2c_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (adap->post_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) adap->post_xfer(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * We print a warning when we are not flagged to support atomic transfers but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * will try anyhow. That's what the I2C core would do as well. Sadly, we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * modify the algorithm struct at probe time because this struct is exported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * 'const'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int bit_xfer_atomic(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (!adap->can_do_atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_warn(&i2c_adap->dev, "not flagged for atomic transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return bit_xfer(i2c_adap, msgs, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static u32 bit_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return I2C_FUNC_I2C | I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_EMUL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) I2C_FUNC_SMBUS_READ_BLOCK_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* -----exported algorithm data: ------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) const struct i2c_algorithm i2c_bit_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .master_xfer = bit_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .master_xfer_atomic = bit_xfer_atomic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .functionality = bit_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) EXPORT_SYMBOL(i2c_bit_algo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const struct i2c_adapter_quirks i2c_bit_quirk_no_clk_stretch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .flags = I2C_AQ_NO_CLK_STRETCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * registering functions to load algorithms at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int __i2c_bit_add_bus(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int (*add_adapter)(struct i2c_adapter *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct i2c_algo_bit_data *bit_adap = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (bit_test) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = test_bus(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (bit_test >= 2 && ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* register new adapter to i2c module... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) adap->algo = &i2c_bit_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) adap->retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (bit_adap->getscl == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) adap->quirks = &i2c_bit_quirk_no_clk_stretch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * We tried forcing SCL/SDA to an initial state here. But that caused a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * regression, sadly. Check Bugzilla #200045 for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* Complain if SCL can't be read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (bit_adap->getscl == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_warn(&adap->dev, "Not I2C compliant: can't read SCL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_warn(&adap->dev, "Bus may be unreliable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int i2c_bit_add_bus(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return __i2c_bit_add_bus(adap, i2c_add_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) EXPORT_SYMBOL(i2c_bit_add_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int i2c_bit_add_numbered_bus(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return __i2c_bit_add_bus(adap, i2c_add_numbered_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) EXPORT_SYMBOL(i2c_bit_add_numbered_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MODULE_AUTHOR("Simon G. Vogl <simon@tk.uni-linz.ac.at>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MODULE_DESCRIPTION("I2C-Bus bit-banging algorithm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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