Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Intel(R) Trace Hub pci driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014-2015 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "intel_th.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DRIVER_NAME "intel_th_pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	TH_PCI_CONFIG_BAR	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	TH_PCI_STH_SW_BAR	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	TH_PCI_RTIT_BAR		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define BAR_MASK (BIT(TH_PCI_CONFIG_BAR) | BIT(TH_PCI_STH_SW_BAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PCI_REG_NPKDSC	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define NPKDSC_TSACT	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static int intel_th_pci_activate(struct intel_th *th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct pci_dev *pdev = to_pci_dev(th->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 npkdsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	if (!INTEL_TH_CAP(th, tscu_enable))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		npkdsc |= NPKDSC_TSACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		dev_err(&pdev->dev, "failed to read NPKDSC register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void intel_th_pci_deactivate(struct intel_th *th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct pci_dev *pdev = to_pci_dev(th->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u32 npkdsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (!INTEL_TH_CAP(th, tscu_enable))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		npkdsc |= NPKDSC_TSACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		dev_err(&pdev->dev, "failed to read NPKDSC register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static int intel_th_pci_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			      const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct intel_th_drvdata *drvdata = (void *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct resource resource[TH_MMIO_END + TH_NVEC_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		[TH_MMIO_CONFIG]	= pdev->resource[TH_PCI_CONFIG_BAR],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		[TH_MMIO_SW]		= pdev->resource[TH_PCI_STH_SW_BAR],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int err, r = TH_MMIO_SW + 1, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct intel_th *th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	err = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	err = pcim_iomap_regions_request_all(pdev, BAR_MASK, DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (pdev->resource[TH_PCI_RTIT_BAR].start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		resource[TH_MMIO_RTIT] = pdev->resource[TH_PCI_RTIT_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		r++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	err = pci_alloc_irq_vectors(pdev, 1, 8, PCI_IRQ_ALL_TYPES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (err > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		for (i = 0; i < err; i++, r++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			resource[r].flags = IORESOURCE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			resource[r].start = pci_irq_vector(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	th = intel_th_alloc(&pdev->dev, drvdata, resource, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (IS_ERR(th))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return PTR_ERR(th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	th->activate   = intel_th_pci_activate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	th->deactivate = intel_th_pci_deactivate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void intel_th_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct intel_th *th = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	intel_th_free(th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct intel_th_drvdata intel_th_1x_multi_is_broken = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.multi_is_broken	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct intel_th_drvdata intel_th_2x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.tscu_enable	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.has_mintctl	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct pci_device_id intel_th_pci_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9d26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.driver_data = (kernel_ulong_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa126),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.driver_data = (kernel_ulong_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		/* Apollo Lake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x5a8e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.driver_data = (kernel_ulong_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		/* Broxton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0a80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.driver_data = (kernel_ulong_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/* Broxton B-step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1a8e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.driver_data = (kernel_ulong_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		/* Kaby Lake PCH-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa2a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.driver_data = (kernel_ulong_t)&intel_th_1x_multi_is_broken,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		/* Denverton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x19e1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.driver_data = (kernel_ulong_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		/* Lewisburg PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa1a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.driver_data = (kernel_ulong_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		/* Lewisburg PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa226),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.driver_data = (kernel_ulong_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		/* Gemini Lake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x318e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		/* Cannon Lake H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa326),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		/* Cannon Lake LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9da6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/* Cedar Fork PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x18e1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		/* Ice Lake PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x34a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		/* Comet Lake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x02a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		/* Comet Lake PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x06a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		/* Comet Lake PCH-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa3a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.driver_data = (kernel_ulong_t)&intel_th_1x_multi_is_broken,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		/* Ice Lake NNPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x45c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		/* Ice Lake CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8a29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		/* Tiger Lake CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9a33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		/* Tiger Lake PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa0a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		/* Tiger Lake PCH-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x43a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		/* Jasper Lake PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4da6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		/* Jasper Lake CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4e29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		/* Elkhart Lake CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4529),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		/* Elkhart Lake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4b26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		/* Emmitsburg PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1bcc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		/* Alder Lake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7aa6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		/* Alder Lake-P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x51a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		/* Alder Lake-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x54a6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		/* Alder Lake CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x466f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		/* Rocket Lake CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.driver_data = (kernel_ulong_t)&intel_th_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_DEVICE_TABLE(pci, intel_th_pci_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct pci_driver intel_th_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.name		= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.id_table	= intel_th_pci_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.probe		= intel_th_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.remove		= intel_th_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) module_pci_driver(intel_th_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MODULE_DESCRIPTION("Intel(R) Trace Hub PCI controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_AUTHOR("Alexander Shishkin <alexander.shishkin@intel.com>");