^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel(R) Trace Hub Memory Storage Unit (MSU) data structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2015 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __INTEL_TH_MSU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __INTEL_TH_MSU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) REG_MSU_MSUPARAMS = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) REG_MSU_MSUSTS = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) REG_MSU_MINTCTL = 0x0004, /* MSU-global interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) REG_MSU_MSC0CTL = 0x0100, /* MSC0 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) REG_MSU_MSC0STS = 0x0104, /* MSC0 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) REG_MSU_MSC0BAR = 0x0108, /* MSC0 output base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) REG_MSU_MSC0SIZE = 0x010c, /* MSC0 output size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) REG_MSU_MSC0MWP = 0x0110, /* MSC0 write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) REG_MSU_MSC0NWSA = 0x011c, /* MSC0 next window start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) REG_MSU_MSC1CTL = 0x0200, /* MSC1 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) REG_MSU_MSC1STS = 0x0204, /* MSC1 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) REG_MSU_MSC1BAR = 0x0208, /* MSC1 output base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) REG_MSU_MSC1SIZE = 0x020c, /* MSC1 output size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) REG_MSU_MSC1MWP = 0x0210, /* MSC1 write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) REG_MSU_MSC1NWSA = 0x021c, /* MSC1 next window start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* MSUSTS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MSUSTS_MSU_INT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MSUSTS_MSC0BLAST BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MSUSTS_MSC1BLAST BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* MSCnCTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MSC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MSC_WRAPEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MSC_RD_HDR_OVRD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MSC_MODE (BIT(4) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MSC_LEN (BIT(8) | BIT(9) | BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* MINTCTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MICDE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define M0BLIE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define M1BLIE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* MSCnSTS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MSCSTS_WRAPSTAT BIT(1) /* Wrap occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MSCSTS_PLE BIT(2) /* Pipeline Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Multiblock/multiwindow block descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct msc_block_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 sw_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 block_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 next_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 next_win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 res0[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 hw_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 valid_dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 ts_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 ts_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 res1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MSC_BDESC sizeof(struct msc_block_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DATA_IN_PAGE (PAGE_SIZE - MSC_BDESC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* MSC multiblock sw tag bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MSC_SW_TAG_LASTBLK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MSC_SW_TAG_LASTWIN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* MSC multiblock hw tag bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MSC_HW_TAG_TRIGGER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MSC_HW_TAG_BLOCKWRAP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MSC_HW_TAG_WINWRAP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MSC_HW_TAG_ENDBIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline unsigned long msc_data_sz(struct msc_block_desc *bdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!bdesc->valid_dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return bdesc->valid_dw * 4 - MSC_BDESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline unsigned long msc_total_sz(struct msc_block_desc *bdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return bdesc->valid_dw * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline unsigned long msc_block_sz(struct msc_block_desc *bdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return bdesc->block_sz * 64 - MSC_BDESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline bool msc_block_wrapped(struct msc_block_desc *bdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (bdesc->hw_tag & (MSC_HW_TAG_BLOCKWRAP | MSC_HW_TAG_WINWRAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline bool msc_block_last_written(struct msc_block_desc *bdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if ((bdesc->hw_tag & MSC_HW_TAG_ENDBIT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (msc_data_sz(bdesc) != msc_block_sz(bdesc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* waiting for Pipeline Empty bit(s) to assert for MSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MSC_PLE_WAITLOOP_DEPTH 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* __INTEL_TH_MSU_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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