Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Intel(R) Trace Hub Global Trace Hub (GTH) data structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2014-2015 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __INTEL_TH_GTH_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __INTEL_TH_GTH_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Map output port parameter bits to symbolic names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TH_OUTPUT_PARM(name)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	TH_OUTPUT_ ## name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum intel_th_output_parm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	/* output port type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	TH_OUTPUT_PARM(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	/* generate NULL packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	TH_OUTPUT_PARM(null),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	/* packet drop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	TH_OUTPUT_PARM(drop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	/* port in reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	TH_OUTPUT_PARM(reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	/* flush out data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	TH_OUTPUT_PARM(flush),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	/* mainenance packet frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	TH_OUTPUT_PARM(smcfreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  * Register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	REG_GTH_GTHOPT0		= 0x00, /* Output ports 0..3 config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	REG_GTH_GTHOPT1		= 0x04, /* Output ports 4..7 config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	REG_GTH_SWDEST0		= 0x08, /* Switching destination masters 0..7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	REG_GTH_GSWTDEST	= 0x88, /* Global sw trace destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	REG_GTH_SMCR0		= 0x9c, /* STP mainenance for ports 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	REG_GTH_SMCR1		= 0xa0, /* STP mainenance for ports 2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	REG_GTH_SMCR2		= 0xa4, /* STP mainenance for ports 4/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	REG_GTH_SMCR3		= 0xa8, /* STP mainenance for ports 6/7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	REG_GTH_SCR		= 0xc8, /* Source control (storeEn override) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	REG_GTH_STAT		= 0xd4, /* GTH status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	REG_GTH_SCR2		= 0xd8, /* Source control (force storeEn off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	REG_GTH_DESTOVR		= 0xdc, /* Destination override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	REG_GTH_SCRPD0		= 0xe0, /* ScratchPad[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	REG_GTH_SCRPD1		= 0xe4, /* ScratchPad[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	REG_GTH_SCRPD2		= 0xe8, /* ScratchPad[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	REG_GTH_SCRPD3		= 0xec, /* ScratchPad[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	REG_TSCU_TSUCTRL	= 0x2000, /* TSCU control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	REG_TSCU_TSCUSTAT	= 0x2004, /* TSCU status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	/* Common Capture Sequencer (CTS) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	REG_CTS_C0S0_EN		= 0x30c0, /* clause_event_enable_c0s0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	REG_CTS_C0S0_ACT	= 0x3180, /* clause_action_control_c0s0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	REG_CTS_STAT		= 0x32a0, /* cts_status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	REG_CTS_CTL		= 0x32a4, /* cts_control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* waiting for Pipeline Empty bit(s) to assert for GTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GTH_PLE_WAITLOOP_DEPTH	10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TSUCTRL_CTCRESYNC	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TSCUSTAT_CTCSYNCING	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* waiting for Trigger status to assert for CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CTS_TRIG_WAITLOOP_DEPTH	10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CTS_EVENT_ENABLE_IF_ANYTHING	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CTS_ACTION_CONTROL_STATE_OFF	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CTS_ACTION_CONTROL_SET_STATE(x)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	(((x) & 0x1f) << CTS_ACTION_CONTROL_STATE_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CTS_ACTION_CONTROL_TRIGGER	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CTS_STATE_IDLE			0x10u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CTS_CTL_SEQUENCER_ENABLE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif /* __INTEL_TH_GTH_H__ */