^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SIRF hardware spinlock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "hwspinlock_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct sirf_hwspinlock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct hwspinlock_device bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Number of Hardware Spinlocks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HW_SPINLOCK_NUMBER 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Hardware spinlock register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HW_SPINLOCK_BASE 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HW_SPINLOCK_OFFSET(x) (HW_SPINLOCK_BASE + 0x4 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int sirf_hwspinlock_trylock(struct hwspinlock *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *lock_addr = lock->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* attempt to acquire the lock by reading value == 1 from it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return !!readl(lock_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void sirf_hwspinlock_unlock(struct hwspinlock *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *lock_addr = lock->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* release the lock by writing 0 to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writel(0, lock_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct hwspinlock_ops sirf_hwspinlock_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .trylock = sirf_hwspinlock_trylock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .unlock = sirf_hwspinlock_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int sirf_hwspinlock_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct sirf_hwspinlock *hwspin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct hwspinlock *hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) hwspin = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct_size(hwspin, bank.lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) HW_SPINLOCK_NUMBER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!hwspin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* retrieve io base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) hwspin->io_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (IS_ERR(hwspin->io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return PTR_ERR(hwspin->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) for (idx = 0; idx < HW_SPINLOCK_NUMBER; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) hwlock = &hwspin->bank.lock[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) hwlock->priv = hwspin->io_base + HW_SPINLOCK_OFFSET(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) platform_set_drvdata(pdev, hwspin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return devm_hwspin_lock_register(&pdev->dev, &hwspin->bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) &sirf_hwspinlock_ops, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) HW_SPINLOCK_NUMBER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct of_device_id sirf_hwpinlock_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .compatible = "sirf,hwspinlock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MODULE_DEVICE_TABLE(of, sirf_hwpinlock_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct platform_driver sirf_hwspinlock_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .probe = sirf_hwspinlock_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "atlas7_hwspinlock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .of_match_table = of_match_ptr(sirf_hwpinlock_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) module_platform_driver(sirf_hwspinlock_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODULE_DESCRIPTION("SIRF Hardware spinlock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MODULE_AUTHOR("Wei Chen <wei.chen@csr.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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