^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "hwspinlock_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct rockchip_hwspinlock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct hwspinlock_device bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Number of Hardware Spinlocks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HWSPINLOCK_NUMBER 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Hardware spinlock register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HWSPINLOCK_OFFSET(x) (0x4 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HWSPINLOCK_OWNER_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int rockchip_hwspinlock_trylock(struct hwspinlock *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *lock_addr = lock->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) writel(HWSPINLOCK_OWNER_ID, lock_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Get only first 4 bits and compare to HWSPINLOCK_OWNER_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * if equal, we attempt to acquire the lock, otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * someone else has it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return (HWSPINLOCK_OWNER_ID == (0x0F & readl(lock_addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void rockchip_hwspinlock_unlock(struct hwspinlock *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *lock_addr = lock->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Release the lock by writing 0 to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) writel(0, lock_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct hwspinlock_ops rockchip_hwspinlock_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .trylock = rockchip_hwspinlock_trylock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .unlock = rockchip_hwspinlock_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int rockchip_hwspinlock_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct rockchip_hwspinlock *hwspin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct hwspinlock *hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) hwspin = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct_size(hwspin, bank.lock, HWSPINLOCK_NUMBER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!hwspin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) hwspin->io_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (IS_ERR(hwspin->io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return PTR_ERR(hwspin->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) for (idx = 0; idx < HWSPINLOCK_NUMBER; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) hwlock = &hwspin->bank.lock[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) hwlock->priv = hwspin->io_base + HWSPINLOCK_OFFSET(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) platform_set_drvdata(pdev, hwspin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return devm_hwspin_lock_register(&pdev->dev, &hwspin->bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) &rockchip_hwspinlock_ops, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) HWSPINLOCK_NUMBER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct of_device_id rockchip_hwpinlock_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .compatible = "rockchip,hwspinlock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_DEVICE_TABLE(of, rockchip_hwpinlock_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct platform_driver rockchip_hwspinlock_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .probe = rockchip_hwspinlock_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .name = "rockchip_hwspinlock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .of_match_table = of_match_ptr(rockchip_hwpinlock_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int __init rockchip_hwspinlock_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return platform_driver_register(&rockchip_hwspinlock_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) postcore_initcall(rockchip_hwspinlock_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void __exit rockchip_hwspinlock_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) platform_driver_unregister(&rockchip_hwspinlock_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) module_exit(rockchip_hwspinlock_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODULE_DESCRIPTION("Rockchip Hardware spinlock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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