^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2015, Sony Mobile Communications AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "hwspinlock_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define QCOM_MUTEX_APPS_PROC_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define QCOM_MUTEX_NUM_LOCKS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regmap_field *field = lock->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 lock_owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ret = regmap_field_write(field, QCOM_MUTEX_APPS_PROC_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ret = regmap_field_read(field, &lock_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return lock_owner == QCOM_MUTEX_APPS_PROC_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void qcom_hwspinlock_unlock(struct hwspinlock *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct regmap_field *field = lock->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 lock_owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ret = regmap_field_read(field, &lock_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pr_err("%s: unable to query spinlock owner\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (lock_owner != QCOM_MUTEX_APPS_PROC_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pr_err("%s: spinlock not owned by us (actual owner is %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __func__, lock_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ret = regmap_field_write(field, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pr_err("%s: failed to unlock spinlock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct hwspinlock_ops qcom_hwspinlock_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .trylock = qcom_hwspinlock_trylock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .unlock = qcom_hwspinlock_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct of_device_id qcom_hwspinlock_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { .compatible = "qcom,sfpb-mutex" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { .compatible = "qcom,tcsr-mutex" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 *base, u32 *stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device_node *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!syscon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) regmap = syscon_node_to_regmap(syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) of_node_put(syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_err(&pdev->dev, "no offset in syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(&pdev->dev, "no stride syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct regmap_config tcsr_mutex_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .max_register = 0x40000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 *offset, u32 *stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* All modern platform has offset 0 and stride of 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *stride = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ERR_CAST(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int qcom_hwspinlock_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct hwspinlock_device *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct reg_field field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) size_t array_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regmap = qcom_hwspinlock_probe_syscon(pdev, &base, &stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (IS_ERR(regmap) && PTR_ERR(regmap) == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) regmap = qcom_hwspinlock_probe_mmio(pdev, &base, &stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) platform_set_drvdata(pdev, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) field.reg = base + i * stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) field.lsb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) field.msb = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regmap, field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return devm_hwspin_lock_register(&pdev->dev, bank, &qcom_hwspinlock_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0, QCOM_MUTEX_NUM_LOCKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct platform_driver qcom_hwspinlock_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .probe = qcom_hwspinlock_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "qcom_hwspinlock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .of_match_table = qcom_hwspinlock_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int __init qcom_hwspinlock_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return platform_driver_register(&qcom_hwspinlock_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* board init code might need to reserve hwspinlocks for predefined purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) postcore_initcall(qcom_hwspinlock_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void __exit qcom_hwspinlock_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) platform_driver_unregister(&qcom_hwspinlock_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) module_exit(qcom_hwspinlock_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_DESCRIPTION("Hardware spinlock driver for Qualcomm SoCs");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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