^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP hardware spinlock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contact: Simon Que <sque@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Hari Kanigeri <h-kanigeri2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Ohad Ben-Cohen <ohad@wizery.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "hwspinlock_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Spinlock register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SYSSTATUS_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LOCK_BASE_OFFSET 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPINLOCK_NUMLOCKS_BIT_OFFSET (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Possible values of SPINLOCK_LOCK_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPINLOCK_NOTTAKEN (0) /* free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPINLOCK_TAKEN (1) /* locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int omap_hwspinlock_trylock(struct hwspinlock *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __iomem *lock_addr = lock->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* attempt to acquire the lock by reading its value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return (SPINLOCK_NOTTAKEN == readl(lock_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void omap_hwspinlock_unlock(struct hwspinlock *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void __iomem *lock_addr = lock->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* release the lock by writing 0 to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) writel(SPINLOCK_NOTTAKEN, lock_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * relax the OMAP interconnect while spinning on it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * The specs recommended that the retry delay time will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * just over half of the time that a requester would be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * expected to hold the lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * The number below is taken from an hardware specs example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * obviously it is somewhat arbitrary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void omap_hwspinlock_relax(struct hwspinlock *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ndelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct hwspinlock_ops omap_hwspinlock_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .trylock = omap_hwspinlock_trylock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .unlock = omap_hwspinlock_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .relax = omap_hwspinlock_relax,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int omap_hwspinlock_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct hwspinlock_device *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct hwspinlock *hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int num_locks, i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Only a single hwspinlock block device is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int base_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) io_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (IS_ERR(io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return PTR_ERR(io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * make sure the module is enabled and clocked before reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * the module SYSSTATUS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto runtime_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Determine number of locks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) i = readl(io_base + SYSSTATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * runtime PM will make sure the clock of this module is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * enabled again iff at least one lock is requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) goto runtime_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* one of the four lsb's must be set, and nothing else */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (hweight_long(i & 0xf) != 1 || i > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto runtime_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) num_locks = i * 32; /* actual number of locks in this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto runtime_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) platform_set_drvdata(pdev, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) hwlock->priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = hwspin_lock_register(bank, &pdev->dev, &omap_hwspinlock_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) base_id, num_locks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto runtime_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev_dbg(&pdev->dev, "Registered %d locks with HwSpinlock core\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) num_locks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) runtime_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int omap_hwspinlock_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct hwspinlock_device *bank = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = hwspin_lock_unregister(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct of_device_id omap_hwspinlock_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .compatible = "ti,omap4-hwspinlock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .compatible = "ti,am654-hwspinlock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { /* end */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MODULE_DEVICE_TABLE(of, omap_hwspinlock_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct platform_driver omap_hwspinlock_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .probe = omap_hwspinlock_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .remove = omap_hwspinlock_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .name = "omap_hwspinlock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .of_match_table = of_match_ptr(omap_hwspinlock_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int __init omap_hwspinlock_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return platform_driver_register(&omap_hwspinlock_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* board init code might need to reserve hwspinlocks for predefined purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) postcore_initcall(omap_hwspinlock_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void __exit omap_hwspinlock_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) platform_driver_unregister(&omap_hwspinlock_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) module_exit(omap_hwspinlock_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_DESCRIPTION("Hardware spinlock driver for OMAP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_AUTHOR("Simon Que <sque@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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