^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * APM X-Gene SoC Hardware Monitoring Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Loc Ho <lho@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Hoan Tran <hotran@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This driver provides the following features:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - Retrieve CPU total power (uW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - Retrieve IO total power (uW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - Retrieve SoC temperature (milli-degree C) and alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mailbox_controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mailbox_client.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <acpi/pcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* SLIMpro message defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MSG_TYPE_DBG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MSG_TYPE_ERR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MSG_TYPE_PWRMGMT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MSG_TYPE(v) (((v) & 0xF0000000) >> 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MSG_TYPE_SET(v) (((v) << 28) & 0xF0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MSG_SUBTYPE(v) (((v) & 0x0F000000) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MSG_SUBTYPE_SET(v) (((v) << 24) & 0x0F000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DBG_SUBTYPE_SENSOR_READ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SENSOR_RD_MSG 0x04FFE902
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SENSOR_RD_EN_ADDR(a) ((a) & 0x000FFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PMD_PWR_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PMD_PWR_MW_REG 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SOC_PWR_REG 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SOC_PWR_MW_REG 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SOC_TEMP_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEMP_NEGATIVE_BIT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SENSOR_INVALID_DATA BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PWRMGMT_SUBTYPE_TPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TPC_ALARM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TPC_GET_ALARM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TPC_CMD(v) (((v) & 0x00FF0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TPC_CMD_SET(v) (((v) << 16) & 0x00FF0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TPC_EN_MSG(hndl, cmd, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (MSG_TYPE_SET(MSG_TYPE_PWRMGMT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MSG_SUBTYPE_SET(hndl) | TPC_CMD_SET(cmd) | type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* PCC defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCC_SIGNATURE_MASK 0x50424300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCCC_GENERATE_DB_INT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCCS_CMD_COMPLETE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCCS_SCI_DOORBEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCCS_PLATFORM_NOTIFICATION BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Arbitrary retries in case the remote processor is slow to respond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * to PCC commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCC_NUM_RETRIES 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ASYNC_MSG_FIFO_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MBOX_OP_TIMEOUTMS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WATT_TO_mWATT(x) ((x) * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define mWATT_TO_uWATT(x) ((x) * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CELSIUS_TO_mCELSIUS(x) ((x) * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define to_xgene_hwmon_dev(cl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) container_of(cl, struct xgene_hwmon_dev, mbox_client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum xgene_hwmon_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) XGENE_HWMON_V1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) XGENE_HWMON_V2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct slimpro_resp_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 param2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct xgene_hwmon_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct mbox_chan *mbox_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mbox_client mbox_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int mbox_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) spinlock_t kfifo_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mutex rd_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct completion rd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int resp_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct slimpro_resp_msg sync_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct work_struct workq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct kfifo_rec_ptr_1 async_msg_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool temp_critical_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) phys_addr_t comm_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void *pcc_comm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u64 usecs_lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * This function tests and clears a bitmask then returns its old value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static u16 xgene_word_tst_and_clr(u16 *addr, u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u16 ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val = le16_to_cpu(READ_ONCE(*addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) WRITE_ONCE(*addr, cpu_to_le16(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int xgene_hwmon_pcc_rd(struct xgene_hwmon_dev *ctx, u32 *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 *ptr = (void *)(generic_comm_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int rc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mutex_lock(&ctx->rd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) init_completion(&ctx->rd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ctx->resp_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Write signature for subspace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) WRITE_ONCE(generic_comm_base->signature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cpu_to_le32(PCC_SIGNATURE_MASK | ctx->mbox_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Write to the shared command region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) WRITE_ONCE(generic_comm_base->command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cpu_to_le16(MSG_TYPE(msg[0]) | PCCC_GENERATE_DB_INT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Flip CMD COMPLETE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val = le16_to_cpu(READ_ONCE(generic_comm_base->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val &= ~PCCS_CMD_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) WRITE_ONCE(generic_comm_base->status, cpu_to_le16(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Copy the message to the PCC comm space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (i = 0; i < sizeof(struct slimpro_resp_msg) / 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) WRITE_ONCE(ptr[i], cpu_to_le32(msg[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Ring the doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rc = mbox_send_message(ctx->mbox_chan, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(ctx->dev, "Mailbox send error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!wait_for_completion_timeout(&ctx->rd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) usecs_to_jiffies(ctx->usecs_lat))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(ctx->dev, "Mailbox operation timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) rc = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Check for error message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (MSG_TYPE(ctx->sync_msg.msg) == MSG_TYPE_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) msg[0] = ctx->sync_msg.msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) msg[1] = ctx->sync_msg.param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) msg[2] = ctx->sync_msg.param2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mbox_chan_txdone(ctx->mbox_chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ctx->resp_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mutex_unlock(&ctx->rd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int xgene_hwmon_rd(struct xgene_hwmon_dev *ctx, u32 *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mutex_lock(&ctx->rd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) init_completion(&ctx->rd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ctx->resp_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) rc = mbox_send_message(ctx->mbox_chan, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(ctx->dev, "Mailbox send error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!wait_for_completion_timeout(&ctx->rd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) msecs_to_jiffies(MBOX_OP_TIMEOUTMS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(ctx->dev, "Mailbox operation timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rc = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Check for error message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (MSG_TYPE(ctx->sync_msg.msg) == MSG_TYPE_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) msg[0] = ctx->sync_msg.msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) msg[1] = ctx->sync_msg.param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) msg[2] = ctx->sync_msg.param2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ctx->resp_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mutex_unlock(&ctx->rd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int xgene_hwmon_reg_map_rd(struct xgene_hwmon_dev *ctx, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 msg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) msg[0] = SENSOR_RD_MSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) msg[1] = SENSOR_RD_EN_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rc = xgene_hwmon_rd(ctx, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rc = xgene_hwmon_pcc_rd(ctx, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Check if sensor data is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (msg[1] & SENSOR_INVALID_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *data = msg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int xgene_hwmon_get_notification_msg(struct xgene_hwmon_dev *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 *amsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 msg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) msg[0] = TPC_EN_MSG(PWRMGMT_SUBTYPE_TPC, TPC_GET_ALARM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) msg[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rc = xgene_hwmon_pcc_rd(ctx, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) amsg[0] = msg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) amsg[1] = msg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) amsg[2] = msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int xgene_hwmon_get_cpu_pwr(struct xgene_hwmon_dev *ctx, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 watt, mwatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) rc = xgene_hwmon_reg_map_rd(ctx, PMD_PWR_REG, &watt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rc = xgene_hwmon_reg_map_rd(ctx, PMD_PWR_MW_REG, &mwatt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *val = WATT_TO_mWATT(watt) + mwatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int xgene_hwmon_get_io_pwr(struct xgene_hwmon_dev *ctx, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 watt, mwatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) rc = xgene_hwmon_reg_map_rd(ctx, SOC_PWR_REG, &watt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) rc = xgene_hwmon_reg_map_rd(ctx, SOC_PWR_MW_REG, &mwatt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *val = WATT_TO_mWATT(watt) + mwatt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int xgene_hwmon_get_temp(struct xgene_hwmon_dev *ctx, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return xgene_hwmon_reg_map_rd(ctx, SOC_TEMP_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Sensor temperature/power functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static ssize_t temp1_input_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int rc, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) rc = xgene_hwmon_get_temp(ctx, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) temp = sign_extend32(val, TEMP_NEGATIVE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return snprintf(buf, PAGE_SIZE, "%d\n", CELSIUS_TO_mCELSIUS(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static ssize_t temp1_label_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return snprintf(buf, PAGE_SIZE, "SoC Temperature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static ssize_t temp1_critical_alarm_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return snprintf(buf, PAGE_SIZE, "%d\n", ctx->temp_critical_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static ssize_t power1_label_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return snprintf(buf, PAGE_SIZE, "CPU power\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static ssize_t power2_label_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return snprintf(buf, PAGE_SIZE, "IO power\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static ssize_t power1_input_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rc = xgene_hwmon_get_cpu_pwr(ctx, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return snprintf(buf, PAGE_SIZE, "%u\n", mWATT_TO_uWATT(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static ssize_t power2_input_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct xgene_hwmon_dev *ctx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rc = xgene_hwmon_get_io_pwr(ctx, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return snprintf(buf, PAGE_SIZE, "%u\n", mWATT_TO_uWATT(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static DEVICE_ATTR_RO(temp1_label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static DEVICE_ATTR_RO(temp1_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static DEVICE_ATTR_RO(temp1_critical_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static DEVICE_ATTR_RO(power1_label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static DEVICE_ATTR_RO(power1_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static DEVICE_ATTR_RO(power2_label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static DEVICE_ATTR_RO(power2_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static struct attribute *xgene_hwmon_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) &dev_attr_temp1_label.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &dev_attr_temp1_input.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) &dev_attr_temp1_critical_alarm.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) &dev_attr_power1_label.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &dev_attr_power1_input.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) &dev_attr_power2_label.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) &dev_attr_power2_input.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ATTRIBUTE_GROUPS(xgene_hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int xgene_hwmon_tpc_alarm(struct xgene_hwmon_dev *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct slimpro_resp_msg *amsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ctx->temp_critical_alarm = !!amsg->param2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) sysfs_notify(&ctx->dev->kobj, NULL, "temp1_critical_alarm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void xgene_hwmon_process_pwrmsg(struct xgene_hwmon_dev *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct slimpro_resp_msg *amsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if ((MSG_SUBTYPE(amsg->msg) == PWRMGMT_SUBTYPE_TPC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) (TPC_CMD(amsg->msg) == TPC_ALARM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) xgene_hwmon_tpc_alarm(ctx, amsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * This function is called to process async work queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void xgene_hwmon_evt_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct slimpro_resp_msg amsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct xgene_hwmon_dev *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ctx = container_of(work, struct xgene_hwmon_dev, workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) while (kfifo_out_spinlocked(&ctx->async_msg_fifo, &amsg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) sizeof(struct slimpro_resp_msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) &ctx->kfifo_lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * If PCC, send a consumer command to Platform to get info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * If Slimpro Mailbox, get message from specific FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!acpi_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = xgene_hwmon_get_notification_msg(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) (u32 *)&amsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (MSG_TYPE(amsg.msg) == MSG_TYPE_PWRMGMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) xgene_hwmon_process_pwrmsg(ctx, &amsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int xgene_hwmon_rx_ready(struct xgene_hwmon_dev *ctx, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (IS_ERR_OR_NULL(ctx->hwmon_dev) && !ctx->resp_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Enqueue to the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) kfifo_in_spinlocked(&ctx->async_msg_fifo, msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sizeof(struct slimpro_resp_msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &ctx->kfifo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * This function is called when the SLIMpro Mailbox received a message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void xgene_hwmon_rx_cb(struct mbox_client *cl, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct xgene_hwmon_dev *ctx = to_xgene_hwmon_dev(cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * While the driver registers with the mailbox framework, an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * can be pending before the probe function completes its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * initialization. If such condition occurs, just queue up the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * as the driver is not ready for servicing the callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (xgene_hwmon_rx_ready(ctx, msg) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Response message format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * msg[0] is the return code of the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * msg[1] is the first parameter word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * msg[2] is the second parameter word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * As message only supports dword size, just assign it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Check for sync query */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ctx->resp_pending &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ((MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_ERR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_DBG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MSG_SUBTYPE(((u32 *)msg)[0]) == DBG_SUBTYPE_SENSOR_READ) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_PWRMGMT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MSG_SUBTYPE(((u32 *)msg)[0]) == PWRMGMT_SUBTYPE_TPC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) TPC_CMD(((u32 *)msg)[0]) == TPC_ALARM))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ctx->sync_msg.msg = ((u32 *)msg)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ctx->sync_msg.param1 = ((u32 *)msg)[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ctx->sync_msg.param2 = ((u32 *)msg)[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Operation waiting for response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) complete(&ctx->rd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Enqueue to the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) kfifo_in_spinlocked(&ctx->async_msg_fifo, msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) sizeof(struct slimpro_resp_msg), &ctx->kfifo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Schedule the bottom handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) schedule_work(&ctx->workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * This function is called when the PCC Mailbox received a message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void xgene_hwmon_pcc_rx_cb(struct mbox_client *cl, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct xgene_hwmon_dev *ctx = to_xgene_hwmon_dev(cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct slimpro_resp_msg amsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * While the driver registers with the mailbox framework, an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * can be pending before the probe function completes its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * initialization. If such condition occurs, just queue up the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * as the driver is not ready for servicing the callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (xgene_hwmon_rx_ready(ctx, &amsg) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) msg = generic_comm_base + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Check if platform sends interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!xgene_word_tst_and_clr(&generic_comm_base->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PCCS_SCI_DOORBEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Response message format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * msg[0] is the return code of the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * msg[1] is the first parameter word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * msg[2] is the second parameter word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * As message only supports dword size, just assign it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Check for sync query */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ctx->resp_pending &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ((MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_ERR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_DBG &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MSG_SUBTYPE(((u32 *)msg)[0]) == DBG_SUBTYPE_SENSOR_READ) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) (MSG_TYPE(((u32 *)msg)[0]) == MSG_TYPE_PWRMGMT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MSG_SUBTYPE(((u32 *)msg)[0]) == PWRMGMT_SUBTYPE_TPC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) TPC_CMD(((u32 *)msg)[0]) == TPC_ALARM))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Check if platform completes command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (xgene_word_tst_and_clr(&generic_comm_base->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PCCS_CMD_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ctx->sync_msg.msg = ((u32 *)msg)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ctx->sync_msg.param1 = ((u32 *)msg)[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ctx->sync_msg.param2 = ((u32 *)msg)[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Operation waiting for response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) complete(&ctx->rd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Platform notifies interrupt to OSPM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * OPSM schedules a consumer command to get this information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * in a workqueue. Platform must wait until OSPM has issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * a consumer command that serves this notification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Enqueue to the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) kfifo_in_spinlocked(&ctx->async_msg_fifo, &amsg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) sizeof(struct slimpro_resp_msg), &ctx->kfifo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Schedule the bottom handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) schedule_work(&ctx->workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static void xgene_hwmon_tx_done(struct mbox_client *cl, void *msg, int ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_dbg(cl->dev, "TX did not complete: CMD sent:%x, ret:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) *(u16 *)msg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_dbg(cl->dev, "TX completed. CMD sent:%x, ret:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) *(u16 *)msg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const struct acpi_device_id xgene_hwmon_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {"APMC0D29", XGENE_HWMON_V1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {"APMC0D8A", XGENE_HWMON_V2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MODULE_DEVICE_TABLE(acpi, xgene_hwmon_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int xgene_hwmon_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct xgene_hwmon_dev *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct mbox_client *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ctx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) platform_set_drvdata(pdev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) cl = &ctx->mbox_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) spin_lock_init(&ctx->kfifo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mutex_init(&ctx->rd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) rc = kfifo_alloc(&ctx->async_msg_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sizeof(struct slimpro_resp_msg) * ASYNC_MSG_FIFO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) INIT_WORK(&ctx->workq, xgene_hwmon_evt_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Request mailbox channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) cl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) cl->tx_done = xgene_hwmon_tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) cl->tx_block = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) cl->tx_tout = MBOX_OP_TIMEOUTMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) cl->knows_txdone = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (acpi_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) cl->rx_callback = xgene_hwmon_rx_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ctx->mbox_chan = mbox_request_channel(cl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (IS_ERR(ctx->mbox_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) "SLIMpro mailbox channel request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) goto out_mbox_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct acpi_pcct_hw_reduced *cppc_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) const struct acpi_device_id *acpi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!acpi_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) version = (int)acpi_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (device_property_read_u32(&pdev->dev, "pcc-channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) &ctx->mbox_idx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(&pdev->dev, "no pcc-channel property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) goto out_mbox_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) cl->rx_callback = xgene_hwmon_pcc_rx_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ctx->mbox_chan = pcc_mbox_request_channel(cl, ctx->mbox_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (IS_ERR(ctx->mbox_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "PPC channel request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto out_mbox_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * The PCC mailbox controller driver should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * have parsed the PCCT (global table of all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * PCC channels) and stored pointers to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * subspace communication region in con_priv.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) cppc_ss = ctx->mbox_chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (!cppc_ss) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_err(&pdev->dev, "PPC subspace not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!ctx->mbox_chan->mbox->txdone_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(&pdev->dev, "PCC IRQ not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * This is the shared communication region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * for the OS and Platform to communicate over.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ctx->comm_base_addr = cppc_ss->base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ctx->comm_base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (version == XGENE_HWMON_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ctx->pcc_comm_addr = (void __force *)ioremap(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ctx->comm_base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) cppc_ss->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ctx->pcc_comm_addr = memremap(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ctx->comm_base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) cppc_ss->length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MEMREMAP_WB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev_err(&pdev->dev, "Failed to get PCC comm region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!ctx->pcc_comm_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "Failed to ioremap PCC comm region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * cppc_ss->latency is just a Nominal value. In reality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * the remote processor could be much slower to reply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * So add an arbitrary amount of wait on top of Nominal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ctx->usecs_lat = PCC_NUM_RETRIES * cppc_ss->latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ctx->hwmon_dev = hwmon_device_register_with_groups(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "apm_xgene",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) xgene_hwmon_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (IS_ERR(ctx->hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_err(&pdev->dev, "Failed to register HW monitor device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) rc = PTR_ERR(ctx->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * Schedule the bottom handler if there is a pending message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) schedule_work(&ctx->workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_info(&pdev->dev, "APM X-Gene SoC HW monitor driver registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) mbox_free_channel(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pcc_mbox_free_channel(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) out_mbox_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) kfifo_free(&ctx->async_msg_fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int xgene_hwmon_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct xgene_hwmon_dev *ctx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) hwmon_device_unregister(ctx->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) kfifo_free(&ctx->async_msg_fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mbox_free_channel(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pcc_mbox_free_channel(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct of_device_id xgene_hwmon_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {.compatible = "apm,xgene-slimpro-hwmon"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) MODULE_DEVICE_TABLE(of, xgene_hwmon_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static struct platform_driver xgene_hwmon_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .probe = xgene_hwmon_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .remove = xgene_hwmon_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .name = "xgene-slimpro-hwmon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .of_match_table = xgene_hwmon_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .acpi_match_table = ACPI_PTR(xgene_hwmon_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) module_platform_driver(xgene_hwmon_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) MODULE_DESCRIPTION("APM X-Gene SoC hardware monitor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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