^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * w83795.c - Linux kernel driver for hardware monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008 Nuvoton Technology Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Wei Song
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Supports following chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Chip #vin #fanin #pwm #temp #dts wchipid vendid i2c ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * w83795g 21 14 8 6 8 0x79 0x5ca3 yes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * w83795adg 18 14 2 6 8 0x79 0x5ca3 yes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/util_macros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Addresses to scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const unsigned short normal_i2c[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 0x2c, 0x2d, 0x2e, 0x2f, I2C_CLIENT_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static bool reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) module_param(reset, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_PARM_DESC(reset, "Set to 1 to reset chip, not recommended");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define W83795_REG_BANKSEL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define W83795_REG_VENDORID 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define W83795_REG_CHIPID 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define W83795_REG_DEVICEID 0xfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define W83795_REG_DEVICEID_A 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define W83795_REG_I2C_ADDR 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define W83795_REG_CONFIG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define W83795_REG_CONFIG_CONFIG48 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define W83795_REG_CONFIG_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Multi-Function Pin Ctrl Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define W83795_REG_VOLT_CTRL1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define W83795_REG_VOLT_CTRL2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define W83795_REG_TEMP_CTRL1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define W83795_REG_TEMP_CTRL2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define W83795_REG_FANIN_CTRL1 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define W83795_REG_FANIN_CTRL2 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define W83795_REG_VMIGB_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEMP_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEMP_CRIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEMP_CRIT_HYST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEMP_WARN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEMP_WARN_HYST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * only crit and crit_hyst affect real-time alarm status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * current crit crit_hyst warn warn_hyst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const u16 W83795_REG_TEMP[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {0x21, 0x96, 0x97, 0x98, 0x99}, /* TD1/TR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {0x22, 0x9a, 0x9b, 0x9c, 0x9d}, /* TD2/TR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {0x23, 0x9e, 0x9f, 0xa0, 0xa1}, /* TD3/TR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {0x24, 0xa2, 0xa3, 0xa4, 0xa5}, /* TD4/TR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {0x1f, 0xa6, 0xa7, 0xa8, 0xa9}, /* TR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {0x20, 0xaa, 0xab, 0xac, 0xad}, /* TR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IN_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IN_MAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IN_LOW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const u16 W83795_REG_IN[][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Current, HL, LL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {0x10, 0x70, 0x71}, /* VSEN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {0x11, 0x72, 0x73}, /* VSEN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {0x12, 0x74, 0x75}, /* VSEN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {0x13, 0x76, 0x77}, /* VSEN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {0x14, 0x78, 0x79}, /* VSEN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {0x15, 0x7a, 0x7b}, /* VSEN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {0x16, 0x7c, 0x7d}, /* VSEN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {0x17, 0x7e, 0x7f}, /* VSEN8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {0x18, 0x80, 0x81}, /* VSEN9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {0x19, 0x82, 0x83}, /* VSEN10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {0x1A, 0x84, 0x85}, /* VSEN11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {0x1B, 0x86, 0x87}, /* VTT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {0x1C, 0x88, 0x89}, /* 3VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {0x1D, 0x8a, 0x8b}, /* 3VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {0x1E, 0x8c, 0x8d}, /* VBAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {0x1F, 0xa6, 0xa7}, /* VSEN12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {0x20, 0xaa, 0xab}, /* VSEN13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {0x21, 0x96, 0x97}, /* VSEN14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {0x22, 0x9a, 0x9b}, /* VSEN15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {0x23, 0x9e, 0x9f}, /* VSEN16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {0x24, 0xa2, 0xa3}, /* VSEN17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define W83795_REG_VRLSB 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const u8 W83795_REG_IN_HL_LSB[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x8e, /* VSEN1-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x90, /* VSEN5-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x92, /* VSEN9-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x94, /* VTT, 3VDD, 3VSB, 3VBAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0xa8, /* VSEN12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0xac, /* VSEN13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x98, /* VSEN14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x9c, /* VSEN15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0xa0, /* VSEN16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0xa4, /* VSEN17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IN_LSB_REG(index, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (((type) == 1) ? W83795_REG_IN_HL_LSB[(index)] \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) : (W83795_REG_IN_HL_LSB[(index)] + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IN_LSB_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IN_LSB_IDX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const u8 IN_LSB_SHIFT_IDX[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* High/Low LSB shift, LSB No. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0x00, 0x00}, /* VSEN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0x02, 0x00}, /* VSEN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0x04, 0x00}, /* VSEN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0x06, 0x00}, /* VSEN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0x00, 0x01}, /* VSEN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0x02, 0x01}, /* VSEN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0x04, 0x01}, /* VSEN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {0x06, 0x01}, /* VSEN8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0x00, 0x02}, /* VSEN9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0x02, 0x02}, /* VSEN10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0x04, 0x02}, /* VSEN11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x00, 0x03}, /* VTT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0x02, 0x03}, /* 3VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x04, 0x03}, /* 3VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0x06, 0x03}, /* VBAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x06, 0x04}, /* VSEN12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x06, 0x05}, /* VSEN13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x06, 0x06}, /* VSEN14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x06, 0x07}, /* VSEN15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x06, 0x08}, /* VSEN16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x06, 0x09}, /* VSEN17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define W83795_REG_FAN(index) (0x2E + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define W83795_REG_FAN_MIN_HL(index) (0xB6 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define W83795_REG_FAN_MIN_LSB(index) (0xC4 + (index) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define W83795_REG_FAN_MIN_LSB_SHIFT(index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (((index) & 1) ? 4 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define W83795_REG_VID_CTRL 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define W83795_REG_ALARM_CTRL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ALARM_CTRL_RTSACS (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define W83795_REG_ALARM(index) (0x41 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define W83795_REG_CLR_CHASSIS 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define W83795_REG_BEEP(index) (0x50 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define W83795_REG_OVT_CFG 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OVT_CFG_SEL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define W83795_REG_FCMS1 0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define W83795_REG_FCMS2 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define W83795_REG_TFMR(index) (0x202 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define W83795_REG_FOMC 0x20F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define W83795_REG_TSS(index) (0x209 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TSS_MAP_RESERVED 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const u8 tss_map[4][6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0, 1, 2, 3, 4, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 6, 7, 8, 9, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {10, 11, 12, 13, 2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 4, 5, 4, 5, TSS_MAP_RESERVED, TSS_MAP_RESERVED},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PWM_OUTPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PWM_FREQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PWM_START 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PWM_NONSTOP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PWM_STOP_TIME 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define W83795_REG_PWM(index, nr) (0x210 + (nr) * 8 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define W83795_REG_FTSH(index) (0x240 + (index) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define W83795_REG_FTSL(index) (0x241 + (index) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define W83795_REG_TFTS 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEMP_PWM_TTTI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TEMP_PWM_CTFS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TEMP_PWM_HCT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TEMP_PWM_HOT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define W83795_REG_TTTI(index) (0x260 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define W83795_REG_CTFS(index) (0x268 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define W83795_REG_HT(index) (0x270 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SF4_TEMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SF4_PWM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define W83795_REG_SF4_TEMP(temp_num, index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) (0x280 + 0x10 * (temp_num) + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define W83795_REG_SF4_PWM(temp_num, index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) (0x288 + 0x10 * (temp_num) + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define W83795_REG_DTSC 0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define W83795_REG_DTSE 0x302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define W83795_REG_DTS(index) (0x26 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define W83795_REG_PECI_TBASE(index) (0x320 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DTS_CRIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DTS_CRIT_HYST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DTS_WARN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DTS_WARN_HYST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define W83795_REG_DTS_EXT(index) (0xB2 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SETUP_PWM_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SETUP_PWM_UPTIME 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SETUP_PWM_DOWNTIME 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define W83795_REG_SETUP_PWM(index) (0x20C + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static inline u16 in_from_reg(u8 index, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* 3VDD, 3VSB and VBAT: 6 mV/bit; other inputs: 2 mV/bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (index >= 12 && index <= 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return val * 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return val * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline u16 in_to_reg(u8 index, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (index >= 12 && index <= 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return val / 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return val / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline unsigned long fan_from_reg(u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if ((val == 0xfff) || (val == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 1350000UL / val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline u16 fan_to_reg(long rpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (rpm <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return clamp_val((1350000 + (rpm >> 1)) / rpm, 1, 0xffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline unsigned long time_from_reg(u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return reg * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline u8 time_to_reg(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return clamp_val((val + 50) / 100, 0, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static inline long temp_from_reg(s8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return reg * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static inline s8 temp_to_reg(long val, s8 min, s8 max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return clamp_val(val / 1000, min, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const u16 pwm_freq_cksel0[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 1024, 512, 341, 256, 205, 171, 146, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 85, 64, 32, 16, 8, 4, 2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static unsigned int pwm_freq_from_reg(u8 reg, u16 clkin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long base_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (reg & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) base_clock = clkin * 1000 / ((clkin == 48000) ? 384 : 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return base_clock / ((reg & 0x7f) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return pwm_freq_cksel0[reg & 0x0f];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static u8 pwm_freq_to_reg(unsigned long val, u16 clkin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long base_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 reg0, reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned long best0, best1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Best fit for cksel = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) reg0 = find_closest_descending(val, pwm_freq_cksel0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ARRAY_SIZE(pwm_freq_cksel0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (val < 375) /* cksel = 1 can't beat this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return reg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) best0 = pwm_freq_cksel0[reg0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Best fit for cksel = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) base_clock = clkin * 1000 / ((clkin == 48000) ? 384 : 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reg1 = clamp_val(DIV_ROUND_CLOSEST(base_clock, val), 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) best1 = base_clock / reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) reg1 = 0x80 | (reg1 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Choose the closest one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (abs(val - best0) > abs(val - best1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return reg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) enum chip_types {w83795g, w83795adg};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct w83795_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long last_updated; /* In jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) enum chip_types chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 has_in; /* Enable monitor VIN or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 has_dyn_in; /* Only in2-0 can have this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u16 in[21][3]; /* Register value, read/high/low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 in_lsb[10][3]; /* LSB Register value, high/low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 has_gain; /* has gain: in17-20 * 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u16 has_fan; /* Enable fan14-1 or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u16 fan[14]; /* Register value combine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u16 fan_min[14]; /* Register value combine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 has_temp; /* Enable monitor temp6-1 or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) s8 temp[6][5]; /* current, crit, crit_hyst, warn, warn_hyst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 temp_read_vrlsb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 temp_mode; /* Bit vector, 0 = TR, 1 = TD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 temp_src[3]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 enable_dts; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Enable PECI and SB-TSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * bit 0: =1 enable, =0 disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * bit 1: =1 AMD SB-TSI, =0 Intel PECI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 has_dts; /* Enable monitor DTS temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) s8 dts[8]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 dts_read_vrlsb[8]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) s8 dts_ext[4]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 has_pwm; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * 795g supports 8 pwm, 795adg only supports 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * no config register, only affected by chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 pwm[8][5]; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Register value, output, freq, start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * non stop, stop time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u16 clkin; /* CLKIN frequency in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 pwm_fcms[2]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 pwm_tfmr[6]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 pwm_fomc; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u16 target_speed[8]; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Register value, target speed for speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * cruise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 tol_speed; /* tolerance of target speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 pwm_temp[6][4]; /* TTTI, CTFS, HCT, HOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 sf4_reg[6][2][7]; /* 6 temp, temp/dcpwm, 7 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 setup_pwm[3]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 alarms[6]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 enable_beep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u8 beeps[6]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) char valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) char valid_limits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) char valid_pwm_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Hardware access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * We assume that nobdody can change the bank outside the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Must be called with data->update_lock held, except during initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int w83795_set_bank(struct i2c_client *client, u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* If the same bank is already set, nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if ((data->bank & 0x07) == bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Change to new bank, preserve all other bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) bank |= data->bank & ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err = i2c_smbus_write_byte_data(client, W83795_REG_BANKSEL, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "Failed to set bank to %d, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) (int)bank, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) data->bank = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Must be called with data->update_lock held, except during initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static u8 w83795_read(struct i2c_client *client, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) err = w83795_set_bank(client, reg >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0x00; /* Arbitrary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) err = i2c_smbus_read_byte_data(client, reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "Failed to read from register 0x%03x, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) (int)reg, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0x00; /* Arbitrary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Must be called with data->update_lock held, except during initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int w83795_write(struct i2c_client *client, u16 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) err = w83795_set_bank(client, reg >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) err = i2c_smbus_write_byte_data(client, reg & 0xff, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "Failed to write to register 0x%03x, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) (int)reg, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static void w83795_update_limits(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int i, limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Read the voltage limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) for (i = 0; i < ARRAY_SIZE(data->in); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!(data->has_in & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) data->in[i][IN_MAX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) w83795_read(client, W83795_REG_IN[i][IN_MAX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) data->in[i][IN_LOW] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) w83795_read(client, W83795_REG_IN[i][IN_LOW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) for (i = 0; i < ARRAY_SIZE(data->in_lsb); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if ((i == 2 && data->chip_type == w83795adg) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) (i >= 4 && !(data->has_in & (1 << (i + 11)))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) data->in_lsb[i][IN_MAX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) w83795_read(client, IN_LSB_REG(i, IN_MAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) data->in_lsb[i][IN_LOW] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) w83795_read(client, IN_LSB_REG(i, IN_LOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Read the fan limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) lsb = 0; /* Silent false gcc warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) for (i = 0; i < ARRAY_SIZE(data->fan); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Each register contains LSB for 2 fans, but we want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * read it only once to save time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if ((i & 1) == 0 && (data->has_fan & (3 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) lsb = w83795_read(client, W83795_REG_FAN_MIN_LSB(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!(data->has_fan & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) data->fan_min[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) w83795_read(client, W83795_REG_FAN_MIN_HL(i)) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) data->fan_min[i] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) (lsb >> W83795_REG_FAN_MIN_LSB_SHIFT(i)) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Read the temperature limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) for (i = 0; i < ARRAY_SIZE(data->temp); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!(data->has_temp & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for (limit = TEMP_CRIT; limit <= TEMP_WARN_HYST; limit++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) data->temp[i][limit] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) w83795_read(client, W83795_REG_TEMP[i][limit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Read the DTS limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (data->enable_dts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (limit = DTS_CRIT; limit <= DTS_WARN_HYST; limit++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) data->dts_ext[limit] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) w83795_read(client, W83795_REG_DTS_EXT(limit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Read beep settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (data->enable_beep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) for (i = 0; i < ARRAY_SIZE(data->beeps); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) data->beeps[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) w83795_read(client, W83795_REG_BEEP(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) data->valid_limits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static struct w83795_data *w83795_update_pwm_config(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int i, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (data->valid_pwm_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Read temperature source selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) for (i = 0; i < ARRAY_SIZE(data->temp_src); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) data->temp_src[i] = w83795_read(client, W83795_REG_TSS(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Read automatic fan speed control settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) data->pwm_fcms[0] = w83795_read(client, W83795_REG_FCMS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) data->pwm_fcms[1] = w83795_read(client, W83795_REG_FCMS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) for (i = 0; i < ARRAY_SIZE(data->pwm_tfmr); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) data->pwm_tfmr[i] = w83795_read(client, W83795_REG_TFMR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) data->pwm_fomc = w83795_read(client, W83795_REG_FOMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) for (i = 0; i < data->has_pwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) for (tmp = PWM_FREQ; tmp <= PWM_STOP_TIME; tmp++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) data->pwm[i][tmp] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) w83795_read(client, W83795_REG_PWM(i, tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) for (i = 0; i < ARRAY_SIZE(data->target_speed); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) data->target_speed[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) w83795_read(client, W83795_REG_FTSH(i)) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) data->target_speed[i] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) w83795_read(client, W83795_REG_FTSL(i)) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) data->tol_speed = w83795_read(client, W83795_REG_TFTS) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) for (i = 0; i < ARRAY_SIZE(data->pwm_temp); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) data->pwm_temp[i][TEMP_PWM_TTTI] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) w83795_read(client, W83795_REG_TTTI(i)) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) data->pwm_temp[i][TEMP_PWM_CTFS] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) w83795_read(client, W83795_REG_CTFS(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) tmp = w83795_read(client, W83795_REG_HT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) data->pwm_temp[i][TEMP_PWM_HCT] = tmp >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) data->pwm_temp[i][TEMP_PWM_HOT] = tmp & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Read SmartFanIV trip points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for (i = 0; i < ARRAY_SIZE(data->sf4_reg); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (tmp = 0; tmp < 7; tmp++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) data->sf4_reg[i][SF4_TEMP][tmp] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) w83795_read(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) W83795_REG_SF4_TEMP(i, tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) data->sf4_reg[i][SF4_PWM][tmp] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) w83795_read(client, W83795_REG_SF4_PWM(i, tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Read setup PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) for (i = 0; i < ARRAY_SIZE(data->setup_pwm); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) data->setup_pwm[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) w83795_read(client, W83795_REG_SETUP_PWM(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) data->valid_pwm_config = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static struct w83795_data *w83795_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u8 intrusion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!data->valid_limits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) w83795_update_limits(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!(time_after(jiffies, data->last_updated + HZ * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) || !data->valid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) goto END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Update the voltages value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) for (i = 0; i < ARRAY_SIZE(data->in); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!(data->has_in & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) tmp = w83795_read(client, W83795_REG_IN[i][IN_READ]) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tmp |= w83795_read(client, W83795_REG_VRLSB) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) data->in[i][IN_READ] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* in0-2 can have dynamic limits (W83795G only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (data->has_dyn_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u8 lsb_max = w83795_read(client, IN_LSB_REG(0, IN_MAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u8 lsb_low = w83795_read(client, IN_LSB_REG(0, IN_LOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!(data->has_dyn_in & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) data->in[i][IN_MAX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) w83795_read(client, W83795_REG_IN[i][IN_MAX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) data->in[i][IN_LOW] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) w83795_read(client, W83795_REG_IN[i][IN_LOW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) data->in_lsb[i][IN_MAX] = (lsb_max >> (2 * i)) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) data->in_lsb[i][IN_LOW] = (lsb_low >> (2 * i)) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Update fan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) for (i = 0; i < ARRAY_SIZE(data->fan); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!(data->has_fan & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) data->fan[i] = w83795_read(client, W83795_REG_FAN(i)) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) data->fan[i] |= w83795_read(client, W83795_REG_VRLSB) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Update temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) for (i = 0; i < ARRAY_SIZE(data->temp); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) data->temp[i][TEMP_READ] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) w83795_read(client, W83795_REG_TEMP[i][TEMP_READ]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) data->temp_read_vrlsb[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) w83795_read(client, W83795_REG_VRLSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Update dts temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (data->enable_dts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) for (i = 0; i < ARRAY_SIZE(data->dts); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (!(data->has_dts & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) data->dts[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) w83795_read(client, W83795_REG_DTS(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) data->dts_read_vrlsb[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) w83795_read(client, W83795_REG_VRLSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Update pwm output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) for (i = 0; i < data->has_pwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) data->pwm[i][PWM_OUTPUT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) w83795_read(client, W83795_REG_PWM(i, PWM_OUTPUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Update intrusion and alarms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * It is important to read intrusion first, because reading from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * register SMI STS6 clears the interrupt status temporarily.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) tmp = w83795_read(client, W83795_REG_ALARM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Switch to interrupt status for intrusion if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (tmp & ALARM_CTRL_RTSACS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) w83795_write(client, W83795_REG_ALARM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) tmp & ~ALARM_CTRL_RTSACS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) intrusion = w83795_read(client, W83795_REG_ALARM(5)) & (1 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Switch to real-time alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) w83795_write(client, W83795_REG_ALARM_CTRL, tmp | ALARM_CTRL_RTSACS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) for (i = 0; i < ARRAY_SIZE(data->alarms); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) data->alarms[i] = w83795_read(client, W83795_REG_ALARM(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) data->alarms[5] |= intrusion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Restore original configuration if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!(tmp & ALARM_CTRL_RTSACS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) w83795_write(client, W83795_REG_ALARM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) tmp & ~ALARM_CTRL_RTSACS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) data->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * Sysfs attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define ALARM_STATUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define BEEP_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) show_alarm_beep(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct w83795_data *data = w83795_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int index = sensor_attr->index >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int bit = sensor_attr->index & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (nr == ALARM_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) val = (data->alarms[index] >> bit) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) else /* BEEP_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) val = (data->beeps[index] >> bit) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return sprintf(buf, "%u\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) store_beep(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int index = sensor_attr->index >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int shift = sensor_attr->index & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 beep_bit = 1 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (val != 0 && val != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) data->beeps[index] = w83795_read(client, W83795_REG_BEEP(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) data->beeps[index] &= ~beep_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) data->beeps[index] |= val << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) w83795_write(client, W83795_REG_BEEP(index), data->beeps[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Write 0 to clear chassis alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) store_chassis_clear(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (kstrtoul(buf, 10, &val) < 0 || val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) val = w83795_read(client, W83795_REG_CLR_CHASSIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) val |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) w83795_write(client, W83795_REG_CLR_CHASSIS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Clear status and force cache refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) w83795_read(client, W83795_REG_ALARM(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) data->valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define FAN_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define FAN_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) show_fan(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct w83795_data *data = w83795_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (nr == FAN_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) val = data->fan[index] & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) val = data->fan_min[index] & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return sprintf(buf, "%lu\n", fan_from_reg(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) store_fan_min(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (kstrtoul(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) val = fan_to_reg(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) data->fan_min[index] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) w83795_write(client, W83795_REG_FAN_MIN_HL(index), (val >> 4) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) val &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (index & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) val <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) val |= w83795_read(client, W83795_REG_FAN_MIN_LSB(index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) val |= w83795_read(client, W83795_REG_FAN_MIN_LSB(index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) w83795_write(client, W83795_REG_FAN_MIN_LSB(index), val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct w83795_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) data = nr == PWM_OUTPUT ? w83795_update_device(dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) : w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case PWM_STOP_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) val = time_from_reg(data->pwm[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case PWM_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) val = pwm_freq_from_reg(data->pwm[index][nr], data->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) val = data->pwm[index][nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return sprintf(buf, "%u\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) store_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case PWM_STOP_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) val = time_to_reg(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case PWM_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) val = pwm_freq_to_reg(val, data->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) val = clamp_val(val, 0, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) w83795_write(client, W83795_REG_PWM(index, nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) data->pwm[index][nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Speed cruise mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (data->pwm_fcms[0] & (1 << index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) tmp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Thermal cruise or SmartFan IV mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) for (tmp = 0; tmp < 6; tmp++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (data->pwm_tfmr[tmp] & (1 << index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) tmp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) tmp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return sprintf(buf, "%u\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) store_pwm_enable(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (val < 1 || val > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #ifndef CONFIG_SENSORS_W83795_FANCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (val > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dev_warn(dev, "Automatic fan speed control support disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dev_warn(dev, "Build with CONFIG_SENSORS_W83795_FANCTRL=y if you want it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* Clear speed cruise mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) data->pwm_fcms[0] &= ~(1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) w83795_write(client, W83795_REG_FCMS1, data->pwm_fcms[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* Clear thermal cruise mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) data->pwm_tfmr[i] &= ~(1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) w83795_write(client, W83795_REG_TFMR(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) data->pwm_tfmr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) data->pwm_fcms[0] |= (1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) w83795_write(client, W83795_REG_FCMS1, data->pwm_fcms[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) int index = to_sensor_dev_attr_2(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (data->pwm_fomc & (1 << index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) mode = 0; /* DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) mode = 1; /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return sprintf(buf, "%u\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * Check whether a given temperature source can ever be useful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * Returns the number of selectable temperature channels which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int w83795_tss_useful(const struct w83795_data *data, int tsrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int useful = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (tss_map[i][tsrc] == TSS_MAP_RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (tss_map[i][tsrc] < 6) /* Analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) useful += (data->has_temp >> tss_map[i][tsrc]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) else /* Digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) useful += (data->has_dts >> (tss_map[i][tsrc] - 6)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return useful;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) show_temp_src(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u8 tmp = data->temp_src[index / 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (index & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) tmp >>= 4; /* Pick high nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) tmp &= 0x0f; /* Pick low nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* Look-up the actual temperature channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (tmp >= 4 || tss_map[tmp][index] == TSS_MAP_RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return -EINVAL; /* Shouldn't happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return sprintf(buf, "%u\n", (unsigned int)tss_map[tmp][index] + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) store_temp_src(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) unsigned long channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) u8 val = index / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (kstrtoul(buf, 10, &channel) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) channel < 1 || channel > 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* Check if request can be fulfilled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) for (tmp = 0; tmp < 4; tmp++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (tss_map[tmp][index] == channel - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (tmp == 4) /* No match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (index & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) tmp <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) data->temp_src[val] &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) data->temp_src[val] &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) data->temp_src[val] |= tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) w83795_write(client, W83795_REG_TSS(val), data->temp_src[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define TEMP_PWM_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define TEMP_PWM_FAN_MAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) show_temp_pwm_enable(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u8 tmp = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case TEMP_PWM_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) tmp = (data->pwm_fcms[1] >> index) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) tmp = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) tmp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case TEMP_PWM_FAN_MAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) tmp = data->pwm_tfmr[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return sprintf(buf, "%u\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) store_temp_pwm_enable(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (kstrtoul(buf, 10, &tmp) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case TEMP_PWM_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (tmp != 3 && tmp != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) tmp -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) data->pwm_fcms[1] &= ~(1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) data->pwm_fcms[1] |= tmp << index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) w83795_write(client, W83795_REG_FCMS2, data->pwm_fcms[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case TEMP_PWM_FAN_MAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) tmp = clamp_val(tmp, 0, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) w83795_write(client, W83795_REG_TFMR(index), tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) data->pwm_tfmr[index] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define FANIN_TARGET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define FANIN_TOL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) show_fanin(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) u16 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) case FANIN_TARGET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) tmp = fan_from_reg(data->target_speed[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) case FANIN_TOL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) tmp = data->tol_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return sprintf(buf, "%u\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) store_fanin(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) case FANIN_TARGET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) val = fan_to_reg(clamp_val(val, 0, 0xfff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) w83795_write(client, W83795_REG_FTSH(index), val >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) w83795_write(client, W83795_REG_FTSL(index), (val << 4) & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) data->target_speed[index] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) case FANIN_TOL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) val = clamp_val(val, 0, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) w83795_write(client, W83795_REG_TFTS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) data->tol_speed = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) show_temp_pwm(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) long tmp = temp_from_reg(data->pwm_temp[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return sprintf(buf, "%ld\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) store_temp_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) val /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) case TEMP_PWM_TTTI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) val = clamp_val(val, 0, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) w83795_write(client, W83795_REG_TTTI(index), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) case TEMP_PWM_CTFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) val = clamp_val(val, 0, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) w83795_write(client, W83795_REG_CTFS(index), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) case TEMP_PWM_HCT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) val = clamp_val(val, 0, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) tmp = w83795_read(client, W83795_REG_HT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) tmp &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) tmp |= (val << 4) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) w83795_write(client, W83795_REG_HT(index), tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) case TEMP_PWM_HOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) val = clamp_val(val, 0, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) tmp = w83795_read(client, W83795_REG_HT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) tmp &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) tmp |= val & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) w83795_write(client, W83795_REG_HT(index), tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) data->pwm_temp[index][nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) show_sf4_pwm(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return sprintf(buf, "%u\n", data->sf4_reg[index][SF4_PWM][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) store_sf4_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) w83795_write(client, W83795_REG_SF4_PWM(index, nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) data->sf4_reg[index][SF4_PWM][nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) show_sf4_temp(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return sprintf(buf, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) (data->sf4_reg[index][SF4_TEMP][nr]) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) store_sf4_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) val /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) w83795_write(client, W83795_REG_SF4_TEMP(index, nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) data->sf4_reg[index][SF4_TEMP][nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) show_temp(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct w83795_data *data = w83795_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) long temp = temp_from_reg(data->temp[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (nr == TEMP_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) temp += (data->temp_read_vrlsb[index] >> 6) * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return sprintf(buf, "%ld\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) store_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (kstrtol(buf, 10, &tmp) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) data->temp[index][nr] = temp_to_reg(tmp, -128, 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) w83795_write(client, W83795_REG_TEMP[index][nr], data->temp[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) show_dts_mode(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct w83795_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (data->enable_dts & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) tmp = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) tmp = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return sprintf(buf, "%d\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) show_dts(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct w83795_data *data = w83795_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) long temp = temp_from_reg(data->dts[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) temp += (data->dts_read_vrlsb[index] >> 6) * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return sprintf(buf, "%ld\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) show_dts_ext(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct w83795_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) long temp = temp_from_reg(data->dts_ext[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return sprintf(buf, "%ld\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) store_dts_ext(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (kstrtol(buf, 10, &tmp) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) data->dts_ext[nr] = temp_to_reg(tmp, -128, 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) w83795_write(client, W83795_REG_DTS_EXT(nr), data->dts_ext[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) show_temp_mode(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) struct w83795_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (data->temp_mode & (1 << index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) tmp = 3; /* Thermal diode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) tmp = 4; /* Thermistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return sprintf(buf, "%d\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* Only for temp1-4 (temp5-6 can only be thermistor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) store_temp_mode(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) int reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if ((val != 4) && (val != 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (val == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Thermal diode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) val = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) data->temp_mode |= 1 << index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) } else if (val == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* Thermistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) val = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) data->temp_mode &= ~(1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) reg_shift = 2 * index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) tmp = w83795_read(client, W83795_REG_TEMP_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) tmp &= ~(0x03 << reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) tmp |= val << reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) w83795_write(client, W83795_REG_TEMP_CTRL2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* show/store VIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) show_in(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct w83795_data *data = w83795_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u16 val = data->in[index][nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) u8 lsb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) case IN_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* calculate this value again by sensors as sensors3.conf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if ((index >= 17) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) !((data->has_gain >> (index - 17)) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) val *= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) case IN_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) case IN_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) lsb_idx = IN_LSB_SHIFT_IDX[index][IN_LSB_IDX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) val <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) val |= (data->in_lsb[lsb_idx][nr] >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) IN_LSB_SHIFT_IDX[index][IN_LSB_SHIFT]) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if ((index >= 17) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) !((data->has_gain >> (index - 17)) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) val *= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) val = in_from_reg(index, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) store_in(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) u8 lsb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) val = in_to_reg(index, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if ((index >= 17) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) !((data->has_gain >> (index - 17)) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) val /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) val = clamp_val(val, 0, 0x3FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) lsb_idx = IN_LSB_SHIFT_IDX[index][IN_LSB_IDX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) tmp = w83795_read(client, IN_LSB_REG(lsb_idx, nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) tmp &= ~(0x03 << IN_LSB_SHIFT_IDX[index][IN_LSB_SHIFT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) tmp |= (val & 0x03) << IN_LSB_SHIFT_IDX[index][IN_LSB_SHIFT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) w83795_write(client, IN_LSB_REG(lsb_idx, nr), tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) data->in_lsb[lsb_idx][nr] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) tmp = (val >> 2) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) w83795_write(client, W83795_REG_IN[index][nr], tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) data->in[index][nr] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #ifdef CONFIG_SENSORS_W83795_FANCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) show_sf_setup(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct w83795_data *data = w83795_update_pwm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) u16 val = data->setup_pwm[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) case SETUP_PWM_UPTIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) case SETUP_PWM_DOWNTIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) val = time_from_reg(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) store_sf_setup(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) case SETUP_PWM_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) val = clamp_val(val, 0, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) case SETUP_PWM_UPTIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) case SETUP_PWM_DOWNTIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) val = time_to_reg(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) data->setup_pwm[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) w83795_write(client, W83795_REG_SETUP_PWM(nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define NOT_USED -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) * Don't change the attribute order, _max, _min and _beep are accessed by index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) * somewhere else in the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define SENSOR_ATTR_IN(index) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) SENSOR_ATTR_2(in##index##_input, S_IRUGO, show_in, NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) IN_READ, index), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) SENSOR_ATTR_2(in##index##_max, S_IRUGO | S_IWUSR, show_in, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) store_in, IN_MAX, index), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) SENSOR_ATTR_2(in##index##_min, S_IRUGO | S_IWUSR, show_in, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) store_in, IN_LOW, index), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) SENSOR_ATTR_2(in##index##_alarm, S_IRUGO, show_alarm_beep, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) NULL, ALARM_STATUS, index + ((index > 14) ? 1 : 0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) SENSOR_ATTR_2(in##index##_beep, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) show_alarm_beep, store_beep, BEEP_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) index + ((index > 14) ? 1 : 0)) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) * Don't change the attribute order, _beep is accessed by index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * somewhere else in the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define SENSOR_ATTR_FAN(index) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) SENSOR_ATTR_2(fan##index##_input, S_IRUGO, show_fan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) NULL, FAN_INPUT, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) SENSOR_ATTR_2(fan##index##_min, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) show_fan, store_fan_min, FAN_MIN, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) SENSOR_ATTR_2(fan##index##_alarm, S_IRUGO, show_alarm_beep, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) NULL, ALARM_STATUS, index + 31), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) SENSOR_ATTR_2(fan##index##_beep, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) show_alarm_beep, store_beep, BEEP_ENABLE, index + 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define SENSOR_ATTR_PWM(index) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) SENSOR_ATTR_2(pwm##index, S_IWUSR | S_IRUGO, show_pwm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) store_pwm, PWM_OUTPUT, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) SENSOR_ATTR_2(pwm##index##_enable, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) show_pwm_enable, store_pwm_enable, NOT_USED, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) SENSOR_ATTR_2(pwm##index##_mode, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) show_pwm_mode, NULL, NOT_USED, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) SENSOR_ATTR_2(pwm##index##_freq, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) show_pwm, store_pwm, PWM_FREQ, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) SENSOR_ATTR_2(pwm##index##_nonstop, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) show_pwm, store_pwm, PWM_NONSTOP, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) SENSOR_ATTR_2(pwm##index##_start, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) show_pwm, store_pwm, PWM_START, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) SENSOR_ATTR_2(pwm##index##_stop_time, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) show_pwm, store_pwm, PWM_STOP_TIME, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) SENSOR_ATTR_2(fan##index##_target, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) show_fanin, store_fanin, FANIN_TARGET, index - 1) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) * Don't change the attribute order, _beep is accessed by index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * somewhere else in the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define SENSOR_ATTR_DTS(index) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) SENSOR_ATTR_2(temp##index##_type, S_IRUGO , \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) show_dts_mode, NULL, NOT_USED, index - 7), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) SENSOR_ATTR_2(temp##index##_input, S_IRUGO, show_dts, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) NULL, NOT_USED, index - 7), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) SENSOR_ATTR_2(temp##index##_crit, S_IRUGO | S_IWUSR, show_dts_ext, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) store_dts_ext, DTS_CRIT, NOT_USED), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) SENSOR_ATTR_2(temp##index##_crit_hyst, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) show_dts_ext, store_dts_ext, DTS_CRIT_HYST, NOT_USED), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) SENSOR_ATTR_2(temp##index##_max, S_IRUGO | S_IWUSR, show_dts_ext, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) store_dts_ext, DTS_WARN, NOT_USED), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) SENSOR_ATTR_2(temp##index##_max_hyst, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) show_dts_ext, store_dts_ext, DTS_WARN_HYST, NOT_USED), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) SENSOR_ATTR_2(temp##index##_alarm, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) show_alarm_beep, NULL, ALARM_STATUS, index + 17), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) SENSOR_ATTR_2(temp##index##_beep, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) show_alarm_beep, store_beep, BEEP_ENABLE, index + 17) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * Don't change the attribute order, _beep is accessed by index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * somewhere else in the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define SENSOR_ATTR_TEMP(index) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) SENSOR_ATTR_2(temp##index##_type, S_IRUGO | (index < 5 ? S_IWUSR : 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) show_temp_mode, store_temp_mode, NOT_USED, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) SENSOR_ATTR_2(temp##index##_input, S_IRUGO, show_temp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) NULL, TEMP_READ, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) SENSOR_ATTR_2(temp##index##_crit, S_IRUGO | S_IWUSR, show_temp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) store_temp, TEMP_CRIT, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) SENSOR_ATTR_2(temp##index##_crit_hyst, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) show_temp, store_temp, TEMP_CRIT_HYST, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) SENSOR_ATTR_2(temp##index##_max, S_IRUGO | S_IWUSR, show_temp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) store_temp, TEMP_WARN, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) SENSOR_ATTR_2(temp##index##_max_hyst, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) show_temp, store_temp, TEMP_WARN_HYST, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) SENSOR_ATTR_2(temp##index##_alarm, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) show_alarm_beep, NULL, ALARM_STATUS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) index + (index > 4 ? 11 : 17)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) SENSOR_ATTR_2(temp##index##_beep, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) show_alarm_beep, store_beep, BEEP_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) index + (index > 4 ? 11 : 17)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) SENSOR_ATTR_2(temp##index##_pwm_enable, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) show_temp_pwm_enable, store_temp_pwm_enable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) TEMP_PWM_ENABLE, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) SENSOR_ATTR_2(temp##index##_auto_channels_pwm, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) show_temp_pwm_enable, store_temp_pwm_enable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) TEMP_PWM_FAN_MAP, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) SENSOR_ATTR_2(thermal_cruise##index, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) show_temp_pwm, store_temp_pwm, TEMP_PWM_TTTI, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) SENSOR_ATTR_2(temp##index##_warn, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) show_temp_pwm, store_temp_pwm, TEMP_PWM_CTFS, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) SENSOR_ATTR_2(temp##index##_warn_hyst, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) show_temp_pwm, store_temp_pwm, TEMP_PWM_HCT, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) SENSOR_ATTR_2(temp##index##_operation_hyst, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) show_temp_pwm, store_temp_pwm, TEMP_PWM_HOT, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) SENSOR_ATTR_2(temp##index##_auto_point1_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) show_sf4_pwm, store_sf4_pwm, 0, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) SENSOR_ATTR_2(temp##index##_auto_point2_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) show_sf4_pwm, store_sf4_pwm, 1, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) SENSOR_ATTR_2(temp##index##_auto_point3_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) show_sf4_pwm, store_sf4_pwm, 2, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) SENSOR_ATTR_2(temp##index##_auto_point4_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) show_sf4_pwm, store_sf4_pwm, 3, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) SENSOR_ATTR_2(temp##index##_auto_point5_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) show_sf4_pwm, store_sf4_pwm, 4, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) SENSOR_ATTR_2(temp##index##_auto_point6_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) show_sf4_pwm, store_sf4_pwm, 5, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) SENSOR_ATTR_2(temp##index##_auto_point7_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) show_sf4_pwm, store_sf4_pwm, 6, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) SENSOR_ATTR_2(temp##index##_auto_point1_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) show_sf4_temp, store_sf4_temp, 0, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) SENSOR_ATTR_2(temp##index##_auto_point2_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) show_sf4_temp, store_sf4_temp, 1, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) SENSOR_ATTR_2(temp##index##_auto_point3_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) show_sf4_temp, store_sf4_temp, 2, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) SENSOR_ATTR_2(temp##index##_auto_point4_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) show_sf4_temp, store_sf4_temp, 3, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) SENSOR_ATTR_2(temp##index##_auto_point5_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) show_sf4_temp, store_sf4_temp, 4, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) SENSOR_ATTR_2(temp##index##_auto_point6_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) show_sf4_temp, store_sf4_temp, 5, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) SENSOR_ATTR_2(temp##index##_auto_point7_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) show_sf4_temp, store_sf4_temp, 6, index - 1) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static struct sensor_device_attribute_2 w83795_in[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) SENSOR_ATTR_IN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) SENSOR_ATTR_IN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) SENSOR_ATTR_IN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) SENSOR_ATTR_IN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) SENSOR_ATTR_IN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) SENSOR_ATTR_IN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) SENSOR_ATTR_IN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) SENSOR_ATTR_IN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) SENSOR_ATTR_IN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) SENSOR_ATTR_IN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) SENSOR_ATTR_IN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) SENSOR_ATTR_IN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) SENSOR_ATTR_IN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) SENSOR_ATTR_IN(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) SENSOR_ATTR_IN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) SENSOR_ATTR_IN(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) SENSOR_ATTR_IN(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) SENSOR_ATTR_IN(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) SENSOR_ATTR_IN(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) SENSOR_ATTR_IN(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) SENSOR_ATTR_IN(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static const struct sensor_device_attribute_2 w83795_fan[][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) SENSOR_ATTR_FAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) SENSOR_ATTR_FAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) SENSOR_ATTR_FAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) SENSOR_ATTR_FAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) SENSOR_ATTR_FAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) SENSOR_ATTR_FAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) SENSOR_ATTR_FAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) SENSOR_ATTR_FAN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) SENSOR_ATTR_FAN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) SENSOR_ATTR_FAN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) SENSOR_ATTR_FAN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) SENSOR_ATTR_FAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) SENSOR_ATTR_FAN(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) SENSOR_ATTR_FAN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static const struct sensor_device_attribute_2 w83795_temp[][28] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) SENSOR_ATTR_TEMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) SENSOR_ATTR_TEMP(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) SENSOR_ATTR_TEMP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) SENSOR_ATTR_TEMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) SENSOR_ATTR_TEMP(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) SENSOR_ATTR_TEMP(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static const struct sensor_device_attribute_2 w83795_dts[][8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) SENSOR_ATTR_DTS(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) SENSOR_ATTR_DTS(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) SENSOR_ATTR_DTS(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) SENSOR_ATTR_DTS(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) SENSOR_ATTR_DTS(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) SENSOR_ATTR_DTS(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) SENSOR_ATTR_DTS(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) SENSOR_ATTR_DTS(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static const struct sensor_device_attribute_2 w83795_pwm[][8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) SENSOR_ATTR_PWM(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) SENSOR_ATTR_PWM(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) SENSOR_ATTR_PWM(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) SENSOR_ATTR_PWM(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) SENSOR_ATTR_PWM(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) SENSOR_ATTR_PWM(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) SENSOR_ATTR_PWM(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) SENSOR_ATTR_PWM(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) static const struct sensor_device_attribute_2 w83795_tss[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) SENSOR_ATTR_2(temp1_source_sel, S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) show_temp_src, store_temp_src, NOT_USED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) SENSOR_ATTR_2(temp2_source_sel, S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) show_temp_src, store_temp_src, NOT_USED, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) SENSOR_ATTR_2(temp3_source_sel, S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) show_temp_src, store_temp_src, NOT_USED, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) SENSOR_ATTR_2(temp4_source_sel, S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) show_temp_src, store_temp_src, NOT_USED, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) SENSOR_ATTR_2(temp5_source_sel, S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) show_temp_src, store_temp_src, NOT_USED, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) SENSOR_ATTR_2(temp6_source_sel, S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) show_temp_src, store_temp_src, NOT_USED, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) static const struct sensor_device_attribute_2 sda_single_files[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) store_chassis_clear, ALARM_STATUS, 46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #ifdef CONFIG_SENSORS_W83795_FANCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) SENSOR_ATTR_2(speed_cruise_tolerance, S_IWUSR | S_IRUGO, show_fanin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) store_fanin, FANIN_TOL, NOT_USED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) SENSOR_ATTR_2(pwm_default, S_IWUSR | S_IRUGO, show_sf_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) store_sf_setup, SETUP_PWM_DEFAULT, NOT_USED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) SENSOR_ATTR_2(pwm_uptime, S_IWUSR | S_IRUGO, show_sf_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) store_sf_setup, SETUP_PWM_UPTIME, NOT_USED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) SENSOR_ATTR_2(pwm_downtime, S_IWUSR | S_IRUGO, show_sf_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) store_sf_setup, SETUP_PWM_DOWNTIME, NOT_USED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static const struct sensor_device_attribute_2 sda_beep_files[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) SENSOR_ATTR_2(intrusion0_beep, S_IWUSR | S_IRUGO, show_alarm_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) store_beep, BEEP_ENABLE, 46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) SENSOR_ATTR_2(beep_enable, S_IWUSR | S_IRUGO, show_alarm_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) store_beep, BEEP_ENABLE, 47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) * Driver interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static void w83795_init_client(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static const u16 clkin[4] = { /* in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) 14318, 24000, 33333, 48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) w83795_write(client, W83795_REG_CONFIG, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* Start monitoring if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) config = w83795_read(client, W83795_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (!(config & W83795_REG_CONFIG_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) dev_info(&client->dev, "Enabling monitoring operations\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) w83795_write(client, W83795_REG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) config | W83795_REG_CONFIG_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) data->clkin = clkin[(config >> 3) & 0x3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev_dbg(&client->dev, "clkin = %u kHz\n", data->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static int w83795_get_device_id(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) int device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) device_id = i2c_smbus_read_byte_data(client, W83795_REG_DEVICEID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * Special case for rev. A chips; can't be checked first because later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * revisions emulate this for compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (device_id < 0 || (device_id & 0xf0) != 0x50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) int alt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) alt_id = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) W83795_REG_DEVICEID_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (alt_id == 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) device_id = alt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) /* Return 0 if detection is successful, -ENODEV otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static int w83795_detect(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) int bank, vendor_id, device_id, expected, i2c_addr, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) unsigned short address = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) const char *chip_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) bank = i2c_smbus_read_byte_data(client, W83795_REG_BANKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (bank < 0 || (bank & 0x7c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) dev_dbg(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) "w83795: Detection failed at addr 0x%02hx, check %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) address, "bank");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /* Check Nuvoton vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) vendor_id = i2c_smbus_read_byte_data(client, W83795_REG_VENDORID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) expected = bank & 0x80 ? 0x5c : 0xa3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (vendor_id != expected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) dev_dbg(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) "w83795: Detection failed at addr 0x%02hx, check %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) address, "vendor id");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /* Check device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) device_id = w83795_get_device_id(client) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) (i2c_smbus_read_byte_data(client, W83795_REG_CHIPID) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if ((device_id >> 4) != 0x795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) dev_dbg(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) "w83795: Detection failed at addr 0x%02hx, check %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) address, "device id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) * If Nuvoton chip, address of chip and W83795_REG_I2C_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * should match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if ((bank & 0x07) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) i2c_addr = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) W83795_REG_I2C_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if ((i2c_addr & 0x7f) != address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) dev_dbg(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) "w83795: Detection failed at addr 0x%02hx, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) "check %s\n", address, "i2c addr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * Check 795 chip type: 795G or 795ADG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) * Usually we don't write to chips during detection, but here we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) * quite have the choice; hopefully it's OK, we are about to return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) * success anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if ((bank & 0x07) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) i2c_smbus_write_byte_data(client, W83795_REG_BANKSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) bank & ~0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) config = i2c_smbus_read_byte_data(client, W83795_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (config & W83795_REG_CONFIG_CONFIG48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) chip_name = "w83795adg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) chip_name = "w83795g";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) strlcpy(info->type, chip_name, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) dev_info(&adapter->dev, "Found %s rev. %c at 0x%02hx\n", chip_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) 'A' + (device_id & 0xf), address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #ifdef CONFIG_SENSORS_W83795_FANCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define NUM_PWM_ATTRIBUTES ARRAY_SIZE(w83795_pwm[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define NUM_TEMP_ATTRIBUTES ARRAY_SIZE(w83795_temp[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define NUM_PWM_ATTRIBUTES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #define NUM_TEMP_ATTRIBUTES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) static int w83795_handle_files(struct device *dev, int (*fn)(struct device *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) const struct device_attribute *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) struct w83795_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) int err, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) for (i = 0; i < ARRAY_SIZE(w83795_in); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) if (!(data->has_in & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) for (j = 0; j < ARRAY_SIZE(w83795_in[0]); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (j == 4 && !data->enable_beep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) err = fn(dev, &w83795_in[i][j].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) for (i = 0; i < ARRAY_SIZE(w83795_fan); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (!(data->has_fan & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) for (j = 0; j < ARRAY_SIZE(w83795_fan[0]); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (j == 3 && !data->enable_beep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) err = fn(dev, &w83795_fan[i][j].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) for (i = 0; i < ARRAY_SIZE(w83795_tss); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) j = w83795_tss_useful(data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (!j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) err = fn(dev, &w83795_tss[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) for (i = 0; i < ARRAY_SIZE(sda_single_files); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) err = fn(dev, &sda_single_files[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (data->enable_beep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) for (i = 0; i < ARRAY_SIZE(sda_beep_files); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) err = fn(dev, &sda_beep_files[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) for (i = 0; i < data->has_pwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) for (j = 0; j < NUM_PWM_ATTRIBUTES; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) err = fn(dev, &w83795_pwm[i][j].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) for (i = 0; i < ARRAY_SIZE(w83795_temp); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (!(data->has_temp & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) for (j = 0; j < NUM_TEMP_ATTRIBUTES; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (j == 7 && !data->enable_beep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) err = fn(dev, &w83795_temp[i][j].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (data->enable_dts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) for (i = 0; i < ARRAY_SIZE(w83795_dts); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (!(data->has_dts & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) for (j = 0; j < ARRAY_SIZE(w83795_dts[0]); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) if (j == 7 && !data->enable_beep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) err = fn(dev, &w83795_dts[i][j].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* We need a wrapper that fits in w83795_handle_files */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static int device_remove_file_wrapper(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) const struct device_attribute *attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) device_remove_file(dev, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) static void w83795_check_dynamic_in_limits(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) u8 vid_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) int i, err_max, err_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) vid_ctl = w83795_read(client, W83795_REG_VID_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) /* Return immediately if VRM isn't configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if ((vid_ctl & 0x07) == 0x00 || (vid_ctl & 0x07) == 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) data->has_dyn_in = (vid_ctl >> 3) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (!(data->has_dyn_in & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) /* Voltage limits in dynamic mode, switch to read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) err_max = sysfs_chmod_file(&client->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) &w83795_in[i][2].dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) err_min = sysfs_chmod_file(&client->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) &w83795_in[i][3].dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (err_max || err_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) "Failed to set in%d limits read-only (%d, %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) i, err_max, err_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) "in%d limits set dynamically from VID\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) /* Check pins that can be used for either temperature or voltage monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) static void w83795_apply_temp_config(struct w83795_data *data, u8 config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) int temp_chan, int in_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) /* config is a 2-bit value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) switch (config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) case 0x2: /* Voltage monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) data->has_in |= 1 << in_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) case 0x1: /* Thermal diode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) if (temp_chan >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) data->temp_mode |= 1 << temp_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) case 0x3: /* Thermistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) data->has_temp |= 1 << temp_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) static const struct i2c_device_id w83795_id[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) static int w83795_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) struct w83795_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) data = devm_kzalloc(dev, sizeof(struct w83795_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) data->chip_type = i2c_match_id(w83795_id, client)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) data->bank = i2c_smbus_read_byte_data(client, W83795_REG_BANKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* Initialize the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) w83795_init_client(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) /* Check which voltages and fans are present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) data->has_in = w83795_read(client, W83795_REG_VOLT_CTRL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) | (w83795_read(client, W83795_REG_VOLT_CTRL2) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) data->has_fan = w83795_read(client, W83795_REG_FANIN_CTRL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) | (w83795_read(client, W83795_REG_FANIN_CTRL2) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /* Check which analog temperatures and extra voltages are present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) tmp = w83795_read(client, W83795_REG_TEMP_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (tmp & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) data->enable_dts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) w83795_apply_temp_config(data, (tmp >> 2) & 0x3, 5, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) w83795_apply_temp_config(data, tmp & 0x3, 4, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) tmp = w83795_read(client, W83795_REG_TEMP_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) w83795_apply_temp_config(data, tmp >> 6, 3, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) w83795_apply_temp_config(data, (tmp >> 4) & 0x3, 2, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) w83795_apply_temp_config(data, (tmp >> 2) & 0x3, 1, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) w83795_apply_temp_config(data, tmp & 0x3, 0, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /* Check DTS enable status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (data->enable_dts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (1 & w83795_read(client, W83795_REG_DTSC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) data->enable_dts |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) data->has_dts = w83795_read(client, W83795_REG_DTSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /* Report PECI Tbase values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) if (data->enable_dts == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) if (!(data->has_dts & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) tmp = w83795_read(client, W83795_REG_PECI_TBASE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) "PECI agent %d Tbase temperature: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) i + 1, (unsigned int)tmp & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) data->has_gain = w83795_read(client, W83795_REG_VMIGB_CTRL) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /* pwm and smart fan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) if (data->chip_type == w83795g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) data->has_pwm = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) data->has_pwm = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) /* Check if BEEP pin is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) if (data->chip_type == w83795g) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) /* The W83795G has a dedicated BEEP pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) data->enable_beep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * The W83795ADG has a shared pin for OVT# and BEEP, so you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) * can't have both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) tmp = w83795_read(client, W83795_REG_OVT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if ((tmp & OVT_CFG_SEL) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) data->enable_beep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) err = w83795_handle_files(dev, device_create_file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (data->chip_type == w83795g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) w83795_check_dynamic_in_limits(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) data->hwmon_dev = hwmon_device_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if (IS_ERR(data->hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) err = PTR_ERR(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) exit_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) w83795_handle_files(dev, device_remove_file_wrapper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static int w83795_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) struct w83795_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) hwmon_device_unregister(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) w83795_handle_files(&client->dev, device_remove_file_wrapper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static const struct i2c_device_id w83795_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) { "w83795g", w83795g },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) { "w83795adg", w83795adg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) MODULE_DEVICE_TABLE(i2c, w83795_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) static struct i2c_driver w83795_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .name = "w83795",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .probe_new = w83795_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .remove = w83795_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .id_table = w83795_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .detect = w83795_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .address_list = normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) module_i2c_driver(w83795_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) MODULE_AUTHOR("Wei Song, Jean Delvare <jdelvare@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) MODULE_DESCRIPTION("W83795G/ADG hardware monitoring driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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