^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * w83793.c - Linux kernel driver for hardware monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2006 Winbond Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Yuan Mu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Rudolf Marek <r.marek@assembler.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009-2010 Sven Anders <anders@anduras.de>, ANDURAS AG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Watchdog driver part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (Based partially on fschmd driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 2007-2008 by Hans de Goede)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Supports following chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Chip #vin #fanin #pwm #temp wchipid vendid i2c ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * w83793 10 12 8 6 0x7b 0x5ca3 yes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/hwmon-vid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/kref.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WATCHDOG_TIMEOUT 2 /* 2 minute default timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Addresses to scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) I2C_CLIENT_END };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Insmod parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static unsigned short force_subclients[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) module_param_array(force_subclients, short, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_PARM_DESC(force_subclients,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "List of subclient addresses: {bus, clientaddr, subclientaddr1, subclientaddr2}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static bool reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) module_param(reset, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_PARM_DESC(reset, "Set to 1 to reset chip, not recommended");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int timeout = WATCHDOG_TIMEOUT; /* default timeout in minutes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) module_param(timeout, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_PARM_DESC(timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "Watchdog timeout in minutes. 2<= timeout <=255 (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MODULE_PARM_DESC(nowayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "Watchdog cannot be stopped once started (default="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Address 0x00, 0x0d, 0x0e, 0x0f in all three banks are reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * as ID, Bank Select registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define W83793_REG_BANKSEL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define W83793_REG_VENDORID 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define W83793_REG_CHIPID 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define W83793_REG_DEVICEID 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define W83793_REG_CONFIG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define W83793_REG_MFC 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define W83793_REG_FANIN_CTRL 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define W83793_REG_FANIN_SEL 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define W83793_REG_I2C_ADDR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define W83793_REG_I2C_SUBADDR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define W83793_REG_VID_INA 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define W83793_REG_VID_INB 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define W83793_REG_VID_LATCHA 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define W83793_REG_VID_LATCHB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define W83793_REG_VID_CTRL 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define W83793_REG_WDT_LOCK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define W83793_REG_WDT_ENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define W83793_REG_WDT_STATUS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define W83793_REG_WDT_TIMEOUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static u16 W83793_REG_TEMP_MODE[2] = { 0x5e, 0x5f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEMP_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEMP_CRIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEMP_CRIT_HYST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEMP_WARN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEMP_WARN_HYST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * only crit and crit_hyst affect real-time alarm status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * current crit crit_hyst warn warn_hyst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static u16 W83793_REG_TEMP[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {0x1c, 0x78, 0x79, 0x7a, 0x7b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {0x1d, 0x7c, 0x7d, 0x7e, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {0x1e, 0x80, 0x81, 0x82, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {0x1f, 0x84, 0x85, 0x86, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {0x20, 0x88, 0x89, 0x8a, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {0x21, 0x8c, 0x8d, 0x8e, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define W83793_REG_TEMP_LOW_BITS 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define W83793_REG_BEEP(index) (0x53 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define W83793_REG_ALARM(index) (0x4b + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define W83793_REG_CLR_CHASSIS 0x4a /* SMI MASK4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define W83793_REG_IRQ_CTRL 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define W83793_REG_OVT_CTRL 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define W83793_REG_OVT_BEEP 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IN_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IN_MAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IN_LOW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const u16 W83793_REG_IN[][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Current, High, Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0x10, 0x60, 0x61}, /* Vcore A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0x11, 0x62, 0x63}, /* Vcore B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0x12, 0x64, 0x65}, /* Vtt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0x14, 0x6a, 0x6b}, /* VSEN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {0x15, 0x6c, 0x6d}, /* VSEN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0x16, 0x6e, 0x6f}, /* +3VSEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0x17, 0x70, 0x71}, /* +12VSEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0x18, 0x72, 0x73}, /* 5VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x19, 0x74, 0x75}, /* 5VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0x1a, 0x76, 0x77}, /* VBAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Low Bits of Vcore A/B Vtt Read/High/Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const u16 W83793_REG_IN_LOW_BITS[] = { 0x1b, 0x68, 0x69 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static u8 scale_in[] = { 2, 2, 2, 16, 16, 16, 8, 24, 24, 16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static u8 scale_in_add[] = { 0, 0, 0, 0, 0, 0, 0, 150, 150, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define W83793_REG_FAN(index) (0x23 + 2 * (index)) /* High byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define W83793_REG_FAN_MIN(index) (0x90 + 2 * (index)) /* High byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define W83793_REG_PWM_DEFAULT 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define W83793_REG_PWM_ENABLE 0x207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define W83793_REG_PWM_UPTIME 0xc3 /* Unit in 0.1 second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define W83793_REG_PWM_DOWNTIME 0xc4 /* Unit in 0.1 second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define W83793_REG_TEMP_CRITICAL 0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PWM_DUTY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PWM_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PWM_NONSTOP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PWM_STOP_TIME 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define W83793_REG_PWM(index, nr) (((nr) == 0 ? 0xb3 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) (nr) == 1 ? 0x220 : 0x218) + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* bit field, fan1 is bit0, fan2 is bit1 ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define W83793_REG_TEMP_FAN_MAP(index) (0x201 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define W83793_REG_TEMP_TOL(index) (0x208 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define W83793_REG_TEMP_CRUISE(index) (0x210 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define W83793_REG_PWM_STOP_TIME(index) (0x228 + (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define W83793_REG_SF2_TEMP(index, nr) (0x230 + ((index) << 4) + (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define W83793_REG_SF2_PWM(index, nr) (0x238 + ((index) << 4) + (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline unsigned long FAN_FROM_REG(u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if ((val >= 0xfff) || (val == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 1350000UL / val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline u16 FAN_TO_REG(long rpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (rpm <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return clamp_val((1350000 + (rpm >> 1)) / rpm, 1, 0xffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline unsigned long TIME_FROM_REG(u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return reg * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline u8 TIME_TO_REG(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return clamp_val((val + 50) / 100, 0, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static inline long TEMP_FROM_REG(s8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return reg * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static inline s8 TEMP_TO_REG(long val, s8 min, s8 max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return clamp_val((val + (val < 0 ? -500 : 500)) / 1000, min, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct w83793_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) char valid; /* !=0 if following fields are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned long last_updated; /* In jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long last_nonvolatile; /* In jiffies, last time we update the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * nonvolatile registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 vrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 vid[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 in[10][3]; /* Register value, read/high/low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 in_low_bits[3]; /* Additional resolution for VCore A/B Vtt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u16 has_fan; /* Only fan1- fan5 has own pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u16 fan[12]; /* Register value combine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u16 fan_min[12]; /* Register value combine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) s8 temp[6][5]; /* current, crit, crit_hyst,warn, warn_hyst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 temp_low_bits; /* Additional resolution TD1-TD4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 temp_mode[2]; /* byte 0: Temp D1-D4 mode each has 2 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * byte 1: Temp R1,R2 mode, each has 1 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 temp_critical; /* If reached all fan will be at full speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 temp_fan_map[6]; /* Temp controls which pwm fan, bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 has_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u8 has_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 has_vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 pwm_enable; /* Register value, each Temp has 1 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 pwm_uptime; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 pwm_downtime; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 pwm_default; /* All fan default pwm, next poweron valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 pwm[8][3]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 pwm_stop_time[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 temp_cruise[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 alarms[5]; /* realtime status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u8 beeps[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 beep_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 tolerance[3]; /* Temp tolerance(Smart Fan I/II) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 sf2_pwm[6][7]; /* Smart FanII: Fan duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 sf2_temp[6][7]; /* Smart FanII: Temp level point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct mutex watchdog_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct list_head list; /* member of the watchdog_data_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct kref kref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct miscdevice watchdog_miscdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long watchdog_is_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) char watchdog_expect_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) char watchdog_name[10]; /* must be unique to avoid sysfs conflict */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int watchdog_caused_reboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int watchdog_timeout; /* watchdog timeout in minutes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Somewhat ugly :( global data pointer list with all devices, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * we can find our device data as when using misc_register. There is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * other method to get to one's device data from the open file-op and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * for usage in the reboot notifier callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static LIST_HEAD(watchdog_data_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Note this lock not only protect list access, but also data.kref access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static DEFINE_MUTEX(watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Release our data struct when we're detached from the i2c client *and* all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * references to our watchdog device are released
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void w83793_release_resources(struct kref *ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct w83793_data *data = container_of(ref, struct w83793_data, kref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static u8 w83793_read_value(struct i2c_client *client, u16 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int w83793_write_value(struct i2c_client *client, u16 reg, u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int w83793_probe(struct i2c_client *client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int w83793_detect(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct i2c_board_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int w83793_remove(struct i2c_client *client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void w83793_init_client(struct i2c_client *client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void w83793_update_nonvolatile(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct w83793_data *w83793_update_device(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct i2c_device_id w83793_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { "w83793", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_DEVICE_TABLE(i2c, w83793_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct i2c_driver w83793_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .name = "w83793",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .probe_new = w83793_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .remove = w83793_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .id_table = w83793_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .detect = w83793_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .address_list = normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) vrm_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct w83793_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return sprintf(buf, "%d\n", data->vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) show_vid(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return sprintf(buf, "%d\n", vid_from_reg(data->vid[index], data->vrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) vrm_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct w83793_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (val > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) data->vrm = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ALARM_STATUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define BEEP_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) show_alarm_beep(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int index = sensor_attr->index >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int bit = sensor_attr->index & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (nr == ALARM_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) val = (data->alarms[index] >> (bit)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) } else { /* BEEP_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) val = (data->beeps[index] >> (bit)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return sprintf(buf, "%u\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) store_beep(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int index = sensor_attr->index >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int shift = sensor_attr->index & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u8 beep_bit = 1 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (val > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) data->beeps[index] = w83793_read_value(client, W83793_REG_BEEP(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) data->beeps[index] &= ~beep_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) data->beeps[index] |= val << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) w83793_write_value(client, W83793_REG_BEEP(index), data->beeps[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) show_beep_enable(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return sprintf(buf, "%u\n", (data->beep_enable >> 1) & 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) store_beep_enable(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (val > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) data->beep_enable = w83793_read_value(client, W83793_REG_OVT_BEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) & 0xfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) data->beep_enable |= val << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) w83793_write_value(client, W83793_REG_OVT_BEEP, data->beep_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Write 0 to clear chassis alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) store_chassis_clear(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) reg = w83793_read_value(client, W83793_REG_CLR_CHASSIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) w83793_write_value(client, W83793_REG_CLR_CHASSIS, reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) data->valid = 0; /* Force cache refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define FAN_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define FAN_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) show_fan(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (nr == FAN_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val = data->fan[index] & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) val = data->fan_min[index] & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return sprintf(buf, "%lu\n", FAN_FROM_REG(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) store_fan_min(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val = FAN_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) data->fan_min[index] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) w83793_write_value(client, W83793_REG_FAN_MIN(index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) (val >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) w83793_write_value(client, W83793_REG_FAN_MIN(index) + 1, val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (nr == PWM_STOP_TIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) val = TIME_FROM_REG(data->pwm_stop_time[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) val = (data->pwm[index][nr] & 0x3f) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) store_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (nr == PWM_STOP_TIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val = TIME_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) data->pwm_stop_time[index] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) w83793_write_value(client, W83793_REG_PWM_STOP_TIME(index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) val = clamp_val(val, 0, 0xff) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) data->pwm[index][nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) w83793_read_value(client, W83793_REG_PWM(index, nr)) & 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) data->pwm[index][nr] |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) w83793_write_value(client, W83793_REG_PWM(index, nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) data->pwm[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) show_temp(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) long temp = TEMP_FROM_REG(data->temp[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (nr == TEMP_READ && index < 4) { /* Only TD1-TD4 have low bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int low = ((data->temp_low_bits >> (index * 2)) & 0x03) * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) temp += temp > 0 ? low : -low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return sprintf(buf, "%ld\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) store_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) err = kstrtol(buf, 10, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) data->temp[index][nr] = TEMP_TO_REG(tmp, -128, 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) w83793_write_value(client, W83793_REG_TEMP[index][nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) data->temp[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * TD1-TD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * each has 4 mode:(2 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * 0: Stop monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * 1: Use internal temp sensor(default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * 2: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * 3: Use sensor in Intel CPU and get result by PECI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * TR1-TR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * each has 2 mode:(1 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * 0: Disable temp sensor monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * 1: To enable temp sensors monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* 0 disable, 6 PECI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static u8 TO_TEMP_MODE[] = { 0, 0, 0, 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) show_temp_mode(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u8 mask = (index < 4) ? 0x03 : 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u8 shift = (index < 4) ? (2 * index) : (index - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) index = (index < 4) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) tmp = (data->temp_mode[index] >> shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* for the internal sensor, found out if diode or thermistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (tmp == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) tmp = index == 0 ? 3 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) tmp = TO_TEMP_MODE[tmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return sprintf(buf, "%d\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) store_temp_mode(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u8 mask = (index < 4) ? 0x03 : 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u8 shift = (index < 4) ? (2 * index) : (index - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* transform the sysfs interface values into table above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if ((val == 6) && (index < 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } else if ((val == 3 && index < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) || (val == 4 && index >= 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* transform diode or thermistor into internal enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) val = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) index = (index < 4) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) data->temp_mode[index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) w83793_read_value(client, W83793_REG_TEMP_MODE[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) data->temp_mode[index] &= ~(mask << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) data->temp_mode[index] |= val << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) w83793_write_value(client, W83793_REG_TEMP_MODE[index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) data->temp_mode[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define SETUP_PWM_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define SETUP_PWM_UPTIME 1 /* Unit in 0.1s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define SETUP_PWM_DOWNTIME 2 /* Unit in 0.1s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define SETUP_TEMP_CRITICAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) show_sf_setup(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (nr == SETUP_PWM_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) val = (data->pwm_default & 0x3f) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) else if (nr == SETUP_PWM_UPTIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) val = TIME_FROM_REG(data->pwm_uptime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) else if (nr == SETUP_PWM_DOWNTIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) val = TIME_FROM_REG(data->pwm_downtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) else if (nr == SETUP_TEMP_CRITICAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) val = TEMP_FROM_REG(data->temp_critical & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) store_sf_setup(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (nr == SETUP_PWM_DEFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) data->pwm_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) w83793_read_value(client, W83793_REG_PWM_DEFAULT) & 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) data->pwm_default |= clamp_val(val, 0, 0xff) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) w83793_write_value(client, W83793_REG_PWM_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) data->pwm_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) } else if (nr == SETUP_PWM_UPTIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) data->pwm_uptime = TIME_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) data->pwm_uptime += data->pwm_uptime == 0 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) w83793_write_value(client, W83793_REG_PWM_UPTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) data->pwm_uptime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) } else if (nr == SETUP_PWM_DOWNTIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) data->pwm_downtime = TIME_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) data->pwm_downtime += data->pwm_downtime == 0 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) w83793_write_value(client, W83793_REG_PWM_DOWNTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) data->pwm_downtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) } else { /* SETUP_TEMP_CRITICAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) data->temp_critical =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) w83793_read_value(client, W83793_REG_TEMP_CRITICAL) & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) data->temp_critical |= TEMP_TO_REG(val, 0, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) w83793_write_value(client, W83793_REG_TEMP_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) data->temp_critical);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * Temp SmartFan control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * TEMP_FAN_MAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * Temp channel control which pwm fan, bitfield, bit 0 indicate pwm1...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * It's possible two or more temp channels control the same fan, w83793
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * always prefers to pick the most critical request and applies it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * the related Fan.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * It's possible one fan is not in any mapping of 6 temp channels, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * means the fan is manual mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * TEMP_PWM_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * Each temp channel has its own SmartFan mode, and temp channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * control fans that are set by TEMP_FAN_MAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * 0: SmartFanII mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * 1: Thermal Cruise Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * TEMP_CRUISE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * Target temperature in thermal cruise mode, w83793 will try to turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * fan speed to keep the temperature of target device around this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * TEMP_TOLERANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * If Temp higher or lower than target with this tolerance, w83793
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * will take actions to speed up or slow down the fan to keep the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * temperature within the tolerance range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define TEMP_FAN_MAP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define TEMP_PWM_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define TEMP_CRUISE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define TEMP_TOLERANCE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) show_sf_ctrl(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (nr == TEMP_FAN_MAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) val = data->temp_fan_map[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) } else if (nr == TEMP_PWM_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* +2 to transform into 2 and 3 to conform with sysfs intf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) val = ((data->pwm_enable >> index) & 0x01) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } else if (nr == TEMP_CRUISE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) val = TEMP_FROM_REG(data->temp_cruise[index] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) } else { /* TEMP_TOLERANCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) val = data->tolerance[index >> 1] >> ((index & 0x01) ? 4 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) val = TEMP_FROM_REG(val & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) store_sf_ctrl(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (nr == TEMP_FAN_MAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) val = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) w83793_write_value(client, W83793_REG_TEMP_FAN_MAP(index), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) data->temp_fan_map[index] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) } else if (nr == TEMP_PWM_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (val == 2 || val == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) data->pwm_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) w83793_read_value(client, W83793_REG_PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (val - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) data->pwm_enable |= 1 << index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) data->pwm_enable &= ~(1 << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) w83793_write_value(client, W83793_REG_PWM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) data->pwm_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) } else if (nr == TEMP_CRUISE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) data->temp_cruise[index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) w83793_read_value(client, W83793_REG_TEMP_CRUISE(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) data->temp_cruise[index] &= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) data->temp_cruise[index] |= TEMP_TO_REG(val, 0, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) w83793_write_value(client, W83793_REG_TEMP_CRUISE(index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) data->temp_cruise[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) } else { /* TEMP_TOLERANCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int i = index >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u8 shift = (index & 0x01) ? 4 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) data->tolerance[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) w83793_read_value(client, W83793_REG_TEMP_TOL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) data->tolerance[i] &= ~(0x0f << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) data->tolerance[i] |= TEMP_TO_REG(val, 0, 0x0f) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) w83793_write_value(client, W83793_REG_TEMP_TOL(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) data->tolerance[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) show_sf2_pwm(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return sprintf(buf, "%d\n", (data->sf2_pwm[index][nr] & 0x3f) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) store_sf2_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) val = clamp_val(val, 0, 0xff) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) data->sf2_pwm[index][nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) w83793_read_value(client, W83793_REG_SF2_PWM(index, nr)) & 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) data->sf2_pwm[index][nr] |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) w83793_write_value(client, W83793_REG_SF2_PWM(index, nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) data->sf2_pwm[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) show_sf2_temp(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return sprintf(buf, "%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) TEMP_FROM_REG(data->sf2_temp[index][nr] & 0x7f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) store_sf2_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) val = TEMP_TO_REG(val, 0, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) data->sf2_temp[index][nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) w83793_read_value(client, W83793_REG_SF2_TEMP(index, nr)) & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) data->sf2_temp[index][nr] |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) w83793_write_value(client, W83793_REG_SF2_TEMP(index, nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) data->sf2_temp[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* only Vcore A/B and Vtt have additional 2 bits precision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) show_in(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct w83793_data *data = w83793_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u16 val = data->in[index][nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (index < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) val <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) val += (data->in_low_bits[nr] >> (index * 2)) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* voltage inputs 5VDD and 5VSB needs 150mV offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) val = val * scale_in[index] + scale_in_add[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) store_in(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int index = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) val = (val + scale_in[index] / 2) / scale_in[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (index > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* fix the limit values of 5VDD and 5VSB to ALARM mechanism */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (nr == 1 || nr == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) val -= scale_in_add[index] / scale_in[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) val = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) val = clamp_val(val, 0, 0x3FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) data->in_low_bits[nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) w83793_read_value(client, W83793_REG_IN_LOW_BITS[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) data->in_low_bits[nr] &= ~(0x03 << (2 * index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) data->in_low_bits[nr] |= (val & 0x03) << (2 * index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) w83793_write_value(client, W83793_REG_IN_LOW_BITS[nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) data->in_low_bits[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) val >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) data->in[index][nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) w83793_write_value(client, W83793_REG_IN[index][nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) data->in[index][nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define NOT_USED -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define SENSOR_ATTR_IN(index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) SENSOR_ATTR_2(in##index##_input, S_IRUGO, show_in, NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) IN_READ, index), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) SENSOR_ATTR_2(in##index##_max, S_IRUGO | S_IWUSR, show_in, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) store_in, IN_MAX, index), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) SENSOR_ATTR_2(in##index##_min, S_IRUGO | S_IWUSR, show_in, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) store_in, IN_LOW, index), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) SENSOR_ATTR_2(in##index##_alarm, S_IRUGO, show_alarm_beep, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) NULL, ALARM_STATUS, index + ((index > 2) ? 1 : 0)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) SENSOR_ATTR_2(in##index##_beep, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) show_alarm_beep, store_beep, BEEP_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) index + ((index > 2) ? 1 : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define SENSOR_ATTR_FAN(index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) SENSOR_ATTR_2(fan##index##_alarm, S_IRUGO, show_alarm_beep, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) NULL, ALARM_STATUS, index + 17), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) SENSOR_ATTR_2(fan##index##_beep, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) show_alarm_beep, store_beep, BEEP_ENABLE, index + 17), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) SENSOR_ATTR_2(fan##index##_input, S_IRUGO, show_fan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) NULL, FAN_INPUT, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) SENSOR_ATTR_2(fan##index##_min, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) show_fan, store_fan_min, FAN_MIN, index - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define SENSOR_ATTR_PWM(index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) SENSOR_ATTR_2(pwm##index, S_IWUSR | S_IRUGO, show_pwm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) store_pwm, PWM_DUTY, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) SENSOR_ATTR_2(pwm##index##_nonstop, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) show_pwm, store_pwm, PWM_NONSTOP, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) SENSOR_ATTR_2(pwm##index##_start, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) show_pwm, store_pwm, PWM_START, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) SENSOR_ATTR_2(pwm##index##_stop_time, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) show_pwm, store_pwm, PWM_STOP_TIME, index - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define SENSOR_ATTR_TEMP(index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) SENSOR_ATTR_2(temp##index##_type, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) show_temp_mode, store_temp_mode, NOT_USED, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) SENSOR_ATTR_2(temp##index##_input, S_IRUGO, show_temp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) NULL, TEMP_READ, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SENSOR_ATTR_2(temp##index##_max, S_IRUGO | S_IWUSR, show_temp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) store_temp, TEMP_CRIT, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) SENSOR_ATTR_2(temp##index##_max_hyst, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) show_temp, store_temp, TEMP_CRIT_HYST, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) SENSOR_ATTR_2(temp##index##_warn, S_IRUGO | S_IWUSR, show_temp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) store_temp, TEMP_WARN, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) SENSOR_ATTR_2(temp##index##_warn_hyst, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) show_temp, store_temp, TEMP_WARN_HYST, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) SENSOR_ATTR_2(temp##index##_alarm, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) show_alarm_beep, NULL, ALARM_STATUS, index + 11), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) SENSOR_ATTR_2(temp##index##_beep, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) show_alarm_beep, store_beep, BEEP_ENABLE, index + 11), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) SENSOR_ATTR_2(temp##index##_auto_channels_pwm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) S_IRUGO | S_IWUSR, show_sf_ctrl, store_sf_ctrl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) TEMP_FAN_MAP, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) SENSOR_ATTR_2(temp##index##_pwm_enable, S_IWUSR | S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) show_sf_ctrl, store_sf_ctrl, TEMP_PWM_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SENSOR_ATTR_2(thermal_cruise##index, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) show_sf_ctrl, store_sf_ctrl, TEMP_CRUISE, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) SENSOR_ATTR_2(tolerance##index, S_IRUGO | S_IWUSR, show_sf_ctrl,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) store_sf_ctrl, TEMP_TOLERANCE, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) SENSOR_ATTR_2(temp##index##_auto_point1_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) show_sf2_pwm, store_sf2_pwm, 0, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) SENSOR_ATTR_2(temp##index##_auto_point2_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) show_sf2_pwm, store_sf2_pwm, 1, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) SENSOR_ATTR_2(temp##index##_auto_point3_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) show_sf2_pwm, store_sf2_pwm, 2, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) SENSOR_ATTR_2(temp##index##_auto_point4_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) show_sf2_pwm, store_sf2_pwm, 3, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) SENSOR_ATTR_2(temp##index##_auto_point5_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) show_sf2_pwm, store_sf2_pwm, 4, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) SENSOR_ATTR_2(temp##index##_auto_point6_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) show_sf2_pwm, store_sf2_pwm, 5, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) SENSOR_ATTR_2(temp##index##_auto_point7_pwm, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) show_sf2_pwm, store_sf2_pwm, 6, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) SENSOR_ATTR_2(temp##index##_auto_point1_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) show_sf2_temp, store_sf2_temp, 0, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) SENSOR_ATTR_2(temp##index##_auto_point2_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) show_sf2_temp, store_sf2_temp, 1, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) SENSOR_ATTR_2(temp##index##_auto_point3_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) show_sf2_temp, store_sf2_temp, 2, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) SENSOR_ATTR_2(temp##index##_auto_point4_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) show_sf2_temp, store_sf2_temp, 3, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) SENSOR_ATTR_2(temp##index##_auto_point5_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) show_sf2_temp, store_sf2_temp, 4, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) SENSOR_ATTR_2(temp##index##_auto_point6_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) show_sf2_temp, store_sf2_temp, 5, index - 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) SENSOR_ATTR_2(temp##index##_auto_point7_temp, S_IRUGO | S_IWUSR,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) show_sf2_temp, store_sf2_temp, 6, index - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static struct sensor_device_attribute_2 w83793_sensor_attr_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) SENSOR_ATTR_IN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) SENSOR_ATTR_IN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) SENSOR_ATTR_IN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) SENSOR_ATTR_IN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) SENSOR_ATTR_IN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) SENSOR_ATTR_IN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) SENSOR_ATTR_IN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) SENSOR_ATTR_IN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) SENSOR_ATTR_IN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) SENSOR_ATTR_IN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) SENSOR_ATTR_FAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) SENSOR_ATTR_FAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) SENSOR_ATTR_FAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) SENSOR_ATTR_FAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) SENSOR_ATTR_FAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) SENSOR_ATTR_PWM(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) SENSOR_ATTR_PWM(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) SENSOR_ATTR_PWM(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static struct sensor_device_attribute_2 w83793_temp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) SENSOR_ATTR_TEMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) SENSOR_ATTR_TEMP(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) SENSOR_ATTR_TEMP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) SENSOR_ATTR_TEMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) SENSOR_ATTR_TEMP(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SENSOR_ATTR_TEMP(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Fan6-Fan12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static struct sensor_device_attribute_2 w83793_left_fan[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) SENSOR_ATTR_FAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) SENSOR_ATTR_FAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) SENSOR_ATTR_FAN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) SENSOR_ATTR_FAN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) SENSOR_ATTR_FAN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) SENSOR_ATTR_FAN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) SENSOR_ATTR_FAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* Pwm4-Pwm8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static struct sensor_device_attribute_2 w83793_left_pwm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) SENSOR_ATTR_PWM(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) SENSOR_ATTR_PWM(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) SENSOR_ATTR_PWM(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SENSOR_ATTR_PWM(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SENSOR_ATTR_PWM(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static struct sensor_device_attribute_2 w83793_vid[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) SENSOR_ATTR_2(cpu0_vid, S_IRUGO, show_vid, NULL, NOT_USED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) SENSOR_ATTR_2(cpu1_vid, S_IRUGO, show_vid, NULL, NOT_USED, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static DEVICE_ATTR_RW(vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static struct sensor_device_attribute_2 sda_single_files[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) store_chassis_clear, ALARM_STATUS, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) SENSOR_ATTR_2(beep_enable, S_IWUSR | S_IRUGO, show_beep_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) store_beep_enable, NOT_USED, NOT_USED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SENSOR_ATTR_2(pwm_default, S_IWUSR | S_IRUGO, show_sf_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) store_sf_setup, SETUP_PWM_DEFAULT, NOT_USED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) SENSOR_ATTR_2(pwm_uptime, S_IWUSR | S_IRUGO, show_sf_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) store_sf_setup, SETUP_PWM_UPTIME, NOT_USED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) SENSOR_ATTR_2(pwm_downtime, S_IWUSR | S_IRUGO, show_sf_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) store_sf_setup, SETUP_PWM_DOWNTIME, NOT_USED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) SENSOR_ATTR_2(temp_critical, S_IWUSR | S_IRUGO, show_sf_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) store_sf_setup, SETUP_TEMP_CRITICAL, NOT_USED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static void w83793_init_client(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) w83793_write_value(client, W83793_REG_CONFIG, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* Start monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) w83793_write_value(client, W83793_REG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) w83793_read_value(client, W83793_REG_CONFIG) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * Watchdog routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static int watchdog_set_timeout(struct w83793_data *data, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) unsigned int mtimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) mtimeout = DIV_ROUND_UP(timeout, 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (mtimeout > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) mutex_lock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!data->client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) goto leave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) data->watchdog_timeout = mtimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Set Timeout value (in Minutes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) w83793_write_value(data->client, W83793_REG_WDT_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) data->watchdog_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret = mtimeout * 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) leave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mutex_unlock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static int watchdog_get_timeout(struct w83793_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) mutex_lock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) timeout = data->watchdog_timeout * 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) mutex_unlock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static int watchdog_trigger(struct w83793_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) mutex_lock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (!data->client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) goto leave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* Set Timeout value (in Minutes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) w83793_write_value(data->client, W83793_REG_WDT_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) data->watchdog_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) leave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) mutex_unlock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int watchdog_enable(struct w83793_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) mutex_lock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (!data->client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) goto leave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Set initial timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) w83793_write_value(data->client, W83793_REG_WDT_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) data->watchdog_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* Enable Soft Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) w83793_write_value(data->client, W83793_REG_WDT_LOCK, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) leave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) mutex_unlock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static int watchdog_disable(struct w83793_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) mutex_lock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!data->client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) goto leave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Disable Soft Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) w83793_write_value(data->client, W83793_REG_WDT_LOCK, 0xAA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) leave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) mutex_unlock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static int watchdog_open(struct inode *inode, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct w83793_data *pos, *data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) int watchdog_is_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * We get called from drivers/char/misc.c with misc_mtx hold, and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * call misc_register() from w83793_probe() with watchdog_data_mutex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * hold, as misc_register() takes the misc_mtx lock, this is a possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * deadlock, so we use mutex_trylock here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (!mutex_trylock(&watchdog_data_mutex))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) list_for_each_entry(pos, &watchdog_data_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (pos->watchdog_miscdev.minor == iminor(inode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) data = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* Check, if device is already open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) watchdog_is_open = test_and_set_bit(0, &data->watchdog_is_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * Increase data reference counter (if not already done).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * Note we can never not have found data, so we don't check for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (!watchdog_is_open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) kref_get(&data->kref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) mutex_unlock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Check, if device is already open and possibly issue error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (watchdog_is_open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* Enable Soft Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) watchdog_enable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* Store pointer to data into filp's private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) filp->private_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return stream_open(inode, filp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int watchdog_close(struct inode *inode, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct w83793_data *data = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (data->watchdog_expect_close) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) watchdog_disable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) data->watchdog_expect_close = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) watchdog_trigger(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) dev_crit(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) "unexpected close, not stopping watchdog!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) clear_bit(0, &data->watchdog_is_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* Decrease data reference counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) mutex_lock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) kref_put(&data->kref, w83793_release_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) mutex_unlock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static ssize_t watchdog_write(struct file *filp, const char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) size_t count, loff_t *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct w83793_data *data = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (!nowayout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /* Clear it in case it was set with a previous write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) data->watchdog_expect_close = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) for (i = 0; i != count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (get_user(c, buf + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (c == 'V')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) data->watchdog_expect_close = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = watchdog_trigger(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static long watchdog_ioctl(struct file *filp, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct watchdog_info ident = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .options = WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) WDIOF_SETTIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) WDIOF_CARDRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .identity = "w83793 watchdog"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) int val, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct w83793_data *data = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) case WDIOC_GETSUPPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (!nowayout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ident.options |= WDIOF_MAGICCLOSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (copy_to_user((void __user *)arg, &ident, sizeof(ident)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) case WDIOC_GETSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) val = data->watchdog_caused_reboot ? WDIOF_CARDRESET : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ret = put_user(val, (int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) case WDIOC_GETBOOTSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ret = put_user(0, (int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) case WDIOC_KEEPALIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ret = watchdog_trigger(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) case WDIOC_GETTIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) val = watchdog_get_timeout(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ret = put_user(val, (int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) case WDIOC_SETTIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (get_user(val, (int __user *)arg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ret = watchdog_set_timeout(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ret = put_user(ret, (int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) case WDIOC_SETOPTIONS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (get_user(val, (int __user *)arg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (val & WDIOS_DISABLECARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ret = watchdog_disable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) else if (val & WDIOS_ENABLECARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ret = watchdog_enable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static const struct file_operations watchdog_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .llseek = no_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .open = watchdog_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .release = watchdog_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .write = watchdog_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .unlocked_ioctl = watchdog_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .compat_ioctl = compat_ptr_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * Notifier for system down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static int watchdog_notify_sys(struct notifier_block *this, unsigned long code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct w83793_data *data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (code == SYS_DOWN || code == SYS_HALT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* Disable each registered watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) mutex_lock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) list_for_each_entry(data, &watchdog_data_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (data->watchdog_miscdev.minor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) watchdog_disable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) mutex_unlock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * The WDT needs to learn about soft shutdowns in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * turn the timebomb registers off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static struct notifier_block watchdog_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .notifier_call = watchdog_notify_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * Init / remove routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static int w83793_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) int i, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* Unregister the watchdog (if registered) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (data->watchdog_miscdev.minor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) misc_deregister(&data->watchdog_miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (data->watchdog_is_open) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) "i2c client detached with watchdog open! "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) "Stopping watchdog.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) watchdog_disable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) mutex_lock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) list_del(&data->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) mutex_unlock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) /* Tell the watchdog code the client is gone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) mutex_lock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) data->client = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) mutex_unlock(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* Reset Configuration Register to Disable Watch Dog Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) tmp = w83793_read_value(client, W83793_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) w83793_write_value(client, W83793_REG_CONFIG, tmp & ~0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) unregister_reboot_notifier(&watchdog_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) hwmon_device_unregister(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) for (i = 0; i < ARRAY_SIZE(w83793_sensor_attr_2); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) device_remove_file(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) &w83793_sensor_attr_2[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) for (i = 0; i < ARRAY_SIZE(sda_single_files); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) device_remove_file(dev, &sda_single_files[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) for (i = 0; i < ARRAY_SIZE(w83793_vid); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) device_remove_file(dev, &w83793_vid[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) device_remove_file(dev, &dev_attr_vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) for (i = 0; i < ARRAY_SIZE(w83793_left_fan); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) device_remove_file(dev, &w83793_left_fan[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) for (i = 0; i < ARRAY_SIZE(w83793_left_pwm); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) device_remove_file(dev, &w83793_left_pwm[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) for (i = 0; i < ARRAY_SIZE(w83793_temp); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) device_remove_file(dev, &w83793_temp[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) /* Decrease data reference counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) mutex_lock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) kref_put(&data->kref, w83793_release_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) mutex_unlock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) w83793_detect_subclients(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) int i, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) int address = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) id = i2c_adapter_id(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (force_subclients[0] == id && force_subclients[1] == address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) for (i = 2; i <= 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (force_subclients[i] < 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) || force_subclients[i] > 0x4f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) "invalid subclient "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) "address %d; must be 0x48-0x4f\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) force_subclients[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) w83793_write_value(client, W83793_REG_I2C_SUBADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) (force_subclients[2] & 0x07) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) ((force_subclients[3] & 0x07) << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) tmp = w83793_read_value(client, W83793_REG_I2C_SUBADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (!(tmp & 0x88) && (tmp & 0x7) == ((tmp >> 4) & 0x7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) "duplicate addresses 0x%x, use force_subclient\n", 0x48 + (tmp & 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (!(tmp & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) devm_i2c_new_dummy_device(&client->dev, adapter, 0x48 + (tmp & 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (!(tmp & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) devm_i2c_new_dummy_device(&client->dev, adapter, 0x48 + ((tmp >> 4) & 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /* Return 0 if detection is successful, -ENODEV otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static int w83793_detect(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) u8 tmp, bank, chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) unsigned short address = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) bank = i2c_smbus_read_byte_data(client, W83793_REG_BANKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) tmp = bank & 0x80 ? 0x5c : 0xa3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* Check Winbond vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (tmp != i2c_smbus_read_byte_data(client, W83793_REG_VENDORID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) pr_debug("w83793: Detection failed at check vendor id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * If Winbond chip, address of chip and W83793_REG_I2C_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * should match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if ((bank & 0x07) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) && i2c_smbus_read_byte_data(client, W83793_REG_I2C_ADDR) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) (address << 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) pr_debug("w83793: Detection failed at check i2c addr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* Determine the chip type now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) chip_id = i2c_smbus_read_byte_data(client, W83793_REG_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (chip_id != 0x7b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) strlcpy(info->type, "w83793", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static int w83793_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static const int watchdog_minors[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) WATCHDOG_MINOR, 212, 213, 214, 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct w83793_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) int i, tmp, val, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) int files_fan = ARRAY_SIZE(w83793_left_fan) / 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) int files_pwm = ARRAY_SIZE(w83793_left_pwm) / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) int files_temp = ARRAY_SIZE(w83793_temp) / 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) data = kzalloc(sizeof(struct w83793_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) data->bank = i2c_smbus_read_byte_data(client, W83793_REG_BANKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) mutex_init(&data->watchdog_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) INIT_LIST_HEAD(&data->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) kref_init(&data->kref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * Store client pointer in our data struct for watchdog usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * (where the client is found through a data ptr instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * otherway around)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) err = w83793_detect_subclients(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) goto free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /* Initialize the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) w83793_init_client(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * Only fan 1-5 has their own input pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) * Pwm 1-3 has their own pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) data->has_fan = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) data->has_pwm = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) tmp = w83793_read_value(client, W83793_REG_MFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) val = w83793_read_value(client, W83793_REG_FANIN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /* check the function of pins 49-56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (tmp & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) data->has_vid |= 0x2; /* has VIDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) data->has_pwm |= 0x18; /* pwm 4,5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (val & 0x01) { /* fan 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) data->has_fan |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) data->has_pwm |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (val & 0x02) { /* fan 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) data->has_fan |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) data->has_pwm |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (!(tmp & 0x40) && (val & 0x04)) { /* fan 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) data->has_fan |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) data->has_pwm |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* check the function of pins 37-40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (!(tmp & 0x29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) data->has_vid |= 0x1; /* has VIDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (0x08 == (tmp & 0x0c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (val & 0x08) /* fan 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) data->has_fan |= 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (val & 0x10) /* fan 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) data->has_fan |= 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (0x20 == (tmp & 0x30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (val & 0x20) /* fan 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) data->has_fan |= 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (val & 0x40) /* fan 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) data->has_fan |= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if ((tmp & 0x01) && (val & 0x04)) { /* fan 8, second location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) data->has_fan |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) data->has_pwm |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) tmp = w83793_read_value(client, W83793_REG_FANIN_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if ((tmp & 0x01) && (val & 0x08)) { /* fan 9, second location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) data->has_fan |= 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if ((tmp & 0x02) && (val & 0x10)) { /* fan 10, second location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) data->has_fan |= 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if ((tmp & 0x04) && (val & 0x20)) { /* fan 11, second location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) data->has_fan |= 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if ((tmp & 0x08) && (val & 0x40)) { /* fan 12, second location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) data->has_fan |= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* check the temp1-6 mode, ignore former AMDSI selected inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) tmp = w83793_read_value(client, W83793_REG_TEMP_MODE[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (tmp & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) data->has_temp |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (tmp & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) data->has_temp |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (tmp & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) data->has_temp |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (tmp & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) data->has_temp |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) tmp = w83793_read_value(client, W83793_REG_TEMP_MODE[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (tmp & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) data->has_temp |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (tmp & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) data->has_temp |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* Register sysfs hooks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) for (i = 0; i < ARRAY_SIZE(w83793_sensor_attr_2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) err = device_create_file(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) &w83793_sensor_attr_2[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) for (i = 0; i < ARRAY_SIZE(w83793_vid); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (!(data->has_vid & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) err = device_create_file(dev, &w83793_vid[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (data->has_vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) data->vrm = vid_which_vrm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) err = device_create_file(dev, &dev_attr_vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) for (i = 0; i < ARRAY_SIZE(sda_single_files); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) err = device_create_file(dev, &sda_single_files[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (!(data->has_temp & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) for (j = 0; j < files_temp; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) err = device_create_file(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) &w83793_temp[(i) * files_temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) + j].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) for (i = 5; i < 12; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (!(data->has_fan & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) for (j = 0; j < files_fan; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) err = device_create_file(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) &w83793_left_fan[(i - 5) * files_fan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) + j].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) for (i = 3; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) if (!(data->has_pwm & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) for (j = 0; j < files_pwm; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) err = device_create_file(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) &w83793_left_pwm[(i - 3) * files_pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) + j].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) data->hwmon_dev = hwmon_device_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (IS_ERR(data->hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) err = PTR_ERR(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /* Watchdog initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* Register boot notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) err = register_reboot_notifier(&watchdog_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) "cannot register reboot notifier (err=%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) goto exit_devunreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * Enable Watchdog registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * Set Configuration Register to Enable Watch Dog Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * (Bit 2) = XXXX, X1XX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) tmp = w83793_read_value(client, W83793_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) w83793_write_value(client, W83793_REG_CONFIG, tmp | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /* Set the default watchdog timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) data->watchdog_timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* Check, if last reboot was caused by watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) data->watchdog_caused_reboot =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) w83793_read_value(data->client, W83793_REG_WDT_STATUS) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* Disable Soft Watchdog during initialiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) watchdog_disable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * We take the data_mutex lock early so that watchdog_open() cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * run when misc_register() has completed, but we've not yet added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * our data to the watchdog_data_list (and set the default timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) mutex_lock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) for (i = 0; i < ARRAY_SIZE(watchdog_minors); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /* Register our watchdog part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) snprintf(data->watchdog_name, sizeof(data->watchdog_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) "watchdog%c", (i == 0) ? '\0' : ('0' + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) data->watchdog_miscdev.name = data->watchdog_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) data->watchdog_miscdev.fops = &watchdog_fops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) data->watchdog_miscdev.minor = watchdog_minors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) err = misc_register(&data->watchdog_miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) if (err == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) data->watchdog_miscdev.minor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) "Registering watchdog chardev: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) list_add(&data->list, &watchdog_data_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) "Registered watchdog chardev major 10, minor: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) watchdog_minors[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (i == ARRAY_SIZE(watchdog_minors)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) data->watchdog_miscdev.minor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) "Couldn't register watchdog chardev (due to no free minor)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) mutex_unlock(&watchdog_data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* Unregister hwmon device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) exit_devunreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) hwmon_device_unregister(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /* Unregister sysfs hooks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) exit_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) for (i = 0; i < ARRAY_SIZE(w83793_sensor_attr_2); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) device_remove_file(dev, &w83793_sensor_attr_2[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) for (i = 0; i < ARRAY_SIZE(sda_single_files); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) device_remove_file(dev, &sda_single_files[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) for (i = 0; i < ARRAY_SIZE(w83793_vid); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) device_remove_file(dev, &w83793_vid[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) for (i = 0; i < ARRAY_SIZE(w83793_left_fan); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) device_remove_file(dev, &w83793_left_fan[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) for (i = 0; i < ARRAY_SIZE(w83793_left_pwm); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) device_remove_file(dev, &w83793_left_pwm[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) for (i = 0; i < ARRAY_SIZE(w83793_temp); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) device_remove_file(dev, &w83793_temp[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) free_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static void w83793_update_nonvolatile(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * They are somewhat "stable" registers, and to update them every time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) * takes so much time, it's just not worthy. Update them in a long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * interval to avoid exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (!(time_after(jiffies, data->last_nonvolatile + HZ * 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) || !data->valid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* update voltage limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) for (i = 1; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) for (j = 0; j < ARRAY_SIZE(data->in); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) data->in[j][i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) w83793_read_value(client, W83793_REG_IN[j][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) data->in_low_bits[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) w83793_read_value(client, W83793_REG_IN_LOW_BITS[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* Update the Fan measured value and limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (!(data->has_fan & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) data->fan_min[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) w83793_read_value(client, W83793_REG_FAN_MIN(i)) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) data->fan_min[i] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) w83793_read_value(client, W83793_REG_FAN_MIN(i) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) for (i = 0; i < ARRAY_SIZE(data->temp_fan_map); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (!(data->has_temp & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) data->temp_fan_map[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) w83793_read_value(client, W83793_REG_TEMP_FAN_MAP(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) for (j = 1; j < 5; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) data->temp[i][j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) w83793_read_value(client, W83793_REG_TEMP[i][j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) data->temp_cruise[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) w83793_read_value(client, W83793_REG_TEMP_CRUISE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) for (j = 0; j < 7; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) data->sf2_pwm[i][j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) w83793_read_value(client, W83793_REG_SF2_PWM(i, j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) data->sf2_temp[i][j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) w83793_read_value(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) W83793_REG_SF2_TEMP(i, j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) for (i = 0; i < ARRAY_SIZE(data->temp_mode); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) data->temp_mode[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) w83793_read_value(client, W83793_REG_TEMP_MODE[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) for (i = 0; i < ARRAY_SIZE(data->tolerance); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) data->tolerance[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) w83793_read_value(client, W83793_REG_TEMP_TOL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) for (i = 0; i < ARRAY_SIZE(data->pwm); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (!(data->has_pwm & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) data->pwm[i][PWM_NONSTOP] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) w83793_read_value(client, W83793_REG_PWM(i, PWM_NONSTOP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) data->pwm[i][PWM_START] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) w83793_read_value(client, W83793_REG_PWM(i, PWM_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) data->pwm_stop_time[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) w83793_read_value(client, W83793_REG_PWM_STOP_TIME(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) data->pwm_default = w83793_read_value(client, W83793_REG_PWM_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) data->pwm_enable = w83793_read_value(client, W83793_REG_PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) data->pwm_uptime = w83793_read_value(client, W83793_REG_PWM_UPTIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) data->pwm_downtime = w83793_read_value(client, W83793_REG_PWM_DOWNTIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) data->temp_critical =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) w83793_read_value(client, W83793_REG_TEMP_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) data->beep_enable = w83793_read_value(client, W83793_REG_OVT_BEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) for (i = 0; i < ARRAY_SIZE(data->beeps); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) data->beeps[i] = w83793_read_value(client, W83793_REG_BEEP(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) data->last_nonvolatile = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static struct w83793_data *w83793_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (!(time_after(jiffies, data->last_updated + HZ * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) || !data->valid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) goto END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* Update the voltages measured value and limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) for (i = 0; i < ARRAY_SIZE(data->in); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) data->in[i][IN_READ] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) w83793_read_value(client, W83793_REG_IN[i][IN_READ]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) data->in_low_bits[IN_READ] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) w83793_read_value(client, W83793_REG_IN_LOW_BITS[IN_READ]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) for (i = 0; i < ARRAY_SIZE(data->fan); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (!(data->has_fan & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) data->fan[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) w83793_read_value(client, W83793_REG_FAN(i)) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) data->fan[i] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) w83793_read_value(client, W83793_REG_FAN(i) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) for (i = 0; i < ARRAY_SIZE(data->temp); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if (!(data->has_temp & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) data->temp[i][TEMP_READ] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) w83793_read_value(client, W83793_REG_TEMP[i][TEMP_READ]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) data->temp_low_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) w83793_read_value(client, W83793_REG_TEMP_LOW_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) for (i = 0; i < ARRAY_SIZE(data->pwm); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (data->has_pwm & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) data->pwm[i][PWM_DUTY] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) w83793_read_value(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) W83793_REG_PWM(i, PWM_DUTY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) for (i = 0; i < ARRAY_SIZE(data->alarms); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) data->alarms[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) w83793_read_value(client, W83793_REG_ALARM(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (data->has_vid & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) data->vid[0] = w83793_read_value(client, W83793_REG_VID_INA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (data->has_vid & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) data->vid[1] = w83793_read_value(client, W83793_REG_VID_INB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) w83793_update_nonvolatile(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) data->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) * Ignore the possibility that somebody change bank outside the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) * Must be called with data->update_lock held, except during initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) static u8 w83793_read_value(struct i2c_client *client, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) u8 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) u8 new_bank = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) new_bank |= data->bank & 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (data->bank != new_bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (i2c_smbus_write_byte_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) (client, W83793_REG_BANKSEL, new_bank) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) data->bank = new_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) "set bank to %d failed, fall back "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) "to bank %d, read reg 0x%x error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) new_bank, data->bank, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) res = 0x0; /* read 0x0 from the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) goto END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) res = i2c_smbus_read_byte_data(client, reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) /* Must be called with data->update_lock held, except during initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) static int w83793_write_value(struct i2c_client *client, u16 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) struct w83793_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) u8 new_bank = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) new_bank |= data->bank & 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (data->bank != new_bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) res = i2c_smbus_write_byte_data(client, W83793_REG_BANKSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) new_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) "set bank to %d failed, fall back "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) "to bank %d, write reg 0x%x error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) new_bank, data->bank, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) goto END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) data->bank = new_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) res = i2c_smbus_write_byte_data(client, reg & 0xff, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) module_i2c_driver(w83793_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) MODULE_AUTHOR("Yuan Mu, Sven Anders");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) MODULE_DESCRIPTION("w83793 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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