Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Driver for the Nuvoton W83773G SMBus temperature sensor IC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Supported models: W83773G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* W83773 has 3 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define W83773_CHANNELS				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* The W83773 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define W83773_CONVERSION_RATE_REG_READ		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define W83773_CONVERSION_RATE_REG_WRITE	0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define W83773_MANUFACTURER_ID_REG		0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define W83773_LOCAL_TEMP			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static const u8 W83773_STATUS[2] = { 0x02, 0x17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static const u8 W83773_TEMP_LSB[2] = { 0x10, 0x25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static const u8 W83773_TEMP_MSB[2] = { 0x01, 0x24 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static const u8 W83773_OFFSET_LSB[2] = { 0x12, 0x16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static const u8 W83773_OFFSET_MSB[2] = { 0x11, 0x15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* this is the number of sensors in the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static const struct i2c_device_id w83773_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	{ "w83773g" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) MODULE_DEVICE_TABLE(i2c, w83773_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static const struct of_device_id __maybe_unused w83773_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.compatible = "nuvoton,w83773g"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) MODULE_DEVICE_TABLE(of, w83773_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static inline long temp_of_local(s8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	return reg * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static inline long temp_of_remote(s8 hb, u8 lb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return (hb << 3 | lb >> 5) * 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static int get_local_temp(struct regmap *regmap, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ret = regmap_read(regmap, W83773_LOCAL_TEMP, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	*val = temp_of_local(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int get_remote_temp(struct regmap *regmap, int index, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned int regval_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	unsigned int regval_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	ret = regmap_read(regmap, W83773_TEMP_MSB[index], &regval_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ret = regmap_read(regmap, W83773_TEMP_LSB[index], &regval_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	*val = temp_of_remote(regval_high, regval_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int get_fault(struct regmap *regmap, int index, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	ret = regmap_read(regmap, W83773_STATUS[index], &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	*val = (regval & 0x04) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int get_offset(struct regmap *regmap, int index, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned int regval_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned int regval_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ret = regmap_read(regmap, W83773_OFFSET_MSB[index], &regval_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ret = regmap_read(regmap, W83773_OFFSET_LSB[index], &regval_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	*val = temp_of_remote(regval_high, regval_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int set_offset(struct regmap *regmap, int index, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u8 high_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 low_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	val = clamp_val(val, -127825, 127825);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* offset value equals to (high_byte << 3 | low_byte >> 5) * 125 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	val /= 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	high_byte = val >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	low_byte = (val & 0x07) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	ret = regmap_write(regmap, W83773_OFFSET_MSB[index], high_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return regmap_write(regmap, W83773_OFFSET_LSB[index], low_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int get_update_interval(struct regmap *regmap, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ret = regmap_read(regmap, W83773_CONVERSION_RATE_REG_READ, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	*val = 16000 >> regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int set_update_interval(struct regmap *regmap, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * For valid rates, interval can be calculated as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 *	interval = (1 << (8 - rate)) * 62.5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 * Rounded rate is therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 *	rate = 8 - __fls(interval * 8 / (62.5 * 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * Use clamp_val() to avoid overflows, and to ensure valid input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * for __fls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	val = clamp_val(val, 62, 16000) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	rate = 8 - __fls((val * 8 / (625 * 7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return regmap_write(regmap, W83773_CONVERSION_RATE_REG_WRITE, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int w83773_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		       u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct regmap *regmap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (type == hwmon_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (attr == hwmon_chip_update_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			return get_update_interval(regmap, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			return get_local_temp(regmap, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return get_remote_temp(regmap, channel - 1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return get_fault(regmap, channel - 1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return get_offset(regmap, channel - 1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int w83773_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct regmap *regmap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (type == hwmon_chip && attr == hwmon_chip_update_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return set_update_interval(regmap, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (type == hwmon_temp && attr == hwmon_temp_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return set_offset(regmap, channel - 1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static umode_t w83773_is_visible(const void *data, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				 u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct hwmon_channel_info *w83773_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	HWMON_CHANNEL_INFO(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			   HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			   HWMON_T_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			   HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			   HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct hwmon_ops w83773_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.is_visible = w83773_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.read = w83773_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.write = w83773_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct hwmon_chip_info w83773_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.ops = &w83773_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.info = w83773_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct regmap_config w83773_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int w83773_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	regmap = devm_regmap_init_i2c(client, &w83773_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		dev_err(dev, "failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Set the conversion rate to 2 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ret = regmap_write(regmap, W83773_CONVERSION_RATE_REG_WRITE, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		dev_err(&client->dev, "error writing config rate register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	i2c_set_clientdata(client, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	hwmon_dev = devm_hwmon_device_register_with_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 							 client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 							 regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 							 &w83773_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 							 NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct i2c_driver w83773_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.name	= "w83773g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.of_match_table = of_match_ptr(w83773_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.probe_new = w83773_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.id_table = w83773_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) module_i2c_driver(w83773_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_AUTHOR("Lei YU <mine260309@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_DESCRIPTION("W83773G temperature sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MODULE_LICENSE("GPL");