^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * w83627ehf - Driver for the hardware monitoring functionality of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * the Winbond W83627EHF Super-I/O chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 Yuan Mu (Winbond),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Rudolf Marek <r.marek@assembler.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * David Hubbard <david.c.hubbard@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Daniel J Blueman <daniel.blueman@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Shamelessly ripped from the w83627hf driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2003 Mark Studebaker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * in testing and debugging this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * This driver also supports the W83627EHG, which is the lead-free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * version of the W83627EHF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Supports the following chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Chip #vin #fan #pwm #temp chip IDs man ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 0x8860 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/hwmon-vid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "lm75.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum kinds {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) w83667hg, w83667hg_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* used to set data->name = w83627ehf_device_names[data->sio_kind] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char * const w83627ehf_device_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "w83627ehf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "w83627dhg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "w83627dhg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "w83627uhg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "w83667hg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "w83667hg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static unsigned short force_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) module_param(force_id, ushort, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MODULE_PARM_DESC(force_id, "Override the detected device ID");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRVNAME "w83627ehf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Super-I/O constants and functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define W83627EHF_LD_HWM 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define W83667HG_LD_VID 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SIO_REG_LDSEL 0x07 /* Logical device select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SIO_REG_ENABLE 0x30 /* Logical device enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SIO_REG_VID_CTRL 0xF0 /* VID control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SIO_REG_VID_DATA 0xF1 /* VID data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SIO_W83627EHF_ID 0x8850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SIO_W83627EHG_ID 0x8860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SIO_W83627DHG_ID 0xa020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SIO_W83627DHG_P_ID 0xb070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SIO_W83627UHG_ID 0xa230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SIO_W83667HG_ID 0xa510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SIO_W83667HG_B_ID 0xb350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SIO_ID_MASK 0xFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) superio_outb(int ioreg, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) outb(reg, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) outb(val, ioreg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) superio_inb(int ioreg, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) outb(reg, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return inb(ioreg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) superio_select(int ioreg, int ld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) outb(SIO_REG_LDSEL, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) outb(ld, ioreg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) superio_enter(int ioreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!request_muxed_region(ioreg, 2, DRVNAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) outb(0x87, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) outb(0x87, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) superio_exit(int ioreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) outb(0xaa, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) outb(0x02, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) outb(0x02, ioreg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) release_region(ioreg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * ISA constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IOREGION_ALIGNMENT (~7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IOREGION_OFFSET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IOREGION_LENGTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ADDR_REG_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DATA_REG_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define W83627EHF_REG_BANK 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define W83627EHF_REG_CONFIG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Not currently used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * REG_MAN_ID has the value 0x5ca3 for all supported chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * REG_MAN_ID is at port 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * REG_CHIP_ID is at port 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* The W83627EHF registers for nr=7,8,9 are in bank 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (0x554 + (((nr) - 7) * 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (0x555 + (((nr) - 7) * 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (0x550 + (nr) - 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Fan clock dividers are spread over the following five registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define W83627EHF_REG_FANDIV1 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define W83627EHF_REG_FANDIV2 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define W83627EHF_REG_VBAT 0x5D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define W83627EHF_REG_DIODE 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define W83627EHF_REG_SMI_OVT 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define W83627EHF_REG_ALARM1 0x459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define W83627EHF_REG_ALARM2 0x45A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define W83627EHF_REG_ALARM3 0x45B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* SmartFan registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* DC or PWM output fan configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const u8 W83627EHF_REG_PWM_ENABLE[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0x04, /* SYS FAN0 output mode and PWM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0x04, /* CPU FAN0 output mode and PWM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x12, /* AUX FAN mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x62, /* CPU FAN1 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* FAN Duty Cycle, be used to control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Advanced Fan control, some values are common for all fans */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) = { 0xff, 0x67, 0xff, 0x69 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) = { 0xff, 0x68, 0xff, 0x6a };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) = { 0x68, 0x6a, 0x6c };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const char *const w83667hg_b_temp_label[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "SYSTIN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "CPUTIN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "AUXTIN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "AMDTSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "PECI Agent 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "PECI Agent 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "PECI Agent 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "PECI Agent 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define NUM_REG_TEMP ARRAY_SIZE(W83627EHF_REG_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int is_word_sized(u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ((((reg & 0xff00) == 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) || (reg & 0xff00) == 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) && ((reg & 0x00ff) == 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) || (reg & 0x00ff) == 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) || (reg & 0x00ff) == 0x55))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) || (reg & 0xfff0) == 0x630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) || reg == 0x640 || reg == 0x642
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) || ((reg & 0xfff0) == 0x650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) && (reg & 0x000f) >= 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) || reg == 0x73 || reg == 0x75 || reg == 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Conversions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* 1 is PWM mode, output in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return mode ? 100 * reg : 400 * reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return clamp_val((mode ? (msec + 50) / 100 : (msec + 200) / 400),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 1, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (reg == 0 || reg == 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 1350000U / (reg << divreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) div_from_reg(u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 1 << reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Some of the voltage inputs have internal scaling, the tables below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * contain 8 (the ADC LSB in mV) * scaling factor * 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const u16 scale_in_common[10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const u16 scale_in_w83627uhg[9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Data structures and manipulation thereof
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct w83627ehf_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int addr; /* IO base of hw monitor block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u16 reg_temp[NUM_REG_TEMP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u16 reg_temp_over[NUM_REG_TEMP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u16 reg_temp_hyst[NUM_REG_TEMP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u16 reg_temp_config[NUM_REG_TEMP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 temp_src[NUM_REG_TEMP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const char * const *temp_label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) const u16 *REG_FAN_MAX_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) const u16 *REG_FAN_STEP_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) const u16 *scale_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) char valid; /* !=0 if following fields are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long last_updated; /* In jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 bank; /* current register bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 in_num; /* number of in inputs we have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 in[10]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 in_max[10]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 in_min[10]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int rpm[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u16 fan_min[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 fan_div[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 has_fan; /* some fan inputs can be disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 has_fan_min; /* some fans don't have min register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 temp_type[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) s8 temp_offset[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) s16 temp[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) s16 temp_max[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) s16 temp_max_hyst[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 caseopen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 pwm_enable[4]; /* 1->manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * 2->thermal cruise mode (also called SmartFan I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * 3->fan speed cruise mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * 4->variable thermal cruise (also called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * SmartFan III)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * 5->enhanced variable thermal cruise (also called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * SmartFan IV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 pwm_enable_orig[4]; /* original value of pwm_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 pwm_num; /* number of pwm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 pwm[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 target_temp[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 tolerance[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 fan_start_output[4]; /* minimum fan speed when spinning up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 fan_stop_time[4]; /* time at minimum before disabling fan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 fan_max_output[4]; /* maximum fan speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 fan_step_output[4]; /* rate of change output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 vrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u16 have_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u16 have_temp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 in6_skip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 temp3_val_only:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 have_vid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Remember extra register values over suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u8 vbat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 fandiv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 fandiv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct w83627ehf_sio_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int sioreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) enum kinds kind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * On older chips, only registers 0x50-0x5f are banked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * On more recent chips, all registers are banked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * Assume that is the case and set the bank number for each access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Cache the bank number so it only needs to be set if it changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 bank = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (data->bank != bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) outb_p(bank, data->addr + DATA_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) data->bank = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int res, word_sized = is_word_sized(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) w83627ehf_set_bank(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) res = inb_p(data->addr + DATA_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (word_sized) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) outb_p((reg & 0xff) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) data->addr + ADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int word_sized = is_word_sized(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) w83627ehf_set_bank(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (word_sized) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) outb_p((reg & 0xff) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) data->addr + ADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* We left-align 8-bit temperature values to make the code simpler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u16 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) res = w83627ehf_read_value(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!is_word_sized(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) res <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!is_word_sized(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) value >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return w83627ehf_write_value(data, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* This function assumes that the caller holds data->update_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) | ((data->fan_div[0] & 0x03) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* fan5 input control bit is write only, compute the value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) | ((data->fan_div[0] & 0x04) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) | ((data->fan_div[1] & 0x03) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* fan5 input control bit is write only, compute the value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) | ((data->fan_div[1] & 0x04) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) | ((data->fan_div[2] & 0x03) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) | ((data->fan_div[2] & 0x04) << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) | (data->fan_div[3] & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) | ((data->fan_div[3] & 0x04) << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) | ((data->fan_div[4] & 0x03) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) | ((data->fan_div[4] & 0x04) << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) data->fan_div[0] = (i >> 4) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) data->fan_div[1] = (i >> 6) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) data->fan_div[2] = (i >> 6) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) data->fan_div[0] |= (i >> 3) & 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) data->fan_div[1] |= (i >> 4) & 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) data->fan_div[2] |= (i >> 5) & 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (data->has_fan & ((1 << 3) | (1 << 4))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) data->fan_div[3] = i & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) data->fan_div[4] = ((i >> 2) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) | ((i >> 5) & 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (data->has_fan & (1 << 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) data->fan_div[3] |= (i >> 5) & 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void w83627ehf_update_pwm(struct w83627ehf_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) for (i = 0; i < data->pwm_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!(data->has_fan & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (i != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pwmcfg = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) W83627EHF_REG_PWM_ENABLE[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) tolerance = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) W83627EHF_REG_TOLERANCE[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) data->pwm_mode[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) & 3) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) data->pwm[i] = w83627ehf_read_value(data, W83627EHF_REG_PWM[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct w83627ehf_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (time_after(jiffies, data->last_updated + HZ + HZ/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) || !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Fan clock dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) w83627ehf_update_fan_div(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Measured voltages and limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) for (i = 0; i < data->in_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if ((i == 6) && data->in6_skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) data->in[i] = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) W83627EHF_REG_IN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) data->in_min[i] = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) W83627EHF_REG_IN_MIN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) data->in_max[i] = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) W83627EHF_REG_IN_MAX(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Measured fan speeds and limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!(data->has_fan & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) reg = w83627ehf_read_value(data, W83627EHF_REG_FAN[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) data->rpm[i] = fan_from_reg8(reg, data->fan_div[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (data->has_fan_min & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) data->fan_min[i] = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) W83627EHF_REG_FAN_MIN[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * If we failed to measure the fan speed and clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * divider can be increased, let's try that for next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (reg >= 0xff && data->fan_div[i] < 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "Increasing fan%d clock divider from %u to %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) i + 1, div_from_reg(data->fan_div[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) div_from_reg(data->fan_div[i] + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) data->fan_div[i]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) w83627ehf_write_fan_div(data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Preserve min limit if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if ((data->has_fan_min & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) && data->fan_min[i] >= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) && data->fan_min[i] != 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) w83627ehf_write_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) W83627EHF_REG_FAN_MIN[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) (data->fan_min[i] /= 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) w83627ehf_update_pwm(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) for (i = 0; i < data->pwm_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!(data->has_fan & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) data->fan_start_output[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) W83627EHF_REG_FAN_START_OUTPUT[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) data->fan_stop_output[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) W83627EHF_REG_FAN_STOP_OUTPUT[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) data->fan_stop_time[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) W83627EHF_REG_FAN_STOP_TIME[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (data->REG_FAN_MAX_OUTPUT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) data->REG_FAN_MAX_OUTPUT[i] != 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) data->fan_max_output[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) data->REG_FAN_MAX_OUTPUT[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (data->REG_FAN_STEP_OUTPUT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) data->REG_FAN_STEP_OUTPUT[i] != 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) data->fan_step_output[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) data->REG_FAN_STEP_OUTPUT[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) data->target_temp[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) W83627EHF_REG_TARGET[i]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Measured temperatures and limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) for (i = 0; i < NUM_REG_TEMP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!(data->have_temp & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) data->temp[i] = w83627ehf_read_temp(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) data->reg_temp[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (data->reg_temp_over[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) data->temp_max[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) = w83627ehf_read_temp(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) data->reg_temp_over[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (data->reg_temp_hyst[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) data->temp_max_hyst[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) = w83627ehf_read_temp(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) data->reg_temp_hyst[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (i > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (data->have_temp_offset & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) data->temp_offset[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) W83627EHF_REG_TEMP_OFFSET[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) data->alarms = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) W83627EHF_REG_ALARM1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) (w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) W83627EHF_REG_ALARM2) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) (w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) W83627EHF_REG_ALARM3) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) data->caseopen = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) W83627EHF_REG_CASEOPEN_DET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) data->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define store_in_reg(REG, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) store_in_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) long val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (val < 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return -EINVAL; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mutex_lock(&data->update_lock); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) data->in_##reg[channel] = in_to_reg(val, channel, data->scale_in); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(channel), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) data->in_##reg[channel]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mutex_unlock(&data->update_lock); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) store_in_reg(MIN, min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) store_in_reg(MAX, max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) store_fan_min(struct device *dev, struct w83627ehf_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u8 new_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* No min limit, alarm disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) data->fan_min[channel] = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) new_div = data->fan_div[channel]; /* No change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_info(dev, "fan%u low limit and alarm disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) channel + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) } else if ((reg = 1350000U / val) >= 128 * 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * Speed below this value cannot possibly be represented,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * even with the highest divider (128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) data->fan_min[channel] = 254;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) new_div = 7; /* 128 == (1 << 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "fan%u low limit %lu below minimum %u, set to minimum\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) channel + 1, val, fan_from_reg8(254, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } else if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * Speed above this value cannot possibly be represented,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * even with the lowest divider (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) data->fan_min[channel] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) new_div = 0; /* 1 == (1 << 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "fan%u low limit %lu above maximum %u, set to maximum\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) channel + 1, val, fan_from_reg8(1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Automatically pick the best divider, i.e. the one such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * that the min limit will correspond to a register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * in the 96..192 range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) new_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) while (reg > 192 && new_div < 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) reg >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) new_div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) data->fan_min[channel] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * Write both the fan clock divider (if it changed) and the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * fan min (unconditionally)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (new_div != data->fan_div[channel]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) channel + 1, div_from_reg(data->fan_div[channel]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) div_from_reg(new_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) data->fan_div[channel] = new_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) w83627ehf_write_fan_div(data, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Give the chip time to sample a new speed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) data->fan_min[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define store_temp_reg(addr, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) store_##reg(struct device *dev, struct w83627ehf_data *data, int channel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) long val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mutex_lock(&data->update_lock); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) data->reg[channel] = LM75_TEMP_TO_REG(val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) w83627ehf_write_temp(data, data->addr[channel], data->reg[channel]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) mutex_unlock(&data->update_lock); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) store_temp_reg(reg_temp_over, temp_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) store_temp_reg(reg_temp_hyst, temp_max_hyst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) store_temp_offset(struct device *dev, struct w83627ehf_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) data->temp_offset[channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[channel], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) store_pwm_mode(struct device *dev, struct w83627ehf_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (val < 0 || val > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) data->pwm_mode[channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) reg |= 1 << W83627EHF_PWM_MODE_SHIFT[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel], reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) store_pwm(struct device *dev, struct w83627ehf_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) val = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) data->pwm[channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) w83627ehf_write_value(data, W83627EHF_REG_PWM[channel], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) store_pwm_enable(struct device *dev, struct w83627ehf_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (!val || val < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) (val > 4 && val != data->pwm_enable_orig[channel]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) data->pwm_enable[channel] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) reg = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) W83627EHF_REG_PWM_ENABLE[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define show_tol_temp(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct sensor_device_attribute *sensor_attr = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) to_sensor_dev_attr(attr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int nr = sensor_attr->index; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) show_tol_temp(tolerance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) show_tol_temp(target_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) store_target_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct w83627ehf_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) data->target_temp[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) store_tolerance(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct w83627ehf_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Limit the temp to 0C - 15C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (nr == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) reg = (reg & 0x0f) | (val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) reg = (reg & 0xf0) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) data->tolerance[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static SENSOR_DEVICE_ATTR(pwm1_target, 0644, show_target_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) store_target_temp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static SENSOR_DEVICE_ATTR(pwm2_target, 0644, show_target_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) store_target_temp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static SENSOR_DEVICE_ATTR(pwm3_target, 0644, show_target_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) store_target_temp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static SENSOR_DEVICE_ATTR(pwm4_target, 0644, show_target_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) store_target_temp, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static SENSOR_DEVICE_ATTR(pwm1_tolerance, 0644, show_tolerance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) store_tolerance, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static SENSOR_DEVICE_ATTR(pwm2_tolerance, 0644, show_tolerance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) store_tolerance, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static SENSOR_DEVICE_ATTR(pwm3_tolerance, 0644, show_tolerance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) store_tolerance, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static SENSOR_DEVICE_ATTR(pwm4_tolerance, 0644, show_tolerance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) store_tolerance, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* Smart Fan registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define fan_functions(reg, REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct sensor_device_attribute *sensor_attr = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) to_sensor_dev_attr(attr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int nr = sensor_attr->index; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return sprintf(buf, "%d\n", data->reg[nr]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static ssize_t \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) store_##reg(struct device *dev, struct device_attribute *attr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) const char *buf, size_t count) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct w83627ehf_data *data = dev_get_drvdata(dev); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct sensor_device_attribute *sensor_attr = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) to_sensor_dev_attr(attr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) int nr = sensor_attr->index; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) unsigned long val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int err; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) err = kstrtoul(buf, 10, &val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (err < 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return err; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) val = clamp_val(val, 1, 255); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) mutex_lock(&data->update_lock); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) data->reg[nr] = val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) w83627ehf_write_value(data, REG[nr], val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) mutex_unlock(&data->update_lock); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return count; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) fan_functions(fan_start_output, W83627EHF_REG_FAN_START_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) fan_functions(fan_stop_output, W83627EHF_REG_FAN_STOP_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) fan_functions(fan_max_output, data->REG_FAN_MAX_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) fan_functions(fan_step_output, data->REG_FAN_STEP_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define fan_time_functions(reg, REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct w83627ehf_data *data = w83627ehf_update_device(dev->parent); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct sensor_device_attribute *sensor_attr = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) to_sensor_dev_attr(attr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int nr = sensor_attr->index; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return sprintf(buf, "%d\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) step_time_from_reg(data->reg[nr], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) data->pwm_mode[nr])); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static ssize_t \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) store_##reg(struct device *dev, struct device_attribute *attr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) const char *buf, size_t count) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct w83627ehf_data *data = dev_get_drvdata(dev); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct sensor_device_attribute *sensor_attr = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) to_sensor_dev_attr(attr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int nr = sensor_attr->index; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) unsigned long val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int err; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) err = kstrtoul(buf, 10, &val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (err < 0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return err; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) val = step_time_to_reg(val, data->pwm_mode[nr]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) mutex_lock(&data->update_lock); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) data->reg[nr] = val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) w83627ehf_write_value(data, REG[nr], val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) mutex_unlock(&data->update_lock); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return count; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) fan_time_functions(fan_stop_time, W83627EHF_REG_FAN_STOP_TIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static SENSOR_DEVICE_ATTR(pwm4_stop_time, 0644, show_fan_stop_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) store_fan_stop_time, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static SENSOR_DEVICE_ATTR(pwm4_start_output, 0644, show_fan_start_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) store_fan_start_output, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static SENSOR_DEVICE_ATTR(pwm4_stop_output, 0644, show_fan_stop_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) store_fan_stop_output, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static SENSOR_DEVICE_ATTR(pwm4_max_output, 0644, show_fan_max_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) store_fan_max_output, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static SENSOR_DEVICE_ATTR(pwm4_step_output, 0644, show_fan_step_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) store_fan_step_output, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static SENSOR_DEVICE_ATTR(pwm3_stop_time, 0644, show_fan_stop_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) store_fan_stop_time, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static SENSOR_DEVICE_ATTR(pwm3_start_output, 0644, show_fan_start_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) store_fan_start_output, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static SENSOR_DEVICE_ATTR(pwm3_stop_output, 0644, show_fan_stop_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) store_fan_stop_output, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static SENSOR_DEVICE_ATTR(pwm1_stop_time, 0644, show_fan_stop_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) store_fan_stop_time, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static SENSOR_DEVICE_ATTR(pwm2_stop_time, 0644, show_fan_stop_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) store_fan_stop_time, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static SENSOR_DEVICE_ATTR(pwm1_start_output, 0644, show_fan_start_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) store_fan_start_output, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static SENSOR_DEVICE_ATTR(pwm2_start_output, 0644, show_fan_start_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) store_fan_start_output, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static SENSOR_DEVICE_ATTR(pwm1_stop_output, 0644, show_fan_stop_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) store_fan_stop_output, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static SENSOR_DEVICE_ATTR(pwm2_stop_output, 0644, show_fan_stop_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) store_fan_stop_output, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * pwm1 and pwm3 don't support max and step settings on all chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Need to check support while generating/removing attribute files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static SENSOR_DEVICE_ATTR(pwm1_max_output, 0644, show_fan_max_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) store_fan_max_output, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static SENSOR_DEVICE_ATTR(pwm1_step_output, 0644, show_fan_step_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) store_fan_step_output, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static SENSOR_DEVICE_ATTR(pwm2_max_output, 0644, show_fan_max_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) store_fan_max_output, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static SENSOR_DEVICE_ATTR(pwm2_step_output, 0644, show_fan_step_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) store_fan_step_output, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static SENSOR_DEVICE_ATTR(pwm3_max_output, 0644, show_fan_max_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) store_fan_max_output, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static SENSOR_DEVICE_ATTR(pwm3_step_output, 0644, show_fan_step_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) store_fan_step_output, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct w83627ehf_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) DEVICE_ATTR_RO(cpu0_vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* Case open detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) clear_caseopen(struct device *dev, struct w83627ehf_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) const u16 mask = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (val != 0 || channel != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) data->valid = 0; /* Force cache refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static umode_t w83627ehf_attrs_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct attribute *a, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct device *dev = container_of(kobj, struct device, kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct w83627ehf_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct device_attribute *devattr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct sensor_device_attribute *sda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) devattr = container_of(a, struct device_attribute, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Not sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (devattr->show == cpu0_vid_show && data->have_vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return a->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) sda = (struct sensor_device_attribute *)devattr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (sda->index < 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) (devattr->show == show_fan_stop_time ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) devattr->show == show_fan_start_output ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) devattr->show == show_fan_stop_output))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return a->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (sda->index < 3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) (devattr->show == show_fan_max_output ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) devattr->show == show_fan_step_output) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) data->REG_FAN_STEP_OUTPUT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) data->REG_FAN_STEP_OUTPUT[sda->index] != 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return a->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* if fan3 and fan4 are enabled create the files for them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (sda->index == 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) (data->has_fan & (1 << 2)) && data->pwm_num >= 3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) (devattr->show == show_fan_stop_time ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) devattr->show == show_fan_start_output ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) devattr->show == show_fan_stop_output))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return a->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (sda->index == 3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) (data->has_fan & (1 << 3)) && data->pwm_num >= 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) (devattr->show == show_fan_stop_time ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) devattr->show == show_fan_start_output ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) devattr->show == show_fan_stop_output ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) devattr->show == show_fan_max_output ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) devattr->show == show_fan_step_output))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return a->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if ((devattr->show == show_target_temp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) devattr->show == show_tolerance) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) (data->has_fan & (1 << sda->index)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) sda->index < data->pwm_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return a->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* These groups handle non-standard attributes used in this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static struct attribute *w83627ehf_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) &sensor_dev_attr_pwm1_stop_time.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) &sensor_dev_attr_pwm1_start_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) &sensor_dev_attr_pwm1_stop_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) &sensor_dev_attr_pwm1_max_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) &sensor_dev_attr_pwm1_step_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) &sensor_dev_attr_pwm1_target.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) &sensor_dev_attr_pwm1_tolerance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) &sensor_dev_attr_pwm2_stop_time.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) &sensor_dev_attr_pwm2_start_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) &sensor_dev_attr_pwm2_stop_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) &sensor_dev_attr_pwm2_max_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) &sensor_dev_attr_pwm2_step_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) &sensor_dev_attr_pwm2_target.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) &sensor_dev_attr_pwm2_tolerance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) &sensor_dev_attr_pwm3_stop_time.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) &sensor_dev_attr_pwm3_start_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) &sensor_dev_attr_pwm3_stop_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) &sensor_dev_attr_pwm3_max_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) &sensor_dev_attr_pwm3_step_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) &sensor_dev_attr_pwm3_target.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) &sensor_dev_attr_pwm3_tolerance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) &sensor_dev_attr_pwm4_stop_time.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) &sensor_dev_attr_pwm4_start_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) &sensor_dev_attr_pwm4_stop_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) &sensor_dev_attr_pwm4_max_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) &sensor_dev_attr_pwm4_step_output.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) &sensor_dev_attr_pwm4_target.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) &sensor_dev_attr_pwm4_tolerance.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) &dev_attr_cpu0_vid.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static const struct attribute_group w83627ehf_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .attrs = w83627ehf_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .is_visible = w83627ehf_attrs_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static const struct attribute_group *w83627ehf_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) &w83627ehf_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * Driver and device management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* Get the monitoring functions started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static inline void w83627ehf_init_device(struct w83627ehf_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) enum kinds kind)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) u8 tmp, diode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* Start monitoring is needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (!(tmp & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) tmp | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* Enable temperature sensors if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) for (i = 0; i < NUM_REG_TEMP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (!(data->have_temp & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (!data->reg_temp_config[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) tmp = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) data->reg_temp_config[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (tmp & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) w83627ehf_write_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) data->reg_temp_config[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) tmp & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Enable VBAT monitoring if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (!(tmp & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* Get thermal sensor types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) switch (kind) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) case w83627ehf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) case w83627uhg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) diode = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) diode = 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) const char *label = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (data->temp_label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) label = data->temp_label[data->temp_src[i]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* Digital source overrides analog type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (label && strncmp(label, "PECI", 4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) data->temp_type[i] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) else if (label && strncmp(label, "AMD", 3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) data->temp_type[i] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) else if ((tmp & (0x02 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) data->temp_type[i] = 4; /* thermistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) for (i = 0; i < n_temp; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) data->reg_temp[i] = W83627EHF_REG_TEMP[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct w83627ehf_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) int fan3pin, fan4pin, fan5pin, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* The W83627UHG is simple, only two fan inputs, no config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (sio_data->kind == w83627uhg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) data->has_fan = 0x03; /* fan1 and fan2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) data->has_fan_min = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* fan4 and fan5 share some pins with the GPIO and serial flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) fan3pin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) fan3pin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) data->has_fan |= (fan3pin << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) data->has_fan_min |= (fan3pin << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * It looks like fan4 and fan5 pins can be alternatively used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * as fan on/off switches, but fan5 control is write only :/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * We assume that if the serial interface is disabled, designers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * connected fan5 as input unless they are emitting log 1, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * is not the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if ((regval & (1 << 2)) && fan4pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) data->has_fan |= (1 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) data->has_fan_min |= (1 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (!(regval & (1 << 1)) && fan5pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) data->has_fan |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) data->has_fan_min |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static umode_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) w83627ehf_is_visible(const void *drvdata, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) const struct w83627ehf_data *data = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* channel 0.., name 1.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (!(data->have_temp & (1 << channel)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (attr == hwmon_temp_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (attr == hwmon_temp_label) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (data->temp_label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (channel == 2 && data->temp3_val_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (attr == hwmon_temp_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (data->reg_temp_over[channel])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (attr == hwmon_temp_max_hyst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (data->reg_temp_hyst[channel])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (channel > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (attr == hwmon_temp_alarm || attr == hwmon_temp_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (attr == hwmon_temp_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (data->have_temp_offset & (1 << channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) case hwmon_fan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* channel 0.., name 1.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (!(data->has_fan & (1 << channel)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (attr == hwmon_fan_input || attr == hwmon_fan_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (attr == hwmon_fan_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (attr == hwmon_fan_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (data->has_fan_min & (1 << channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* channel 0.., name 0.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (channel >= data->in_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (channel == 6 && data->in6_skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (attr == hwmon_in_alarm || attr == hwmon_in_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (attr == hwmon_in_min || attr == hwmon_in_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) case hwmon_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* channel 0.., name 1.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (!(data->has_fan & (1 << channel)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) channel >= data->pwm_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (attr == hwmon_pwm_mode || attr == hwmon_pwm_enable ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) attr == hwmon_pwm_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) case hwmon_intrusion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) default: /* Shouldn't happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return 0; /* Shouldn't happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) w83627ehf_do_read_temp(struct w83627ehf_data *data, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) *val = LM75_TEMP_FROM_REG(data->temp[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) *val = LM75_TEMP_FROM_REG(data->temp_max[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) case hwmon_temp_max_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) *val = LM75_TEMP_FROM_REG(data->temp_max_hyst[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) *val = data->temp_offset[channel] * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) case hwmon_temp_type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) *val = (int)data->temp_type[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) case hwmon_temp_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (channel < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) int bit[] = { 4, 5, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) *val = (data->alarms >> bit[channel]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) w83627ehf_do_read_in(struct w83627ehf_data *data, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) case hwmon_in_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) *val = in_from_reg(data->in[channel], channel, data->scale_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) case hwmon_in_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) *val = in_from_reg(data->in_min[channel], channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) data->scale_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) case hwmon_in_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) *val = in_from_reg(data->in_max[channel], channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) data->scale_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) case hwmon_in_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (channel < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) int bit[] = { 0, 1, 2, 3, 8, 21, 20, 16, 17, 19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) *val = (data->alarms >> bit[channel]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) w83627ehf_do_read_fan(struct w83627ehf_data *data, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) case hwmon_fan_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) *val = data->rpm[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) case hwmon_fan_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) *val = fan_from_reg8(data->fan_min[channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) data->fan_div[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) case hwmon_fan_div:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) *val = div_from_reg(data->fan_div[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) case hwmon_fan_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (channel < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) int bit[] = { 6, 7, 11, 10, 23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) *val = (data->alarms >> bit[channel]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) w83627ehf_do_read_pwm(struct w83627ehf_data *data, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) case hwmon_pwm_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) *val = data->pwm[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) case hwmon_pwm_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) *val = data->pwm_enable[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) case hwmon_pwm_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) *val = data->pwm_enable[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) w83627ehf_do_read_intrusion(struct w83627ehf_data *data, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if (attr != hwmon_intrusion_alarm || channel != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) return -EOPNOTSUPP; /* shouldn't happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) *val = !!(data->caseopen & 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) w83627ehf_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) struct w83627ehf_data *data = w83627ehf_update_device(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) case hwmon_fan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return w83627ehf_do_read_fan(data, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return w83627ehf_do_read_in(data, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) case hwmon_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) return w83627ehf_do_read_pwm(data, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return w83627ehf_do_read_temp(data, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) case hwmon_intrusion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return w83627ehf_do_read_intrusion(data, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) w83627ehf_read_string(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) u32 attr, int channel, const char **str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct w83627ehf_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (attr == hwmon_temp_label) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) *str = data->temp_label[data->temp_src[channel]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* Nothing else should be read as a string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) w83627ehf_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct w83627ehf_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (type == hwmon_in && attr == hwmon_in_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return store_in_min(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (type == hwmon_in && attr == hwmon_in_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return store_in_max(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (type == hwmon_fan && attr == hwmon_fan_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return store_fan_min(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (type == hwmon_temp && attr == hwmon_temp_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return store_temp_max(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (type == hwmon_temp && attr == hwmon_temp_max_hyst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) return store_temp_max_hyst(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (type == hwmon_temp && attr == hwmon_temp_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return store_temp_offset(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (type == hwmon_pwm && attr == hwmon_pwm_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return store_pwm_mode(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (type == hwmon_pwm && attr == hwmon_pwm_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return store_pwm_enable(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (type == hwmon_pwm && attr == hwmon_pwm_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return store_pwm(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (type == hwmon_intrusion && attr == hwmon_intrusion_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return clear_caseopen(dev, data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static const struct hwmon_ops w83627ehf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .is_visible = w83627ehf_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .read = w83627ehf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .read_string = w83627ehf_read_string,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .write = w83627ehf_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static const struct hwmon_channel_info *w83627ehf_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) HWMON_CHANNEL_INFO(fan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) HWMON_F_ALARM | HWMON_F_DIV | HWMON_F_INPUT | HWMON_F_MIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) HWMON_CHANNEL_INFO(in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) HWMON_I_ALARM | HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_MIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) HWMON_CHANNEL_INFO(pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) HWMON_PWM_ENABLE | HWMON_PWM_INPUT | HWMON_PWM_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) HWMON_T_ALARM | HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) HWMON_T_MAX_HYST | HWMON_T_OFFSET | HWMON_T_TYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) HWMON_CHANNEL_INFO(intrusion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) HWMON_INTRUSION_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static const struct hwmon_chip_info w83627ehf_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .ops = &w83627ehf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .info = w83627ehf_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static int w83627ehf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct w83627ehf_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) u8 en_vrm10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) int i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) (unsigned long)res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) (unsigned long)res->start + IOREGION_LENGTH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) goto exit_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) data->addr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) data->name = w83627ehf_device_names[sio_data->kind];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) data->bank = 0xff; /* Force initial bank selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) /* 667HG has 3 pwms, and 627UHG has only 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) switch (sio_data->kind) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) data->pwm_num = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) case w83667hg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) case w83667hg_b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) data->pwm_num = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) case w83627uhg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) data->pwm_num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* Default to 3 temperature inputs, code below will adjust as needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) data->have_temp = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* Deal with temperature register setup first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (sio_data->kind == w83667hg_b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) w83627ehf_set_temp_reg_ehf(data, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * Temperature sources are selected with bank 0, registers 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * and 0x4a.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) reg = w83627ehf_read_value(data, 0x4a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) data->temp_src[0] = reg >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) reg = w83627ehf_read_value(data, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) data->temp_src[1] = reg & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) data->temp_src[2] = (reg >> 4) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * W83667HG-B has another temperature register at 0x7e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * The temperature source is selected with register 0x7d.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) * Support it if the source differs from already reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) reg = w83627ehf_read_value(data, 0x7d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) reg &= 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (reg != data->temp_src[0] && reg != data->temp_src[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) && reg != data->temp_src[2]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) data->temp_src[3] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) data->have_temp |= 1 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) * Chip supports either AUXTIN or VIN3. Try to find out which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) * one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (data->temp_src[2] == 2 && (reg & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) data->have_temp &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) data->in6_skip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) data->temp_label = w83667hg_b_temp_label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) data->have_temp_offset = data->have_temp & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (data->temp_src[i] > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) data->have_temp_offset &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) } else if (sio_data->kind == w83627uhg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) w83627ehf_set_temp_reg_ehf(data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) * Temperature sources for temp2 and temp3 are selected with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * bank 0, registers 0x49 and 0x4a.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) data->temp_src[0] = 0; /* SYSTIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) reg = w83627ehf_read_value(data, 0x49) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) /* Adjust to have the same mapping as other source registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (reg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) data->temp_src[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) else if (reg >= 2 && reg <= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) data->temp_src[1] = reg + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) else /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) data->have_temp &= ~(1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) reg = w83627ehf_read_value(data, 0x4a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) data->temp_src[2] = reg >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) * Skip temp3 if source is invalid or the same as temp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * or temp2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) data->temp_src[2] == data->temp_src[0] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ((data->have_temp & (1 << 1)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) data->temp_src[2] == data->temp_src[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) data->have_temp &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) data->temp3_val_only = 1; /* No limit regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) data->in6_skip = 1; /* No VIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) data->temp_label = w83667hg_b_temp_label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) data->have_temp_offset = data->have_temp & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (data->temp_src[i] > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) data->have_temp_offset &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) w83627ehf_set_temp_reg_ehf(data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* Temperature sources are fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (sio_data->kind == w83667hg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * Chip supports either AUXTIN or VIN3. Try to find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * out which one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) reg = w83627ehf_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) W83627EHF_REG_TEMP_CONFIG[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (reg & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) data->have_temp &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) data->in6_skip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) data->have_temp_offset = data->have_temp & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (sio_data->kind == w83667hg_b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) data->REG_FAN_MAX_OUTPUT =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) data->REG_FAN_STEP_OUTPUT =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) data->REG_FAN_MAX_OUTPUT =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) data->REG_FAN_STEP_OUTPUT =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /* Setup input voltage scaling factors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (sio_data->kind == w83627uhg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) data->scale_in = scale_in_w83627uhg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) data->scale_in = scale_in_common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /* Initialize the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) w83627ehf_init_device(data, sio_data->kind);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) data->vrm = vid_which_vrm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) err = superio_enter(sio_data->sioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) goto exit_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* Read VID value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) * W83667HG has different pins for VID input and output, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) * we can get the VID input values directly at logical device D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) * 0xe3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) superio_select(sio_data->sioreg, W83667HG_LD_VID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) data->vid = superio_inb(sio_data->sioreg, 0xe3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) data->have_vid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) } else if (sio_data->kind != w83627uhg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * Set VID input sensibility if needed. In theory the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) * BIOS should have set it, but in practice it's not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * always the case. We only do it for the W83627EHF/EHG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * because the W83627DHG is more complex in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * respect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (sio_data->kind == w83627ehf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) en_vrm10 = superio_inb(sio_data->sioreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) SIO_REG_EN_VRM10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if ((en_vrm10 & 0x08) && data->vrm == 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) "Setting VID input voltage to TTL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) superio_outb(sio_data->sioreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) SIO_REG_EN_VRM10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) en_vrm10 & ~0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) } else if (!(en_vrm10 & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) && data->vrm == 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) "Setting VID input voltage to VRM10\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) superio_outb(sio_data->sioreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) SIO_REG_EN_VRM10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) en_vrm10 | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) data->vid = superio_inb(sio_data->sioreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) SIO_REG_VID_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (sio_data->kind == w83627ehf) /* 6 VID pins only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) data->vid &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) data->have_vid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) "VID pins in output mode, CPU VID not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) w83627ehf_check_fan_inputs(sio_data, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) superio_exit(sio_data->sioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /* Read fan clock dividers immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) w83627ehf_update_fan_div(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) /* Read pwm data to save original values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) w83627ehf_update_pwm(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) for (i = 0; i < data->pwm_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) data->pwm_enable_orig[i] = data->pwm_enable[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) &w83627ehf_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) w83627ehf_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (IS_ERR(hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) err = PTR_ERR(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) goto exit_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) exit_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) release_region(res->start, IOREGION_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) static int w83627ehf_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) struct w83627ehf_data *data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) release_region(data->addr, IOREGION_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static int w83627ehf_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) struct w83627ehf_data *data = w83627ehf_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) data->vbat = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static int w83627ehf_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) struct w83627ehf_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) data->bank = 0xff; /* Force initial bank selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) /* Restore limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) for (i = 0; i < data->in_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if ((i == 6) && data->in6_skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) data->in_min[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) data->in_max[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (!(data->has_fan_min & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) data->fan_min[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) for (i = 0; i < NUM_REG_TEMP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (!(data->have_temp & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (data->reg_temp_over[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) w83627ehf_write_temp(data, data->reg_temp_over[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) data->temp_max[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (data->reg_temp_hyst[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) w83627ehf_write_temp(data, data->reg_temp_hyst[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) data->temp_max_hyst[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (i > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (data->have_temp_offset & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) w83627ehf_write_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) W83627EHF_REG_TEMP_OFFSET[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) data->temp_offset[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) /* Restore other settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) /* Force re-reading all values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) data->valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static const struct dev_pm_ops w83627ehf_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .suspend = w83627ehf_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .resume = w83627ehf_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .freeze = w83627ehf_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .restore = w83627ehf_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define W83627EHF_DEV_PM_OPS (&w83627ehf_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) #define W83627EHF_DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static struct platform_driver w83627ehf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .name = DRVNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .pm = W83627EHF_DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .probe = w83627ehf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .remove = w83627ehf_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* w83627ehf_find() looks for a '627 in the Super-I/O config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) struct w83627ehf_sio_data *sio_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) static const char sio_name_W83667HG[] __initconst = "W83667HG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) const char *sio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) err = superio_enter(sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (force_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) val = force_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) | superio_inb(sioaddr, SIO_REG_DEVID + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) switch (val & SIO_ID_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) case SIO_W83627EHF_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) sio_data->kind = w83627ehf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) sio_name = sio_name_W83627EHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) case SIO_W83627EHG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) sio_data->kind = w83627ehf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) sio_name = sio_name_W83627EHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) case SIO_W83627DHG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) sio_data->kind = w83627dhg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) sio_name = sio_name_W83627DHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) case SIO_W83627DHG_P_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) sio_data->kind = w83627dhg_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) sio_name = sio_name_W83627DHG_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) case SIO_W83627UHG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) sio_data->kind = w83627uhg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) sio_name = sio_name_W83627UHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) case SIO_W83667HG_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) sio_data->kind = w83667hg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) sio_name = sio_name_W83667HG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) case SIO_W83667HG_B_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) sio_data->kind = w83667hg_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) sio_name = sio_name_W83667HG_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (val != 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) pr_debug("unsupported chip ID: 0x%04x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) superio_exit(sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /* We have a known chip, find the HWM I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) superio_select(sioaddr, W83627EHF_LD_HWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) | superio_inb(sioaddr, SIO_REG_ADDR + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) *addr = val & IOREGION_ALIGNMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (*addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) superio_exit(sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /* Activate logical device if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) val = superio_inb(sioaddr, SIO_REG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (!(val & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) superio_exit(sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) pr_info("Found %s chip at %#x\n", sio_name, *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) sio_data->sioreg = sioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) * when Super-I/O functions move to a separate file, the Super-I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) * bus will manage the lifetime of the device and this module will only keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) * track of the w83627ehf driver. But since we platform_device_alloc(), we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) * must keep track of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) static struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static int __init sensors_w83627ehf_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) unsigned short address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) struct w83627ehf_sio_data sio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) * initialize sio_data->kind and sio_data->sioreg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) * when Super-I/O functions move to a separate file, the Super-I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) * driver will probe 0x2e and 0x4e and auto-detect the presence of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) * w83627ehf hardware monitor, and call probe()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) if (w83627ehf_find(0x2e, &address, &sio_data) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) w83627ehf_find(0x4e, &address, &sio_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) err = platform_driver_register(&w83627ehf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) pdev = platform_device_alloc(DRVNAME, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) pr_err("Device allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) goto exit_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) err = platform_device_add_data(pdev, &sio_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) sizeof(struct w83627ehf_sio_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) pr_err("Platform data allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) memset(&res, 0, sizeof(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) res.name = DRVNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) res.start = address + IOREGION_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) res.flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) err = acpi_check_resource_conflict(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) err = platform_device_add_resources(pdev, &res, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) pr_err("Device resource addition failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) /* platform_device_add calls probe() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) err = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) pr_err("Device addition failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) exit_device_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) exit_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) platform_driver_unregister(&w83627ehf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static void __exit sensors_w83627ehf_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) platform_device_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) platform_driver_unregister(&w83627ehf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) MODULE_DESCRIPTION("W83627EHF driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) module_init(sensors_w83627ehf_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) module_exit(sensors_w83627ehf_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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