Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for Texas Instruments TMP512, TMP513 power monitor chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * TMP513:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Thermal/Power Management with Triple Remote and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Local Temperature Sensor and Current Shunt Monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Datasheet: https://www.ti.com/lit/gpn/tmp513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * TMP512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Thermal/Power Management with Dual Remote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *	and Local Temperature Sensor and Current Shunt Monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Datasheet: https://www.ti.com/lit/gpn/tmp512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Copyright (C) 2019 Eric Tremblay <etremblay@distech-controls.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/util_macros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) // Common register definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TMP51X_SHUNT_CONFIG		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TMP51X_TEMP_CONFIG		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TMP51X_STATUS			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TMP51X_SMBUS_ALERT		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TMP51X_SHUNT_CURRENT_RESULT	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TMP51X_BUS_VOLTAGE_RESULT	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TMP51X_POWER_RESULT		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TMP51X_BUS_CURRENT_RESULT	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TMP51X_LOCAL_TEMP_RESULT	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TMP51X_REMOTE_TEMP_RESULT_1	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TMP51X_REMOTE_TEMP_RESULT_2	0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TMP51X_SHUNT_CURRENT_H_LIMIT	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TMP51X_SHUNT_CURRENT_L_LIMIT	0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TMP51X_BUS_VOLTAGE_H_LIMIT	0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TMP51X_BUS_VOLTAGE_L_LIMIT	0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TMP51X_POWER_LIMIT		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TMP51X_LOCAL_TEMP_LIMIT	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TMP51X_REMOTE_TEMP_LIMIT_1	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TMP51X_REMOTE_TEMP_LIMIT_2	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TMP51X_SHUNT_CALIBRATION	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TMP51X_N_FACTOR_AND_HYST_1	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TMP51X_N_FACTOR_2		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TMP51X_MAN_ID_REG		0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TMP51X_DEVICE_ID_REG		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) // TMP513 specific register definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TMP513_REMOTE_TEMP_RESULT_3	0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TMP513_REMOTE_TEMP_LIMIT_3	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TMP513_N_FACTOR_3		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) // Common attrs, and NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define TMP51X_MANUFACTURER_ID		0x55FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TMP512_DEVICE_ID		0x22FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TMP513_DEVICE_ID		0x23FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) // Default config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TMP51X_SHUNT_CONFIG_DEFAULT	0x399F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TMP51X_SHUNT_VALUE_DEFAULT	1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TMP51X_VBUS_RANGE_DEFAULT	TMP51X_VBUS_RANGE_32V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TMP51X_PGA_DEFAULT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define TMP51X_MAX_REGISTER_ADDR	0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TMP512_TEMP_CONFIG_DEFAULT	0xBF80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define TMP513_TEMP_CONFIG_DEFAULT	0xFF80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) // Mask and shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CURRENT_SENSE_VOLTAGE_320_MASK	0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CURRENT_SENSE_VOLTAGE_160_MASK	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CURRENT_SENSE_VOLTAGE_80_MASK	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CURRENT_SENSE_VOLTAGE_40_MASK	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define TMP51X_BUS_VOLTAGE_MASK		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TMP51X_NFACTOR_MASK		0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TMP51X_HYST_MASK		0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TMP51X_BUS_VOLTAGE_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TMP51X_TEMP_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) // Alarms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TMP51X_SHUNT_CURRENT_H_LIMIT_POS	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TMP51X_SHUNT_CURRENT_L_LIMIT_POS	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TMP51X_BUS_VOLTAGE_H_LIMIT_POS		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TMP51X_BUS_VOLTAGE_L_LIMIT_POS		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TMP51X_POWER_LIMIT_POS			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TMP51X_LOCAL_TEMP_LIMIT_POS		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define TMP51X_REMOTE_TEMP_LIMIT_1_POS		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TMP51X_REMOTE_TEMP_LIMIT_2_POS		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TMP513_REMOTE_TEMP_LIMIT_3_POS		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TMP51X_VBUS_RANGE_32V		32000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TMP51X_VBUS_RANGE_16V		16000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) // Max and Min value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MAX_BUS_VOLTAGE_32_LIMIT	32764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MAX_BUS_VOLTAGE_16_LIMIT	16382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) // Max possible value is -256 to +256 but datasheet indicated -40 to 125.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MAX_TEMP_LIMIT			125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MIN_TEMP_LIMIT			-40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MAX_TEMP_HYST			127500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const u8 TMP51X_TEMP_INPUT[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	TMP51X_LOCAL_TEMP_RESULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	TMP51X_REMOTE_TEMP_RESULT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	TMP51X_REMOTE_TEMP_RESULT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	TMP513_REMOTE_TEMP_RESULT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const u8 TMP51X_TEMP_CRIT[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	TMP51X_LOCAL_TEMP_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	TMP51X_REMOTE_TEMP_LIMIT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	TMP51X_REMOTE_TEMP_LIMIT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	TMP513_REMOTE_TEMP_LIMIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const u8 TMP51X_TEMP_CRIT_ALARM[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	TMP51X_LOCAL_TEMP_LIMIT_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	TMP51X_REMOTE_TEMP_LIMIT_1_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	TMP51X_REMOTE_TEMP_LIMIT_2_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	TMP513_REMOTE_TEMP_LIMIT_3_POS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const u8 TMP51X_TEMP_CRIT_HYST[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	TMP51X_N_FACTOR_AND_HYST_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	TMP51X_N_FACTOR_AND_HYST_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	TMP51X_N_FACTOR_AND_HYST_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	TMP51X_N_FACTOR_AND_HYST_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const u8 TMP51X_CURR_INPUT[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	TMP51X_SHUNT_CURRENT_RESULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	TMP51X_BUS_CURRENT_RESULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct regmap_config tmp51x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.max_register = TMP51X_MAX_REGISTER_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) enum tmp51x_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	tmp512, tmp513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct tmp51x_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u16 shunt_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u16 pga_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u32 vbus_range_uvolt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u16 temp_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u32 nfactor[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 shunt_uohms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u32 curr_lsb_ua;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 pwr_lsb_uw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	enum tmp51x_ids id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) // Set the shift based on the gain 8=4, 4=3, 2=2, 1=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline u8 tmp51x_get_pga_shift(struct tmp51x_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return 5 - ffs(data->pga_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int tmp51x_get_value(struct tmp51x_data *data, u8 reg, u8 pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			    unsigned int regval, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	case TMP51X_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		*val = (regval >> pos) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	case TMP51X_SHUNT_CURRENT_RESULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	case TMP51X_SHUNT_CURRENT_H_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case TMP51X_SHUNT_CURRENT_L_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		 * The valus is read in voltage in the chip but reported as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		 * current to the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		 * 2's complement number shifted by one to four depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		 * on the pga gain setting. 1lsb = 10uV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		*val = sign_extend32(regval, 17 - tmp51x_get_pga_shift(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		*val = DIV_ROUND_CLOSEST(*val * 10000, data->shunt_uohms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case TMP51X_BUS_VOLTAGE_RESULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case TMP51X_BUS_VOLTAGE_H_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	case TMP51X_BUS_VOLTAGE_L_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		// 1lsb = 4mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		*val = (regval >> TMP51X_BUS_VOLTAGE_SHIFT) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case TMP51X_POWER_RESULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	case TMP51X_POWER_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		// Power = (current * BusVoltage) / 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		*val = regval * data->pwr_lsb_uw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case TMP51X_BUS_CURRENT_RESULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		// Current = (ShuntVoltage * CalibrationRegister) / 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		*val = sign_extend32(regval, 16) * data->curr_lsb_ua;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		*val = DIV_ROUND_CLOSEST(*val, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case TMP51X_LOCAL_TEMP_RESULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case TMP51X_REMOTE_TEMP_RESULT_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case TMP51X_REMOTE_TEMP_RESULT_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case TMP513_REMOTE_TEMP_RESULT_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case TMP51X_LOCAL_TEMP_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	case TMP51X_REMOTE_TEMP_LIMIT_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	case TMP51X_REMOTE_TEMP_LIMIT_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	case TMP513_REMOTE_TEMP_LIMIT_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		// 1lsb = 0.0625 degrees centigrade
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		*val = sign_extend32(regval, 16) >> TMP51X_TEMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		*val = DIV_ROUND_CLOSEST(*val * 625, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	case TMP51X_N_FACTOR_AND_HYST_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		// 1lsb = 0.5 degrees centigrade
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		*val = (regval & TMP51X_HYST_MASK) * 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		// Programmer goofed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int tmp51x_set_value(struct tmp51x_data *data, u8 reg, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	int regval, max_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	case TMP51X_SHUNT_CURRENT_H_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	case TMP51X_SHUNT_CURRENT_L_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		 * The user enter current value and we convert it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		 * voltage. 1lsb = 10uV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		val = DIV_ROUND_CLOSEST(val * data->shunt_uohms, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		max_val = U16_MAX >> tmp51x_get_pga_shift(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		regval = clamp_val(val, -max_val, max_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case TMP51X_BUS_VOLTAGE_H_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	case TMP51X_BUS_VOLTAGE_L_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		// 1lsb = 4mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		max_val = (data->vbus_range_uvolt == TMP51X_VBUS_RANGE_32V) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			MAX_BUS_VOLTAGE_32_LIMIT : MAX_BUS_VOLTAGE_16_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		val = clamp_val(DIV_ROUND_CLOSEST(val, 4), 0, max_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		regval = val << TMP51X_BUS_VOLTAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case TMP51X_POWER_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		regval = clamp_val(DIV_ROUND_CLOSEST(val, data->pwr_lsb_uw), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				   U16_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	case TMP51X_LOCAL_TEMP_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case TMP51X_REMOTE_TEMP_LIMIT_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	case TMP51X_REMOTE_TEMP_LIMIT_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	case TMP513_REMOTE_TEMP_LIMIT_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		// 1lsb = 0.0625 degrees centigrade
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		val = clamp_val(val, MIN_TEMP_LIMIT, MAX_TEMP_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		regval = DIV_ROUND_CLOSEST(val * 10, 625) << TMP51X_TEMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	case TMP51X_N_FACTOR_AND_HYST_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		// 1lsb = 0.5 degrees centigrade
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		val = clamp_val(val, 0, MAX_TEMP_HYST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		regval = DIV_ROUND_CLOSEST(val, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		mask = TMP51X_HYST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		// Programmer goofed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return regmap_write(data->regmap, reg, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		return regmap_update_bits(data->regmap, reg, mask, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static u8 tmp51x_get_reg(enum hwmon_sensor_types type, u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			return TMP51X_TEMP_INPUT[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			return TMP51X_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			return TMP51X_TEMP_CRIT[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		case hwmon_temp_crit_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			return TMP51X_TEMP_CRIT_HYST[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		case hwmon_in_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			return TMP51X_BUS_VOLTAGE_RESULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		case hwmon_in_lcrit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		case hwmon_in_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			return TMP51X_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		case hwmon_in_lcrit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			return TMP51X_BUS_VOLTAGE_L_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		case hwmon_in_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			return TMP51X_BUS_VOLTAGE_H_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	case hwmon_curr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		case hwmon_curr_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			return TMP51X_CURR_INPUT[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		case hwmon_curr_lcrit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		case hwmon_curr_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			return TMP51X_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		case hwmon_curr_lcrit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			return TMP51X_SHUNT_CURRENT_L_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		case hwmon_curr_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			return TMP51X_SHUNT_CURRENT_H_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	case hwmon_power:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		case hwmon_power_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			return TMP51X_POWER_RESULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		case hwmon_power_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			return TMP51X_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		case hwmon_power_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			return TMP51X_POWER_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static u8 tmp51x_get_status_pos(enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			return TMP51X_TEMP_CRIT_ALARM[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		case hwmon_in_lcrit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			return TMP51X_BUS_VOLTAGE_L_LIMIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		case hwmon_in_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			return TMP51X_BUS_VOLTAGE_H_LIMIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	case hwmon_curr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		case hwmon_curr_lcrit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			return TMP51X_SHUNT_CURRENT_L_LIMIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		case hwmon_curr_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			return TMP51X_SHUNT_CURRENT_H_LIMIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	case hwmon_power:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		case hwmon_power_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 			return TMP51X_POWER_LIMIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int tmp51x_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		       u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	struct tmp51x_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	u8 pos = 0, reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	reg = tmp51x_get_reg(type, attr, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	if (reg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	if (reg == TMP51X_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		pos = tmp51x_get_status_pos(type, attr, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	ret = regmap_read(data->regmap, reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return tmp51x_get_value(data, reg, pos, regval, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int tmp51x_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	reg = tmp51x_get_reg(type, attr, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	if (reg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	return tmp51x_set_value(dev_get_drvdata(dev), reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static umode_t tmp51x_is_visible(const void *_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 				 enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 				 int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	const struct tmp51x_data *data = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		if (data->id == tmp512 && channel == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		case hwmon_temp_crit_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 			if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 				return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		case hwmon_in_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		case hwmon_in_lcrit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		case hwmon_in_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		case hwmon_in_lcrit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		case hwmon_in_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	case hwmon_curr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		if (!data->shunt_uohms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		case hwmon_curr_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		case hwmon_curr_lcrit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		case hwmon_curr_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		case hwmon_curr_lcrit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		case hwmon_curr_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	case hwmon_power:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		if (!data->shunt_uohms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		case hwmon_power_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		case hwmon_power_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		case hwmon_power_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct hwmon_channel_info *tmp51x_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 			   HWMON_T_CRIT_HYST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 			   HWMON_T_CRIT_HYST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 			   HWMON_T_CRIT_HYST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 			   HWMON_T_CRIT_HYST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	HWMON_CHANNEL_INFO(in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 			   HWMON_I_INPUT | HWMON_I_LCRIT | HWMON_I_LCRIT_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 			   HWMON_I_CRIT | HWMON_I_CRIT_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	HWMON_CHANNEL_INFO(curr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 			   HWMON_C_INPUT | HWMON_C_LCRIT | HWMON_C_LCRIT_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 			   HWMON_C_CRIT | HWMON_C_CRIT_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 			   HWMON_C_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	HWMON_CHANNEL_INFO(power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 			   HWMON_P_INPUT | HWMON_P_CRIT | HWMON_P_CRIT_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct hwmon_ops tmp51x_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	.is_visible = tmp51x_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	.read = tmp51x_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	.write = tmp51x_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const struct hwmon_chip_info tmp51x_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	.ops = &tmp51x_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	.info = tmp51x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)  * Calibrate the tmp51x following the datasheet method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int tmp51x_calibrate(struct tmp51x_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	int vshunt_max = data->pga_gain * 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	u64 max_curr_ma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	 * If shunt_uohms is equal to 0, the calibration should be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	 * The consequence will be that the current and power measurement engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	 * of the sensor will not work. Temperature and voltage sensing will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	 * continue to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	if (data->shunt_uohms == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 		return regmap_write(data->regmap, TMP51X_SHUNT_CALIBRATION, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	max_curr_ma = DIV_ROUND_CLOSEST_ULL(vshunt_max * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 					    data->shunt_uohms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	 * Calculate the minimal bit resolution for the current and the power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	 * Those values will be used during register interpretation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	data->curr_lsb_ua = DIV_ROUND_CLOSEST_ULL(max_curr_ma * 1000, 32767);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	data->pwr_lsb_uw = 20 * data->curr_lsb_ua;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	div = DIV_ROUND_CLOSEST_ULL(data->curr_lsb_ua * data->shunt_uohms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 				    1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	return regmap_write(data->regmap, TMP51X_SHUNT_CALIBRATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 			    DIV_ROUND_CLOSEST(40960, div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)  * Initialize the configuration and calibration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int tmp51x_init(struct tmp51x_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	int ret = regmap_write(data->regmap, TMP51X_SHUNT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 			       data->shunt_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	ret = regmap_write(data->regmap, TMP51X_TEMP_CONFIG, data->temp_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	// nFactor configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	ret = regmap_update_bits(data->regmap, TMP51X_N_FACTOR_AND_HYST_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 				 TMP51X_NFACTOR_MASK, data->nfactor[0] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	ret = regmap_write(data->regmap, TMP51X_N_FACTOR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 			   data->nfactor[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	if (data->id == tmp513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 		ret = regmap_write(data->regmap, TMP513_N_FACTOR_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 				   data->nfactor[2] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	ret = tmp51x_calibrate(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	// Read the status register before using as the datasheet propose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	return regmap_read(data->regmap, TMP51X_STATUS, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const struct i2c_device_id tmp51x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	{ "tmp512", tmp512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	{ "tmp513", tmp513 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MODULE_DEVICE_TABLE(i2c, tmp51x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct of_device_id tmp51x_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 		.compatible = "ti,tmp512",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		.data = (void *)tmp512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 		.compatible = "ti,tmp513",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 		.data = (void *)tmp513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_DEVICE_TABLE(of, tmp51x_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int tmp51x_vbus_range_to_reg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 				    struct tmp51x_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	if (data->vbus_range_uvolt == TMP51X_VBUS_RANGE_32V) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 		data->shunt_config |= TMP51X_BUS_VOLTAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	} else if (data->vbus_range_uvolt == TMP51X_VBUS_RANGE_16V) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 		data->shunt_config &= ~TMP51X_BUS_VOLTAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 		dev_err(dev, "ti,bus-range-microvolt is invalid: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 			data->vbus_range_uvolt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int tmp51x_pga_gain_to_reg(struct device *dev, struct tmp51x_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	if (data->pga_gain == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 		data->shunt_config |= CURRENT_SENSE_VOLTAGE_320_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	} else if (data->pga_gain == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 		data->shunt_config |= CURRENT_SENSE_VOLTAGE_160_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	} else if (data->pga_gain == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 		data->shunt_config |= CURRENT_SENSE_VOLTAGE_80_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	} else if (data->pga_gain == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 		data->shunt_config |= CURRENT_SENSE_VOLTAGE_40_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 		dev_err(dev, "ti,pga-gain is invalid: %u\n", data->pga_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int tmp51x_read_properties(struct device *dev, struct tmp51x_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	u32 nfactor[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	ret = device_property_read_u32(dev, "shunt-resistor-micro-ohms", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	data->shunt_uohms = (ret >= 0) ? val : TMP51X_SHUNT_VALUE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	ret = device_property_read_u32(dev, "ti,bus-range-microvolt", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 	data->vbus_range_uvolt = (ret >= 0) ? val : TMP51X_VBUS_RANGE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 	ret = tmp51x_vbus_range_to_reg(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	ret = device_property_read_u32(dev, "ti,pga-gain", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 	data->pga_gain = (ret >= 0) ? val : TMP51X_PGA_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	ret = tmp51x_pga_gain_to_reg(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 	ret = device_property_read_u32_array(dev, "ti,nfactor", nfactor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 					    (data->id == tmp513) ? 3 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 	if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 		memcpy(data->nfactor, nfactor, (data->id == tmp513) ? 3 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 	// Check if shunt value is compatible with pga-gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	if (data->shunt_uohms > data->pga_gain * 40 * 1000 * 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 		dev_err(dev, "shunt-resistor: %u too big for pga_gain: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 			data->shunt_uohms, data->pga_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void tmp51x_use_default(struct tmp51x_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 	data->vbus_range_uvolt = TMP51X_VBUS_RANGE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 	data->pga_gain = TMP51X_PGA_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	data->shunt_uohms = TMP51X_SHUNT_VALUE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int tmp51x_configure(struct device *dev, struct tmp51x_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	data->shunt_config = TMP51X_SHUNT_CONFIG_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 	data->temp_config = (data->id == tmp513) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 			TMP513_TEMP_CONFIG_DEFAULT : TMP512_TEMP_CONFIG_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 	if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 		return tmp51x_read_properties(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 	tmp51x_use_default(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int tmp51x_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 	struct tmp51x_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 	struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 	if (client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 		data->id = (enum tmp51x_ids)device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 		data->id = i2c_match_id(tmp51x_id, client)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 	ret = tmp51x_configure(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 		dev_err(dev, "error configuring the device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 	data->regmap = devm_regmap_init_i2c(client, &tmp51x_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 	if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 		dev_err(dev, "failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 		return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 	ret = tmp51x_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 		dev_err(dev, "error configuring the device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 	hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 							 data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 							 &tmp51x_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 							 NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 	if (IS_ERR(hwmon_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 		return PTR_ERR(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	dev_dbg(dev, "power monitor %s\n", client->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static struct i2c_driver tmp51x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 		.name	= "tmp51x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 		.of_match_table = of_match_ptr(tmp51x_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 	.probe_new	= tmp51x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 	.id_table	= tmp51x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) module_i2c_driver(tmp51x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MODULE_AUTHOR("Eric Tremblay <etremblay@distechcontrols.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) MODULE_DESCRIPTION("tmp51x driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) MODULE_LICENSE("GPL");