Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Texas Instruments TMP108 SMBus temperature sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2016 John Muir <john@jmuir.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define	DRIVER_NAME "tmp108"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define	TMP108_REG_TEMP		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	TMP108_REG_CONF		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	TMP108_REG_TLOW		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define	TMP108_REG_THIGH	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TMP108_TEMP_MIN_MC	-50000 /* Minimum millicelcius. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TMP108_TEMP_MAX_MC	127937 /* Maximum millicelcius. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Configuration register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * Note: these bit definitions are byte swapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TMP108_CONF_M0		0x0100 /* Sensor mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TMP108_CONF_M1		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TMP108_CONF_TM		0x0400 /* Thermostat mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TMP108_CONF_FL		0x0800 /* Watchdog flag - TLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TMP108_CONF_FH		0x1000 /* Watchdog flag - THIGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TMP108_CONF_CR0		0x2000 /* Conversion rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TMP108_CONF_CR1		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TMP108_CONF_ID		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TMP108_CONF_HYS0	0x0010 /* Hysteresis. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TMP108_CONF_HYS1	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TMP108_CONF_POL		0x0080 /* Polarity of alert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Defaults set by the hardware upon reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TMP108_CONF_DEFAULTS		(TMP108_CONF_CR0 | TMP108_CONF_TM |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 					 TMP108_CONF_HYS0 | TMP108_CONF_M1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* These bits are read-only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TMP108_CONF_READ_ONLY		(TMP108_CONF_FL | TMP108_CONF_FH |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 					 TMP108_CONF_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TMP108_CONF_MODE_MASK		(TMP108_CONF_M0|TMP108_CONF_M1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TMP108_MODE_SHUTDOWN		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TMP108_MODE_ONE_SHOT		TMP108_CONF_M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TMP108_MODE_CONTINUOUS		TMP108_CONF_M1		/* Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					/* When M1 is set, M0 is ignored. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TMP108_CONF_CONVRATE_MASK	(TMP108_CONF_CR0|TMP108_CONF_CR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TMP108_CONVRATE_0P25HZ		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TMP108_CONVRATE_1HZ		TMP108_CONF_CR0		/* Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define TMP108_CONVRATE_4HZ		TMP108_CONF_CR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TMP108_CONVRATE_16HZ		(TMP108_CONF_CR0|TMP108_CONF_CR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TMP108_CONF_HYSTERESIS_MASK	(TMP108_CONF_HYS0|TMP108_CONF_HYS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TMP108_HYSTERESIS_0C		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TMP108_HYSTERESIS_1C		TMP108_CONF_HYS0	/* Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TMP108_HYSTERESIS_2C		TMP108_CONF_HYS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TMP108_HYSTERESIS_4C		(TMP108_CONF_HYS0|TMP108_CONF_HYS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TMP108_CONVERSION_TIME_MS	30	/* in milli-seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) struct tmp108 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u16 orig_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned long ready_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* convert 12-bit TMP108 register value to milliCelsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static inline int tmp108_temp_reg_to_mC(s16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return (val & ~0x0f) * 1000 / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* convert milliCelsius to left adjusted 12-bit TMP108 register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static inline u16 tmp108_mC_to_temp_reg(int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return (val * 256) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int tmp108_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		       u32 attr, int channel, long *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct tmp108 *tmp108 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int err, hyst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (type == hwmon_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		if (attr == hwmon_chip_update_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			err = regmap_read(tmp108->regmap, TMP108_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					  &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			switch (regval & TMP108_CONF_CONVRATE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			case TMP108_CONVRATE_0P25HZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				*temp = 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			case TMP108_CONVRATE_1HZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				*temp = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			case TMP108_CONVRATE_4HZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				*temp = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			case TMP108_CONVRATE_16HZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				*temp = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		/* Is it too early to return a conversion ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (time_before(jiffies, tmp108->ready_time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			dev_dbg(dev, "%s: Conversion not ready yet..\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		err = regmap_read(tmp108->regmap, TMP108_REG_TEMP, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		*temp = tmp108_temp_reg_to_mC(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		err = regmap_read(tmp108->regmap, attr == hwmon_temp_min ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 				  TMP108_REG_TLOW : TMP108_REG_THIGH, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		*temp = tmp108_temp_reg_to_mC(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		err = regmap_read(tmp108->regmap, TMP108_REG_CONF, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		*temp = !!(regval & (attr == hwmon_temp_min_alarm ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				     TMP108_CONF_FL : TMP108_CONF_FH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case hwmon_temp_min_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	case hwmon_temp_max_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		err = regmap_read(tmp108->regmap, TMP108_REG_CONF, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		switch (regval & TMP108_CONF_HYSTERESIS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		case TMP108_HYSTERESIS_0C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			hyst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		case TMP108_HYSTERESIS_1C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			hyst = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		case TMP108_HYSTERESIS_2C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			hyst = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		case TMP108_HYSTERESIS_4C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			hyst = 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		err = regmap_read(tmp108->regmap, attr == hwmon_temp_min_hyst ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				  TMP108_REG_TLOW : TMP108_REG_THIGH, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		*temp = tmp108_temp_reg_to_mC(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (attr == hwmon_temp_min_hyst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			*temp += hyst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			*temp -= hyst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int tmp108_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			u32 attr, int channel, long temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct tmp108 *tmp108 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	u32 regval, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (type == hwmon_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		if (attr == hwmon_chip_update_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			if (temp < 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				mask = TMP108_CONVRATE_16HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			else if (temp < 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				mask = TMP108_CONVRATE_4HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			else if (temp < 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				mask = TMP108_CONVRATE_1HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				mask = TMP108_CONVRATE_0P25HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			return regmap_update_bits(tmp108->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 						  TMP108_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 						  TMP108_CONF_CONVRATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 						  mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		temp = clamp_val(temp, TMP108_TEMP_MIN_MC, TMP108_TEMP_MAX_MC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return regmap_write(tmp108->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				    attr == hwmon_temp_min ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					TMP108_REG_TLOW : TMP108_REG_THIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				    tmp108_mC_to_temp_reg(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	case hwmon_temp_min_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	case hwmon_temp_max_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		temp = clamp_val(temp, TMP108_TEMP_MIN_MC, TMP108_TEMP_MAX_MC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		err = regmap_read(tmp108->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				  attr == hwmon_temp_min_hyst ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 					TMP108_REG_TLOW : TMP108_REG_THIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				  &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if (attr == hwmon_temp_min_hyst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			temp -= tmp108_temp_reg_to_mC(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			temp = tmp108_temp_reg_to_mC(regval) - temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		if (temp < 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			mask = TMP108_HYSTERESIS_0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		else if (temp < 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			mask = TMP108_HYSTERESIS_1C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		else if (temp < 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			mask = TMP108_HYSTERESIS_2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			mask = TMP108_HYSTERESIS_4C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return regmap_update_bits(tmp108->regmap, TMP108_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 					  TMP108_CONF_HYSTERESIS_MASK, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static umode_t tmp108_is_visible(const void *data, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 				 u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (type == hwmon_chip && attr == hwmon_chip_update_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	case hwmon_temp_min_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case hwmon_temp_max_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct hwmon_channel_info *tmp108_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	HWMON_CHANNEL_INFO(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			   HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			   HWMON_T_MIN_HYST | HWMON_T_MAX_HYST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			   HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct hwmon_ops tmp108_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.is_visible = tmp108_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.read = tmp108_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.write = tmp108_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct hwmon_chip_info tmp108_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.ops = &tmp108_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.info = tmp108_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void tmp108_restore_config(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct tmp108 *tmp108 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	regmap_write(tmp108->regmap, TMP108_REG_CONF, tmp108->orig_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static bool tmp108_is_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return reg != TMP108_REG_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static bool tmp108_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* Configuration register must be volatile to enable FL and FH. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return reg == TMP108_REG_TEMP || reg == TMP108_REG_CONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct regmap_config tmp108_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.max_register = TMP108_REG_THIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.writeable_reg = tmp108_is_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.volatile_reg = tmp108_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.val_format_endian = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.use_single_read = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int tmp108_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	struct tmp108 *tmp108;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (!i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 				     I2C_FUNC_SMBUS_WORD_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			"adapter doesn't support SMBus word transactions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	tmp108 = devm_kzalloc(dev, sizeof(*tmp108), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (!tmp108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	dev_set_drvdata(dev, tmp108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	tmp108->regmap = devm_regmap_init_i2c(client, &tmp108_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (IS_ERR(tmp108->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		err = PTR_ERR(tmp108->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		dev_err(dev, "regmap init failed: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	err = regmap_read(tmp108->regmap, TMP108_REG_CONF, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		dev_err(dev, "error reading config register: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	tmp108->orig_config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* Only continuous mode is supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	config &= ~TMP108_CONF_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	config |= TMP108_MODE_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	/* Only comparator mode is supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	config &= ~TMP108_CONF_TM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	err = regmap_write(tmp108->regmap, TMP108_REG_CONF, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		dev_err(dev, "error writing config register: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	tmp108->ready_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if ((tmp108->orig_config & TMP108_CONF_MODE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	    TMP108_MODE_SHUTDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		tmp108->ready_time +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			msecs_to_jiffies(TMP108_CONVERSION_TIME_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	err = devm_add_action_or_reset(dev, tmp108_restore_config, tmp108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		dev_err(dev, "add action or reset failed: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 							 tmp108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 							 &tmp108_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 							 NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int __maybe_unused tmp108_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	struct tmp108 *tmp108 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	return regmap_update_bits(tmp108->regmap, TMP108_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 				  TMP108_CONF_MODE_MASK, TMP108_MODE_SHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int __maybe_unused tmp108_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct tmp108 *tmp108 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	err = regmap_update_bits(tmp108->regmap, TMP108_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 				 TMP108_CONF_MODE_MASK, TMP108_MODE_CONTINUOUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	tmp108->ready_time = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 			     msecs_to_jiffies(TMP108_CONVERSION_TIME_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static SIMPLE_DEV_PM_OPS(tmp108_dev_pm_ops, tmp108_suspend, tmp108_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const struct i2c_device_id tmp108_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	{ "tmp108", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MODULE_DEVICE_TABLE(i2c, tmp108_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct of_device_id tmp108_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	{ .compatible = "ti,tmp108", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MODULE_DEVICE_TABLE(of, tmp108_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct i2c_driver tmp108_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		.name	= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		.pm	= &tmp108_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		.of_match_table = of_match_ptr(tmp108_of_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.probe_new	= tmp108_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.id_table	= tmp108_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) module_i2c_driver(tmp108_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_AUTHOR("John Muir <john@jmuir.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MODULE_DESCRIPTION("Texas Instruments TMP108 temperature sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_LICENSE("GPL");