Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Texas Instruments TMP102 SMBus temperature sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2010 Steven King <sfking@fdwdc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define	DRIVER_NAME "tmp102"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define	TMP102_TEMP_REG			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	TMP102_CONF_REG			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* note: these bit definitions are byte swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define		TMP102_CONF_SD		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define		TMP102_CONF_TM		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define		TMP102_CONF_POL		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define		TMP102_CONF_F0		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define		TMP102_CONF_F1		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define		TMP102_CONF_R0		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define		TMP102_CONF_R1		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define		TMP102_CONF_OS		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define		TMP102_CONF_EM		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define		TMP102_CONF_AL		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define		TMP102_CONF_CR0		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define		TMP102_CONF_CR1		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	TMP102_TLOW_REG			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	TMP102_THIGH_REG		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TMP102_CONFREG_MASK	(TMP102_CONF_SD | TMP102_CONF_TM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 				 TMP102_CONF_POL | TMP102_CONF_F0 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 				 TMP102_CONF_F1 | TMP102_CONF_OS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 				 TMP102_CONF_EM | TMP102_CONF_AL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 				 TMP102_CONF_CR0 | TMP102_CONF_CR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TMP102_CONFIG_CLEAR	(TMP102_CONF_SD | TMP102_CONF_OS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 				 TMP102_CONF_CR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TMP102_CONFIG_SET	(TMP102_CONF_TM | TMP102_CONF_EM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 				 TMP102_CONF_CR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CONVERSION_TIME_MS		35	/* in milli-seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) struct tmp102 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u16 config_orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned long ready_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* convert left adjusted 13-bit TMP102 register value to milliCelsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static inline int tmp102_reg_to_mC(s16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return ((val & ~0x01) * 1000) / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* convert milliCelsius to left adjusted 13-bit TMP102 register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static inline u16 tmp102_mC_to_reg(int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return (val * 128) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static int tmp102_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		       u32 attr, int channel, long *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct tmp102 *tmp102 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int err, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		/* Is it too early to return a conversion ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		if (time_before(jiffies, tmp102->ready_time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			dev_dbg(dev, "%s: Conversion not ready yet..\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		reg = TMP102_TEMP_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	case hwmon_temp_max_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		reg = TMP102_TLOW_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		reg = TMP102_THIGH_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	err = regmap_read(tmp102->regmap, reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	*temp = tmp102_reg_to_mC(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int tmp102_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			u32 attr, int channel, long temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct tmp102 *tmp102 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	case hwmon_temp_max_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		reg = TMP102_TLOW_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		reg = TMP102_THIGH_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	temp = clamp_val(temp, -256000, 255000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return regmap_write(tmp102->regmap, reg, tmp102_mC_to_reg(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static umode_t tmp102_is_visible(const void *data, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				 u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	case hwmon_temp_max_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct hwmon_channel_info *tmp102_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	HWMON_CHANNEL_INFO(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			   HWMON_C_REGISTER_TZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct hwmon_ops tmp102_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.is_visible = tmp102_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.read = tmp102_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.write = tmp102_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct hwmon_chip_info tmp102_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.ops = &tmp102_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.info = tmp102_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void tmp102_restore_config(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct tmp102 *tmp102 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	regmap_write(tmp102->regmap, TMP102_CONF_REG, tmp102->config_orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static bool tmp102_is_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return reg != TMP102_TEMP_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static bool tmp102_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return reg == TMP102_TEMP_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct regmap_config tmp102_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.max_register = TMP102_THIGH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.writeable_reg = tmp102_is_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.volatile_reg = tmp102_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.val_format_endian = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.use_single_read = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int tmp102_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct tmp102 *tmp102;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (!i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				     I2C_FUNC_SMBUS_WORD_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			"adapter doesn't support SMBus word transactions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	tmp102 = devm_kzalloc(dev, sizeof(*tmp102), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (!tmp102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	i2c_set_clientdata(client, tmp102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	tmp102->regmap = devm_regmap_init_i2c(client, &tmp102_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (IS_ERR(tmp102->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return PTR_ERR(tmp102->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	err = regmap_read(tmp102->regmap, TMP102_CONF_REG, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		dev_err(dev, "error reading config register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if ((regval & ~TMP102_CONFREG_MASK) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	    (TMP102_CONF_R0 | TMP102_CONF_R1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_err(dev, "unexpected config register value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	tmp102->config_orig = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	err = devm_add_action_or_reset(dev, tmp102_restore_config, tmp102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	regval &= ~TMP102_CONFIG_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	regval |= TMP102_CONFIG_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	err = regmap_write(tmp102->regmap, TMP102_CONF_REG, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		dev_err(dev, "error writing config register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * Mark that we are not ready with data until the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 * conversion is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	tmp102->ready_time = jiffies + msecs_to_jiffies(CONVERSION_TIME_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 							 tmp102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 							 &tmp102_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 							 NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (IS_ERR(hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		dev_dbg(dev, "unable to register hwmon device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return PTR_ERR(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	dev_info(dev, "initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int tmp102_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct tmp102 *tmp102 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return regmap_update_bits(tmp102->regmap, TMP102_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				  TMP102_CONF_SD, TMP102_CONF_SD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int tmp102_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct tmp102 *tmp102 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	err = regmap_update_bits(tmp102->regmap, TMP102_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				 TMP102_CONF_SD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	tmp102->ready_time = jiffies + msecs_to_jiffies(CONVERSION_TIME_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static SIMPLE_DEV_PM_OPS(tmp102_dev_pm_ops, tmp102_suspend, tmp102_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct i2c_device_id tmp102_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{ "tmp102", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_DEVICE_TABLE(i2c, tmp102_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct of_device_id __maybe_unused tmp102_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	{ .compatible = "ti,tmp102" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_DEVICE_TABLE(of, tmp102_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct i2c_driver tmp102_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.driver.name	= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.driver.of_match_table = of_match_ptr(tmp102_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.driver.pm	= &tmp102_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.probe_new	= tmp102_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.id_table	= tmp102_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) module_i2c_driver(tmp102_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MODULE_DESCRIPTION("Texas Instruments TMP102 temperature sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MODULE_LICENSE("GPL");