^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Sparx5 SoC temperature sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2020 Lars Povlsen <lars.povlsen@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEMP_CTRL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEMP_CFG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEMP_CFG_CYCLES GENMASK(24, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEMP_CFG_ENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEMP_STAT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEMP_STAT_VALID BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEMP_STAT_TEMP GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct s5_hwmon {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void s5_temp_clk_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk *clk = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void s5_temp_enable(struct s5_hwmon *hwmon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 val = readl(hwmon->base + TEMP_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 clk = clk_get_rate(hwmon->clk) / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) val &= ~TEMP_CFG_CYCLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) val |= FIELD_PREP(TEMP_CFG_CYCLES, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) val |= TEMP_CFG_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writel(val, hwmon->base + TEMP_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int s5_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 attr, int channel, long *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct s5_hwmon *hwmon = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int rc = 0, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) stat = readl_relaxed(hwmon->base + TEMP_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!(stat & TEMP_STAT_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) value = stat & TEMP_STAT_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * From register documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Temp(C) = TEMP_SENSOR_STAT.TEMP / 4096 * 352.2 - 109.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) value = DIV_ROUND_CLOSEST(value * 3522, 4096) - 1094;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Scale down by 10 from above and multiply by 1000 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * have millidegrees as specified by the hwmon sysfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) value *= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *temp = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) rc = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static umode_t s5_is_visible(const void *_data, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct hwmon_channel_info *s5_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct hwmon_ops s5_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .is_visible = s5_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .read = s5_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct hwmon_chip_info s5_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .ops = &s5_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .info = s5_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int s5_temp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct s5_hwmon *hwmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!hwmon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) hwmon->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (IS_ERR(hwmon->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return PTR_ERR(hwmon->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) hwmon->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (IS_ERR(hwmon->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return PTR_ERR(hwmon->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = clk_prepare_enable(hwmon->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = devm_add_action_or_reset(&pdev->dev, s5_temp_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) hwmon->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) s5_temp_enable(hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "s5_temp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) hwmon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &s5_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct of_device_id s5_temp_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { .compatible = "microchip,sparx5-temp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MODULE_DEVICE_TABLE(of, s5_temp_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct platform_driver s5_temp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .probe = s5_temp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "sparx5-temp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .of_match_table = s5_temp_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) module_platform_driver(s5_temp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_AUTHOR("Lars Povlsen <lars.povlsen@microchip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_DESCRIPTION("Sparx5 SoC temperature sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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