^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for SMM665 Power Controller / Monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Ericsson AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This driver should also work for SMM465, SMM764, and SMM766, but is untested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for those chips. Only monitoring functionality is implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Datasheets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * http://www.summitmicro.com/prod_select/summary/SMM665/SMM665B_2089_20.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * http://www.summitmicro.com/prod_select/summary/SMM766B/SMM766B_2122.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Internal reference voltage (VREF, x 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SMM665_VREF_ADC_X1000 1250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int vref = SMM665_VREF_ADC_X1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) module_param(vref, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_PARM_DESC(vref, "Reference voltage in mV");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum chips { smm465, smm665, smm665c, smm764, smm766 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * ADC channel addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SMM665_MISC16_ADC_DATA_A 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SMM665_MISC16_ADC_DATA_B 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SMM665_MISC16_ADC_DATA_C 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SMM665_MISC16_ADC_DATA_D 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SMM665_MISC16_ADC_DATA_E 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SMM665_MISC16_ADC_DATA_F 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SMM665_MISC16_ADC_DATA_VDD 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SMM665_MISC16_ADC_DATA_12V 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SMM665_MISC16_ADC_DATA_INT_TEMP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SMM665_MISC16_ADC_DATA_AIN1 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SMM665_MISC16_ADC_DATA_AIN2 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Command registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SMM665_MISC8_CMD_STS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SMM665_MISC8_STATUS1 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SMM665_MISC8_STATUSS2 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SMM665_MISC8_IO_POLARITY 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SMM665_MISC8_PUP_POLARITY 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SMM665_MISC8_ADOC_STATUS1 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SMM665_MISC8_ADOC_STATUS2 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SMM665_MISC8_WRITE_PROT 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SMM665_MISC8_STS_TRACK 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Configuration registers and register groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SMM665_ADOC_ENABLE 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SMM665_LIMIT_BASE 0x80 /* First limit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Limit register bit masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SMM665_TRIGGER_RST 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SMM665_TRIGGER_HEALTHY 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SMM665_TRIGGER_POWEROFF 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SMM665_TRIGGER_SHUTDOWN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SMM665_ADC_MASK 0x03ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define smm665_is_critical(lim) ((lim) & (SMM665_TRIGGER_RST \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) | SMM665_TRIGGER_POWEROFF \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) | SMM665_TRIGGER_SHUTDOWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Fault register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Values are merged from status registers 1/2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * with status register 1 providing the upper 8 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SMM665_FAULT_A 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SMM665_FAULT_B 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SMM665_FAULT_C 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SMM665_FAULT_D 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SMM665_FAULT_E 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SMM665_FAULT_F 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SMM665_FAULT_VDD 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SMM665_FAULT_12V 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SMM665_FAULT_TEMP 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SMM665_FAULT_AIN1 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SMM665_FAULT_AIN2 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * I2C Register addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * The configuration register needs to be the configured base register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * The command/status register address is derived from it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SMM665_REGMASK 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SMM665_CMDREG_BASE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SMM665_CONFREG_BASE 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Equations given by chip manufacturer to calculate voltage/temperature values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * vref = Reference voltage on VREF_ADC pin (module parameter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * adc = 10bit ADC value read back from registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Voltage A-F and VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SMM665_VMON_ADC_TO_VOLTS(adc) ((adc) * vref / 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Voltage 12VIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SMM665_12VIN_ADC_TO_VOLTS(adc) ((adc) * vref * 3 / 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Voltage AIN1, AIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SMM665_AIN_ADC_TO_VOLTS(adc) ((adc) * vref / 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Temp Sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SMM665_TEMP_ADC_TO_CELSIUS(adc) (((adc) <= 511) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ((int)(adc) * 1000 / 4) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (((int)(adc) - 0x400) * 1000 / 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SMM665_NUM_ADC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Chip dependent ADC conversion time, in uS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SMM665_ADC_WAIT_SMM665 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SMM665_ADC_WAIT_SMM766 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct smm665_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum chips type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int conversion_time; /* ADC conversion time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long last_updated; /* in jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u16 adc[SMM665_NUM_ADC]; /* adc values (raw) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u16 faults; /* fault status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* The following values are in mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int critical_min_limit[SMM665_NUM_ADC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int alarm_min_limit[SMM665_NUM_ADC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int critical_max_limit[SMM665_NUM_ADC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int alarm_max_limit[SMM665_NUM_ADC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct i2c_client *cmdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * smm665_read16()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Read 16 bit value from <reg>, <reg+1>. Upper 8 bits are in <reg>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int smm665_read16(struct i2c_client *client, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int rv, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rv = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (rv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val = rv << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rv = i2c_smbus_read_byte_data(client, reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (rv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val |= rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Read adc value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int smm665_read_adc(struct smm665_data *data, int adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct i2c_client *client = data->cmdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int radc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Algorithm for reading ADC, per SMM665 datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * {[S][addr][W][Ack]} {[offset][Ack]} {[S][addr][R][Nack]}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * [wait conversion time]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * {[S][addr][R][Ack]} {[datahi][Ack]} {[datalo][Ack][P]}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * To implement the first part of this exchange,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * do a full read transaction and expect a failure/Nack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * This sets up the address pointer on the SMM665
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * and starts the ADC conversion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Then do a two-byte read transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) rv = i2c_smbus_read_byte_data(client, adc << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (rv != -ENXIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * We expect ENXIO to reflect NACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * (per Documentation/i2c/fault-codes.rst).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Everything else is an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "Unexpected return code %d when setting ADC index", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return (rv < 0) ? rv : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) udelay(data->conversion_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Now read two bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Neither i2c_smbus_read_byte() nor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * i2c_smbus_read_block_data() worked here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * so use i2c_smbus_read_word_swapped() instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * We could also try to use i2c_master_recv(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * but that is not always supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rv = i2c_smbus_read_word_swapped(client, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (rv < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_dbg(&client->dev, "Failed to read ADC value: error %d", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * Validate/verify readback adc channel (in bit 11..14).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) radc = (rv >> 11) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (radc != adc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_dbg(&client->dev, "Unexpected RADC: Expected %d got %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) adc, radc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return rv & SMM665_ADC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct smm665_data *smm665_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct smm665_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct smm665_data *ret = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int i, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * read status registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) val = smm665_read16(client, SMM665_MISC8_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (unlikely(val < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = ERR_PTR(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) data->faults = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Read adc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 0; i < SMM665_NUM_ADC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val = smm665_read_adc(data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (unlikely(val < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = ERR_PTR(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) data->adc[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) data->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Return converted value from given adc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int smm665_convert(u16 adcval, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case SMM665_MISC16_ADC_DATA_12V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val = SMM665_12VIN_ADC_TO_VOLTS(adcval & SMM665_ADC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case SMM665_MISC16_ADC_DATA_VDD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case SMM665_MISC16_ADC_DATA_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case SMM665_MISC16_ADC_DATA_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case SMM665_MISC16_ADC_DATA_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case SMM665_MISC16_ADC_DATA_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case SMM665_MISC16_ADC_DATA_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case SMM665_MISC16_ADC_DATA_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val = SMM665_VMON_ADC_TO_VOLTS(adcval & SMM665_ADC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case SMM665_MISC16_ADC_DATA_AIN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case SMM665_MISC16_ADC_DATA_AIN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) val = SMM665_AIN_ADC_TO_VOLTS(adcval & SMM665_ADC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case SMM665_MISC16_ADC_DATA_INT_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) val = SMM665_TEMP_ADC_TO_CELSIUS(adcval & SMM665_ADC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* If we get here, the developer messed up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int smm665_get_min(struct device *dev, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct smm665_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return data->alarm_min_limit[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int smm665_get_max(struct device *dev, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct smm665_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return data->alarm_max_limit[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int smm665_get_lcrit(struct device *dev, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct smm665_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return data->critical_min_limit[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int smm665_get_crit(struct device *dev, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct smm665_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return data->critical_max_limit[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static ssize_t smm665_show_crit_alarm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct device_attribute *da, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct smm665_data *data = smm665_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (data->faults & (1 << attr->index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return snprintf(buf, PAGE_SIZE, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static ssize_t smm665_show_input(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct device_attribute *da, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct smm665_data *data = smm665_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int adc = attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) val = smm665_convert(data->adc[adc], adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return snprintf(buf, PAGE_SIZE, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SMM665_SHOW(what) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static ssize_t smm665_show_##what(struct device *dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct device_attribute *da, char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct sensor_device_attribute *attr = to_sensor_dev_attr(da); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) const int val = smm665_get_##what(dev, attr->index); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return snprintf(buf, PAGE_SIZE, "%d\n", val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SMM665_SHOW(min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SMM665_SHOW(max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SMM665_SHOW(lcrit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) SMM665_SHOW(crit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * These macros are used below in constructing device attribute objects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * for use with sysfs_create_group() to make a sysfs device file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * for each register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SMM665_ATTR(name, type, cmd_idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static SENSOR_DEVICE_ATTR(name##_##type, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) smm665_show_##type, NULL, cmd_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Construct a sensor_device_attribute structure for each register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Input voltages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SMM665_ATTR(in1, input, SMM665_MISC16_ADC_DATA_12V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SMM665_ATTR(in2, input, SMM665_MISC16_ADC_DATA_VDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) SMM665_ATTR(in3, input, SMM665_MISC16_ADC_DATA_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SMM665_ATTR(in4, input, SMM665_MISC16_ADC_DATA_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SMM665_ATTR(in5, input, SMM665_MISC16_ADC_DATA_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SMM665_ATTR(in6, input, SMM665_MISC16_ADC_DATA_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SMM665_ATTR(in7, input, SMM665_MISC16_ADC_DATA_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SMM665_ATTR(in8, input, SMM665_MISC16_ADC_DATA_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SMM665_ATTR(in9, input, SMM665_MISC16_ADC_DATA_AIN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SMM665_ATTR(in10, input, SMM665_MISC16_ADC_DATA_AIN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Input voltages min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SMM665_ATTR(in1, min, SMM665_MISC16_ADC_DATA_12V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SMM665_ATTR(in2, min, SMM665_MISC16_ADC_DATA_VDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SMM665_ATTR(in3, min, SMM665_MISC16_ADC_DATA_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) SMM665_ATTR(in4, min, SMM665_MISC16_ADC_DATA_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SMM665_ATTR(in5, min, SMM665_MISC16_ADC_DATA_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SMM665_ATTR(in6, min, SMM665_MISC16_ADC_DATA_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SMM665_ATTR(in7, min, SMM665_MISC16_ADC_DATA_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SMM665_ATTR(in8, min, SMM665_MISC16_ADC_DATA_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SMM665_ATTR(in9, min, SMM665_MISC16_ADC_DATA_AIN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) SMM665_ATTR(in10, min, SMM665_MISC16_ADC_DATA_AIN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Input voltages max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) SMM665_ATTR(in1, max, SMM665_MISC16_ADC_DATA_12V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) SMM665_ATTR(in2, max, SMM665_MISC16_ADC_DATA_VDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) SMM665_ATTR(in3, max, SMM665_MISC16_ADC_DATA_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) SMM665_ATTR(in4, max, SMM665_MISC16_ADC_DATA_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) SMM665_ATTR(in5, max, SMM665_MISC16_ADC_DATA_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SMM665_ATTR(in6, max, SMM665_MISC16_ADC_DATA_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) SMM665_ATTR(in7, max, SMM665_MISC16_ADC_DATA_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) SMM665_ATTR(in8, max, SMM665_MISC16_ADC_DATA_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) SMM665_ATTR(in9, max, SMM665_MISC16_ADC_DATA_AIN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) SMM665_ATTR(in10, max, SMM665_MISC16_ADC_DATA_AIN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Input voltages lcrit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) SMM665_ATTR(in1, lcrit, SMM665_MISC16_ADC_DATA_12V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SMM665_ATTR(in2, lcrit, SMM665_MISC16_ADC_DATA_VDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SMM665_ATTR(in3, lcrit, SMM665_MISC16_ADC_DATA_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) SMM665_ATTR(in4, lcrit, SMM665_MISC16_ADC_DATA_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) SMM665_ATTR(in5, lcrit, SMM665_MISC16_ADC_DATA_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SMM665_ATTR(in6, lcrit, SMM665_MISC16_ADC_DATA_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) SMM665_ATTR(in7, lcrit, SMM665_MISC16_ADC_DATA_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) SMM665_ATTR(in8, lcrit, SMM665_MISC16_ADC_DATA_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) SMM665_ATTR(in9, lcrit, SMM665_MISC16_ADC_DATA_AIN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) SMM665_ATTR(in10, lcrit, SMM665_MISC16_ADC_DATA_AIN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Input voltages crit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) SMM665_ATTR(in1, crit, SMM665_MISC16_ADC_DATA_12V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) SMM665_ATTR(in2, crit, SMM665_MISC16_ADC_DATA_VDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SMM665_ATTR(in3, crit, SMM665_MISC16_ADC_DATA_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) SMM665_ATTR(in4, crit, SMM665_MISC16_ADC_DATA_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SMM665_ATTR(in5, crit, SMM665_MISC16_ADC_DATA_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) SMM665_ATTR(in6, crit, SMM665_MISC16_ADC_DATA_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SMM665_ATTR(in7, crit, SMM665_MISC16_ADC_DATA_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SMM665_ATTR(in8, crit, SMM665_MISC16_ADC_DATA_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) SMM665_ATTR(in9, crit, SMM665_MISC16_ADC_DATA_AIN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SMM665_ATTR(in10, crit, SMM665_MISC16_ADC_DATA_AIN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* critical alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SMM665_ATTR(in1, crit_alarm, SMM665_FAULT_12V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) SMM665_ATTR(in2, crit_alarm, SMM665_FAULT_VDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SMM665_ATTR(in3, crit_alarm, SMM665_FAULT_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) SMM665_ATTR(in4, crit_alarm, SMM665_FAULT_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SMM665_ATTR(in5, crit_alarm, SMM665_FAULT_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) SMM665_ATTR(in6, crit_alarm, SMM665_FAULT_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) SMM665_ATTR(in7, crit_alarm, SMM665_FAULT_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SMM665_ATTR(in8, crit_alarm, SMM665_FAULT_F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SMM665_ATTR(in9, crit_alarm, SMM665_FAULT_AIN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) SMM665_ATTR(in10, crit_alarm, SMM665_FAULT_AIN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) SMM665_ATTR(temp1, input, SMM665_MISC16_ADC_DATA_INT_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) SMM665_ATTR(temp1, min, SMM665_MISC16_ADC_DATA_INT_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SMM665_ATTR(temp1, max, SMM665_MISC16_ADC_DATA_INT_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SMM665_ATTR(temp1, lcrit, SMM665_MISC16_ADC_DATA_INT_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) SMM665_ATTR(temp1, crit, SMM665_MISC16_ADC_DATA_INT_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) SMM665_ATTR(temp1, crit_alarm, SMM665_FAULT_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * Finally, construct an array of pointers to members of the above objects,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * as required for sysfs_create_group()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct attribute *smm665_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) &sensor_dev_attr_in1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &sensor_dev_attr_in1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &sensor_dev_attr_in1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &sensor_dev_attr_in1_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &sensor_dev_attr_in1_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &sensor_dev_attr_in1_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) &sensor_dev_attr_in2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &sensor_dev_attr_in2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) &sensor_dev_attr_in2_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) &sensor_dev_attr_in2_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) &sensor_dev_attr_in2_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) &sensor_dev_attr_in2_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) &sensor_dev_attr_in3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) &sensor_dev_attr_in3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) &sensor_dev_attr_in3_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &sensor_dev_attr_in3_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) &sensor_dev_attr_in3_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) &sensor_dev_attr_in3_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) &sensor_dev_attr_in4_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) &sensor_dev_attr_in4_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) &sensor_dev_attr_in4_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) &sensor_dev_attr_in4_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) &sensor_dev_attr_in4_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) &sensor_dev_attr_in4_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) &sensor_dev_attr_in5_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) &sensor_dev_attr_in5_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &sensor_dev_attr_in5_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) &sensor_dev_attr_in5_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &sensor_dev_attr_in5_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &sensor_dev_attr_in5_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) &sensor_dev_attr_in6_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &sensor_dev_attr_in6_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) &sensor_dev_attr_in6_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &sensor_dev_attr_in6_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &sensor_dev_attr_in6_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &sensor_dev_attr_in6_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) &sensor_dev_attr_in7_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &sensor_dev_attr_in7_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) &sensor_dev_attr_in7_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &sensor_dev_attr_in7_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &sensor_dev_attr_in7_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &sensor_dev_attr_in7_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) &sensor_dev_attr_in8_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &sensor_dev_attr_in8_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) &sensor_dev_attr_in8_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) &sensor_dev_attr_in8_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &sensor_dev_attr_in8_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) &sensor_dev_attr_in8_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &sensor_dev_attr_in9_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) &sensor_dev_attr_in9_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) &sensor_dev_attr_in9_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) &sensor_dev_attr_in9_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) &sensor_dev_attr_in9_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) &sensor_dev_attr_in9_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) &sensor_dev_attr_in10_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) &sensor_dev_attr_in10_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &sensor_dev_attr_in10_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &sensor_dev_attr_in10_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) &sensor_dev_attr_in10_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) &sensor_dev_attr_in10_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) &sensor_dev_attr_temp1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) &sensor_dev_attr_temp1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) &sensor_dev_attr_temp1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) &sensor_dev_attr_temp1_lcrit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &sensor_dev_attr_temp1_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) &sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ATTRIBUTE_GROUPS(smm665);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const struct i2c_device_id smm665_id[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int smm665_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct smm665_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) | I2C_FUNC_SMBUS_WORD_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (i2c_smbus_read_byte_data(client, SMM665_ADOC_ENABLE) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) data->type = i2c_match_id(smm665_id, client)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) data->cmdreg = i2c_new_dummy_device(adapter, (client->addr & ~SMM665_REGMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) | SMM665_CMDREG_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (IS_ERR(data->cmdreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return PTR_ERR(data->cmdreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case smm465:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case smm665:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) data->conversion_time = SMM665_ADC_WAIT_SMM665;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case smm665c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case smm764:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case smm766:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) data->conversion_time = SMM665_ADC_WAIT_SMM766;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (i2c_smbus_read_byte_data(data->cmdreg, SMM665_MISC8_CMD_STS) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * Read limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * Limit registers start with register SMM665_LIMIT_BASE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * Each channel uses 8 registers, providing four limit values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * per channel. Each limit value requires two registers, with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * high byte in the first register and the low byte in the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * register. The first two limits are under limit values, followed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * by two over limit values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Limit register order matches the ADC register order, so we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * ADC register defines throughout the code to index limit registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * We save the first retrieved value both as "critical" and "alarm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * value. The second value overwrites either the critical or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * alarm value, depending on its configuration. This ensures that both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * critical and alarm values are initialized, even if both registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * configured as critical or non-critical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (i = 0; i < SMM665_NUM_ADC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (unlikely(val < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) data->critical_min_limit[i] = data->alarm_min_limit[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) = smm665_convert(val, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8 + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (unlikely(val < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) goto out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (smm665_is_critical(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) data->critical_min_limit[i] = smm665_convert(val, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) data->alarm_min_limit[i] = smm665_convert(val, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8 + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (unlikely(val < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) goto out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) data->critical_max_limit[i] = data->alarm_max_limit[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) = smm665_convert(val, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) val = smm665_read16(client, SMM665_LIMIT_BASE + i * 8 + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (unlikely(val < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) goto out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (smm665_is_critical(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) data->critical_max_limit[i] = smm665_convert(val, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) data->alarm_max_limit[i] = smm665_convert(val, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hwmon_dev = devm_hwmon_device_register_with_groups(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) client->name, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) smm665_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (IS_ERR(hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = PTR_ERR(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) goto out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) out_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) i2c_unregister_device(data->cmdreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int smm665_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct smm665_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) i2c_unregister_device(data->cmdreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const struct i2c_device_id smm665_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {"smm465", smm465},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {"smm665", smm665},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {"smm665c", smm665c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {"smm764", smm764},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {"smm766", smm766},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MODULE_DEVICE_TABLE(i2c, smm665_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* This is the driver that will be inserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static struct i2c_driver smm665_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .name = "smm665",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .probe_new = smm665_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .remove = smm665_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .id_table = smm665_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) module_i2c_driver(smm665_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MODULE_AUTHOR("Guenter Roeck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MODULE_DESCRIPTION("SMM665 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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