Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Hardware monitoring driver for ucd9200 series Digital PWM System Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011 Ericsson AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pmbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "pmbus.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define UCD9200_PHASE_INFO	0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define UCD9200_DEVICE_ID	0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) enum chips { ucd9200, ucd9220, ucd9222, ucd9224, ucd9240, ucd9244, ucd9246,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	     ucd9248 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static const struct i2c_device_id ucd9200_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	{"ucd9200", ucd9200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	{"ucd9220", ucd9220},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	{"ucd9222", ucd9222},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{"ucd9224", ucd9224},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	{"ucd9240", ucd9240},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	{"ucd9244", ucd9244},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{"ucd9246", ucd9246},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{"ucd9248", ucd9248},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) MODULE_DEVICE_TABLE(i2c, ucd9200_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static const struct of_device_id __maybe_unused ucd9200_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.compatible = "ti,cd9200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.data = (void *)ucd9200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.compatible = "ti,cd9220",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.data = (void *)ucd9220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.compatible = "ti,cd9222",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.data = (void *)ucd9222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.compatible = "ti,cd9224",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.data = (void *)ucd9224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.compatible = "ti,cd9240",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.data = (void *)ucd9240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.compatible = "ti,cd9244",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.data = (void *)ucd9244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.compatible = "ti,cd9246",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.data = (void *)ucd9246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.compatible = "ti,cd9248",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.data = (void *)ucd9248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) MODULE_DEVICE_TABLE(of, ucd9200_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int ucd9200_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8 block_buffer[I2C_SMBUS_BLOCK_MAX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct pmbus_driver_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	const struct i2c_device_id *mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	enum chips chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int i, j, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (!i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 				     I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				     I2C_FUNC_SMBUS_BLOCK_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	ret = i2c_smbus_read_block_data(client, UCD9200_DEVICE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 					block_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		dev_err(&client->dev, "Failed to read device ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	block_buffer[ret] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	dev_info(&client->dev, "Device ID %s\n", block_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	for (mid = ucd9200_id; mid->name[0]; mid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		if (!strncasecmp(mid->name, block_buffer, strlen(mid->name)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (!mid->name[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		dev_err(&client->dev, "Unsupported device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		chip = (enum chips)of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		chip = mid->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (chip != ucd9200 && strcmp(client->name, mid->name) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		dev_notice(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			   "Device mismatch: Configured %s, detected %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			   client->name, mid->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	info = devm_kzalloc(&client->dev, sizeof(struct pmbus_driver_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ret = i2c_smbus_read_block_data(client, UCD9200_PHASE_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 					block_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		dev_err(&client->dev, "Failed to read phase information\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * Calculate number of configured pages (rails) from PHASE_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * Rails have to be sequential, so we can abort after finding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * the first unconfigured rail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	info->pages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	for (i = 0; i < ret; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (!block_buffer[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		info->pages++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (!info->pages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		dev_err(&client->dev, "No rails configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	dev_info(&client->dev, "%d rails configured\n", info->pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * Set PHASE registers on all pages to 0xff to ensure that phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * specific commands will apply to all phases of a given page (rail).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * This only affects the READ_IOUT and READ_TEMPERATURE2 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 * READ_IOUT will return the sum of currents of all phases of a rail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 * and READ_TEMPERATURE2 will return the maximum temperature detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * for the the phases of the rail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	for (i = 0; i < info->pages; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 * Setting PAGE & PHASE fails once in a while for no obvious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		 * reason, so we need to retry a couple of times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		for (j = 0; j < 3; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			ret = i2c_smbus_write_byte_data(client, PMBUS_PHASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 							0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				"Failed to initialize PHASE registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (info->pages > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		i2c_smbus_write_byte_data(client, PMBUS_PAGE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	info->func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_STATUS_INPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			PMBUS_HAVE_IIN | PMBUS_HAVE_PIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			PMBUS_HAVE_POUT | PMBUS_HAVE_TEMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			PMBUS_HAVE_TEMP2 | PMBUS_HAVE_STATUS_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	for (i = 1; i < info->pages; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		info->func[i] = PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			PMBUS_HAVE_POUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			PMBUS_HAVE_TEMP2 | PMBUS_HAVE_STATUS_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* ucd9240 supports a single fan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (mid->driver_data == ucd9240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		info->func[0] |= PMBUS_HAVE_FAN12 | PMBUS_HAVE_STATUS_FAN12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return pmbus_do_probe(client, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* This is the driver that will be inserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct i2c_driver ucd9200_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.name = "ucd9200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.of_match_table = of_match_ptr(ucd9200_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.probe_new = ucd9200_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.remove = pmbus_do_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.id_table = ucd9200_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) module_i2c_driver(ucd9200_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_AUTHOR("Guenter Roeck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_DESCRIPTION("PMBus driver for TI UCD922x, UCD924x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_LICENSE("GPL");