^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pmbus.h - Common defines and structures for PMBus devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010, 2011 Ericsson AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2012 Guenter Roeck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef PMBUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PMBUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum pmbus_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PMBUS_PAGE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PMBUS_OPERATION = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PMBUS_ON_OFF_CONFIG = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PMBUS_CLEAR_FAULTS = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PMBUS_PHASE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PMBUS_WRITE_PROTECT = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PMBUS_CAPABILITY = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PMBUS_QUERY = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PMBUS_VOUT_MODE = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PMBUS_VOUT_COMMAND = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PMBUS_VOUT_TRIM = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PMBUS_VOUT_CAL_OFFSET = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PMBUS_VOUT_MAX = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PMBUS_VOUT_MARGIN_HIGH = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PMBUS_VOUT_MARGIN_LOW = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PMBUS_VOUT_TRANSITION_RATE = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PMBUS_VOUT_DROOP = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PMBUS_VOUT_SCALE_LOOP = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PMBUS_VOUT_SCALE_MONITOR = 0x2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PMBUS_COEFFICIENTS = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PMBUS_POUT_MAX = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PMBUS_FAN_CONFIG_12 = 0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PMBUS_FAN_COMMAND_1 = 0x3B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PMBUS_FAN_COMMAND_2 = 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PMBUS_FAN_CONFIG_34 = 0x3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PMBUS_FAN_COMMAND_3 = 0x3E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PMBUS_FAN_COMMAND_4 = 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PMBUS_VOUT_OV_FAULT_LIMIT = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PMBUS_VOUT_OV_FAULT_RESPONSE = 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PMBUS_VOUT_OV_WARN_LIMIT = 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PMBUS_VOUT_UV_WARN_LIMIT = 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PMBUS_VOUT_UV_FAULT_LIMIT = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PMBUS_VOUT_UV_FAULT_RESPONSE = 0x45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PMBUS_IOUT_OC_FAULT_LIMIT = 0x46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PMBUS_IOUT_OC_FAULT_RESPONSE = 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PMBUS_IOUT_OC_LV_FAULT_LIMIT = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PMBUS_IOUT_OC_LV_FAULT_RESPONSE = 0x49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PMBUS_IOUT_OC_WARN_LIMIT = 0x4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PMBUS_IOUT_UC_FAULT_LIMIT = 0x4B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PMBUS_IOUT_UC_FAULT_RESPONSE = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PMBUS_OT_FAULT_LIMIT = 0x4F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PMBUS_OT_FAULT_RESPONSE = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PMBUS_OT_WARN_LIMIT = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PMBUS_UT_WARN_LIMIT = 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PMBUS_UT_FAULT_LIMIT = 0x53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PMBUS_UT_FAULT_RESPONSE = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PMBUS_VIN_OV_FAULT_LIMIT = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PMBUS_VIN_OV_FAULT_RESPONSE = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PMBUS_VIN_OV_WARN_LIMIT = 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PMBUS_VIN_UV_WARN_LIMIT = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PMBUS_VIN_UV_FAULT_LIMIT = 0x59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PMBUS_IIN_OC_FAULT_LIMIT = 0x5B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PMBUS_IIN_OC_WARN_LIMIT = 0x5D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PMBUS_POUT_OP_FAULT_LIMIT = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PMBUS_POUT_OP_WARN_LIMIT = 0x6A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PMBUS_PIN_OP_WARN_LIMIT = 0x6B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PMBUS_STATUS_BYTE = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PMBUS_STATUS_WORD = 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PMBUS_STATUS_VOUT = 0x7A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PMBUS_STATUS_IOUT = 0x7B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PMBUS_STATUS_INPUT = 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PMBUS_STATUS_TEMPERATURE = 0x7D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PMBUS_STATUS_CML = 0x7E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PMBUS_STATUS_OTHER = 0x7F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PMBUS_STATUS_MFR_SPECIFIC = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PMBUS_STATUS_FAN_12 = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PMBUS_STATUS_FAN_34 = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PMBUS_READ_VIN = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PMBUS_READ_IIN = 0x89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PMBUS_READ_VCAP = 0x8A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PMBUS_READ_VOUT = 0x8B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PMBUS_READ_IOUT = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PMBUS_READ_TEMPERATURE_1 = 0x8D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PMBUS_READ_TEMPERATURE_2 = 0x8E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PMBUS_READ_TEMPERATURE_3 = 0x8F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PMBUS_READ_FAN_SPEED_1 = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PMBUS_READ_FAN_SPEED_2 = 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PMBUS_READ_FAN_SPEED_3 = 0x92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PMBUS_READ_FAN_SPEED_4 = 0x93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PMBUS_READ_DUTY_CYCLE = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PMBUS_READ_FREQUENCY = 0x95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PMBUS_READ_POUT = 0x96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PMBUS_READ_PIN = 0x97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PMBUS_REVISION = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PMBUS_MFR_ID = 0x99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PMBUS_MFR_MODEL = 0x9A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PMBUS_MFR_REVISION = 0x9B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PMBUS_MFR_LOCATION = 0x9C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PMBUS_MFR_DATE = 0x9D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PMBUS_MFR_SERIAL = 0x9E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PMBUS_MFR_VIN_MIN = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PMBUS_MFR_VIN_MAX = 0xA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PMBUS_MFR_IIN_MAX = 0xA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PMBUS_MFR_PIN_MAX = 0xA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PMBUS_MFR_VOUT_MIN = 0xA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PMBUS_MFR_VOUT_MAX = 0xA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PMBUS_MFR_IOUT_MAX = 0xA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PMBUS_MFR_POUT_MAX = 0xA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PMBUS_IC_DEVICE_ID = 0xAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PMBUS_IC_DEVICE_REV = 0xAE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PMBUS_MFR_MAX_TEMP_1 = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PMBUS_MFR_MAX_TEMP_2 = 0xC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PMBUS_MFR_MAX_TEMP_3 = 0xC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Virtual registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Useful to support attributes which are not supported by standard PMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * registers but exist as manufacturer specific registers on individual chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Must be mapped to real registers in device specific code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Semantics:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Virtual registers are all word size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * READ registers are read-only; writes are either ignored or return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * RESET registers are read/write. Reading reset registers returns zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * (used for detection), writing any value causes the associated history to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Virtual registers have to be handled in device specific driver code. Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * driver code returns non-negative register values if a virtual register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * supported, or a negative error code if not. The chip driver may return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * -ENODATA or any other error code in this case, though an error code other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * than -ENODATA is handled more efficiently and thus preferred. Either case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * the calling PMBus core code will abort if the chip driver returns an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * code when reading or writing virtual registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PMBUS_VIRT_BASE = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PMBUS_VIRT_READ_TEMP_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PMBUS_VIRT_READ_TEMP_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PMBUS_VIRT_READ_TEMP_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PMBUS_VIRT_RESET_TEMP_HISTORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PMBUS_VIRT_READ_VIN_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PMBUS_VIRT_READ_VIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PMBUS_VIRT_READ_VIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PMBUS_VIRT_RESET_VIN_HISTORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PMBUS_VIRT_READ_IIN_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PMBUS_VIRT_READ_IIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PMBUS_VIRT_READ_IIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PMBUS_VIRT_RESET_IIN_HISTORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PMBUS_VIRT_READ_PIN_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PMBUS_VIRT_READ_PIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PMBUS_VIRT_READ_PIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PMBUS_VIRT_RESET_PIN_HISTORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PMBUS_VIRT_READ_POUT_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PMBUS_VIRT_READ_POUT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PMBUS_VIRT_READ_POUT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PMBUS_VIRT_RESET_POUT_HISTORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PMBUS_VIRT_READ_VOUT_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PMBUS_VIRT_READ_VOUT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PMBUS_VIRT_READ_VOUT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PMBUS_VIRT_RESET_VOUT_HISTORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PMBUS_VIRT_READ_IOUT_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PMBUS_VIRT_READ_IOUT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PMBUS_VIRT_READ_IOUT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PMBUS_VIRT_RESET_IOUT_HISTORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PMBUS_VIRT_READ_TEMP2_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PMBUS_VIRT_READ_TEMP2_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PMBUS_VIRT_READ_TEMP2_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PMBUS_VIRT_RESET_TEMP2_HISTORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PMBUS_VIRT_READ_VMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PMBUS_VIRT_VMON_UV_WARN_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PMBUS_VIRT_VMON_OV_WARN_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PMBUS_VIRT_VMON_UV_FAULT_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PMBUS_VIRT_VMON_OV_FAULT_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PMBUS_VIRT_STATUS_VMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * RPM and PWM Fan control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Drivers wanting to expose PWM control must define the behaviour of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * PMBUS_VIRT_PWM_[1-4] and PMBUS_VIRT_PWM_ENABLE_[1-4] in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * {read,write}_word_data callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * pmbus core provides a default implementation for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * PMBUS_VIRT_FAN_TARGET_[1-4].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * TARGET, PWM and PWM_ENABLE members must be defined sequentially;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * pmbus core uses the difference between the provided register and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * it's _1 counterpart to calculate the FAN/PWM ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PMBUS_VIRT_FAN_TARGET_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PMBUS_VIRT_FAN_TARGET_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PMBUS_VIRT_FAN_TARGET_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PMBUS_VIRT_FAN_TARGET_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PMBUS_VIRT_PWM_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PMBUS_VIRT_PWM_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PMBUS_VIRT_PWM_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PMBUS_VIRT_PWM_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PMBUS_VIRT_PWM_ENABLE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PMBUS_VIRT_PWM_ENABLE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PMBUS_VIRT_PWM_ENABLE_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PMBUS_VIRT_PWM_ENABLE_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Samples for average
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Drivers wanting to expose functionality for changing the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * samples used for average values should implement support in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * {read,write}_word_data callback for either PMBUS_VIRT_SAMPLES if it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * applies to all types of measurements, or any number of specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * PMBUS_VIRT_*_SAMPLES registers to allow for individual control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PMBUS_VIRT_SAMPLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PMBUS_VIRT_IN_SAMPLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PMBUS_VIRT_CURR_SAMPLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PMBUS_VIRT_POWER_SAMPLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PMBUS_VIRT_TEMP_SAMPLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * OPERATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PB_OPERATION_CONTROL_ON BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * WRITE_PROTECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PB_WP_ALL BIT(7) /* all but WRITE_PROTECT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PB_WP_OP BIT(6) /* all but WP, OPERATION, PAGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PB_WP_VOUT BIT(5) /* all but WP, OPERATION, PAGE, VOUT, ON_OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PB_WP_ANY (PB_WP_ALL | PB_WP_OP | PB_WP_VOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * CAPABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PB_CAPABILITY_SMBALERT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PB_CAPABILITY_ERROR_CHECK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * VOUT_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PB_VOUT_MODE_MODE_MASK 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PB_VOUT_MODE_PARAM_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PB_VOUT_MODE_LINEAR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PB_VOUT_MODE_VID 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PB_VOUT_MODE_DIRECT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Fan configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define PB_FAN_2_PULSE_MASK (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PB_FAN_2_RPM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define PB_FAN_2_INSTALLED BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PB_FAN_1_PULSE_MASK (BIT(4) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PB_FAN_1_RPM BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PB_FAN_1_INSTALLED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) enum pmbus_fan_mode { percent = 0, rpm };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * STATUS_BYTE, STATUS_WORD (lower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PB_STATUS_NONE_ABOVE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PB_STATUS_CML BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PB_STATUS_TEMPERATURE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PB_STATUS_VIN_UV BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PB_STATUS_IOUT_OC BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define PB_STATUS_VOUT_OV BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PB_STATUS_OFF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PB_STATUS_BUSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * STATUS_WORD (upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define PB_STATUS_UNKNOWN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PB_STATUS_OTHER BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PB_STATUS_FANS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PB_STATUS_POWER_GOOD_N BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PB_STATUS_WORD_MFR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define PB_STATUS_INPUT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define PB_STATUS_IOUT_POUT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define PB_STATUS_VOUT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * STATUS_IOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define PB_POUT_OP_WARNING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define PB_POUT_OP_FAULT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define PB_POWER_LIMITING BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define PB_CURRENT_SHARE_FAULT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PB_IOUT_UC_FAULT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PB_IOUT_OC_WARNING BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define PB_IOUT_OC_LV_FAULT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define PB_IOUT_OC_FAULT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * STATUS_VOUT, STATUS_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define PB_VOLTAGE_VIN_OFF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define PB_VOLTAGE_UV_FAULT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PB_VOLTAGE_UV_WARNING BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PB_VOLTAGE_OV_WARNING BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define PB_VOLTAGE_OV_FAULT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * STATUS_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PB_PIN_OP_WARNING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PB_IIN_OC_WARNING BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PB_IIN_OC_FAULT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * STATUS_TEMPERATURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PB_TEMP_UT_FAULT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define PB_TEMP_UT_WARNING BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PB_TEMP_OT_WARNING BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PB_TEMP_OT_FAULT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * STATUS_FAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PB_FAN_AIRFLOW_WARNING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PB_FAN_AIRFLOW_FAULT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PB_FAN_FAN2_SPEED_OVERRIDE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PB_FAN_FAN1_SPEED_OVERRIDE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PB_FAN_FAN2_WARNING BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define PB_FAN_FAN1_WARNING BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define PB_FAN_FAN2_FAULT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PB_FAN_FAN1_FAULT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * CML_FAULT_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PB_CML_FAULT_OTHER_MEM_LOGIC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PB_CML_FAULT_OTHER_COMM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PB_CML_FAULT_PROCESSOR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PB_CML_FAULT_MEMORY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PB_CML_FAULT_PACKET_ERROR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PB_CML_FAULT_INVALID_DATA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PB_CML_FAULT_INVALID_COMMAND BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) enum pmbus_sensor_classes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PSC_VOLTAGE_IN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PSC_VOLTAGE_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PSC_CURRENT_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PSC_CURRENT_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PSC_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PSC_TEMPERATURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PSC_FAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PSC_PWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PSC_NUM_CLASSES /* Number of power sensor classes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PMBUS_PAGES 32 /* Per PMBus specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PMBUS_PHASES 8 /* Maximum number of phases per page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Functionality bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PMBUS_HAVE_VIN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PMBUS_HAVE_VCAP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PMBUS_HAVE_VOUT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PMBUS_HAVE_IIN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PMBUS_HAVE_IOUT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PMBUS_HAVE_PIN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PMBUS_HAVE_POUT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PMBUS_HAVE_FAN12 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define PMBUS_HAVE_FAN34 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define PMBUS_HAVE_TEMP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PMBUS_HAVE_TEMP2 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define PMBUS_HAVE_TEMP3 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define PMBUS_HAVE_STATUS_VOUT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define PMBUS_HAVE_STATUS_IOUT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define PMBUS_HAVE_STATUS_INPUT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define PMBUS_HAVE_STATUS_TEMP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PMBUS_HAVE_STATUS_FAN12 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PMBUS_HAVE_STATUS_FAN34 BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PMBUS_HAVE_VMON BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PMBUS_HAVE_STATUS_VMON BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PMBUS_HAVE_PWM12 BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PMBUS_HAVE_PWM34 BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PMBUS_HAVE_SAMPLES BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PMBUS_PHASE_VIRTUAL BIT(30) /* Phases on this page are virtual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PMBUS_PAGE_VIRTUAL BIT(31) /* Page is virtual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) enum pmbus_data_format { linear = 0, direct, vid };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct pmbus_driver_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int pages; /* Total number of pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u8 phases[PMBUS_PAGES]; /* Number of phases per page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) enum pmbus_data_format format[PSC_NUM_CLASSES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) enum vrm_version vrm_version[PMBUS_PAGES]; /* vrm version per page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Support one set of coefficients for each sensor type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Used for chips providing data in direct mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int m[PSC_NUM_CLASSES]; /* mantissa for direct data format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int b[PSC_NUM_CLASSES]; /* offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int R[PSC_NUM_CLASSES]; /* exponent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 func[PMBUS_PAGES]; /* Functionality, per page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 pfunc[PMBUS_PHASES];/* Functionality, per phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * The following functions map manufacturing specific register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * to PMBus standard register values. Specify only if mapping is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Functions return the register value (read) or zero (write) if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * successful. A return value of -ENODATA indicates that there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * manufacturer specific register, but that a standard PMBus register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * may exist. Any other negative return value indicates that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * register does not exist, and that no attempt should be made to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * the standard register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int (*read_byte_data)(struct i2c_client *client, int page, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int (*read_word_data)(struct i2c_client *client, int page, int phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int (*write_word_data)(struct i2c_client *client, int page, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u16 word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int (*write_byte)(struct i2c_client *client, int page, u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * The identify function determines supported PMBus functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * This function is only necessary if a chip driver supports multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * chips, and the chip functionality is not pre-determined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int (*identify)(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct pmbus_driver_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Regulator functionality, if supported by this chip driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int num_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) const struct regulator_desc *reg_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* custom attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) const struct attribute_group **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Regulator ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) extern const struct regulator_ops pmbus_regulator_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Macro for filling in array of struct regulator_desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PMBUS_REGULATOR(_name, _id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) [_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .name = (_name # _id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .id = (_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .of_match = of_match_ptr(_name # _id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .ops = &pmbus_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Function declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void pmbus_clear_cache(struct i2c_client *client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int pmbus_set_page(struct i2c_client *client, int page, int phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int pmbus_read_word_data(struct i2c_client *client, int page, int phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int pmbus_write_word_data(struct i2c_client *client, int page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u16 word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int pmbus_write_byte(struct i2c_client *client, int page, u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 mask, u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) void pmbus_clear_faults(struct i2c_client *client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) bool pmbus_check_byte_register(struct i2c_client *client, int page, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) bool pmbus_check_word_register(struct i2c_client *client, int page, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int pmbus_do_probe(struct i2c_client *client, struct pmbus_driver_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int pmbus_do_remove(struct i2c_client *client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) const struct pmbus_driver_info *pmbus_get_driver_info(struct i2c_client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int pmbus_get_fan_rate_device(struct i2c_client *client, int page, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) enum pmbus_fan_mode mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int pmbus_get_fan_rate_cached(struct i2c_client *client, int page, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) enum pmbus_fan_mode mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int pmbus_update_fan(struct i2c_client *client, int page, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 config, u8 mask, u16 command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct dentry *pmbus_get_debugfs_dir(struct i2c_client *client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #endif /* PMBUS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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