^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADM1266 - Cascadable Super Sequencer with Margin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Control and Fault Recording
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2020 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/crc8.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c-smbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "pmbus.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/timekeeping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADM1266_BLACKBOX_CONFIG 0xD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADM1266_PDIO_CONFIG 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADM1266_READ_STATE 0xD9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADM1266_READ_BLACKBOX 0xDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADM1266_SET_RTC 0xDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADM1266_GPIO_CONFIG 0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADM1266_BLACKBOX_INFO 0xE6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADM1266_PDIO_STATUS 0xE9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADM1266_GPIO_STATUS 0xEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* ADM1266 GPIO defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADM1266_GPIO_NR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADM1266_GPIO_FUNCTIONS(x) FIELD_GET(BIT(0), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADM1266_GPIO_INPUT_EN(x) FIELD_GET(BIT(2), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADM1266_GPIO_OUTPUT_EN(x) FIELD_GET(BIT(3), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADM1266_GPIO_OPEN_DRAIN(x) FIELD_GET(BIT(4), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* ADM1266 PDIO defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADM1266_PDIO_NR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADM1266_PDIO_PIN_CFG(x) FIELD_GET(GENMASK(15, 13), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADM1266_PDIO_GLITCH_FILT(x) FIELD_GET(GENMASK(12, 9), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADM1266_PDIO_OUT_CFG(x) FIELD_GET(GENMASK(2, 0), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADM1266_BLACKBOX_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADM1266_BLACKBOX_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADM1266_PMBUS_BLOCK_MAX 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct adm1266_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct pmbus_driver_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const char *gpio_names[ADM1266_GPIO_NR + ADM1266_PDIO_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct dentry *debugfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct nvmem_config nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 *dev_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct mutex buf_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 write_buf[ADM1266_PMBUS_BLOCK_MAX + 1] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 read_buf[ADM1266_PMBUS_BLOCK_MAX + 1] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct nvmem_cell_info adm1266_nvmem_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .name = "blackbox",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .offset = ADM1266_BLACKBOX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .bytes = 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DECLARE_CRC8_TABLE(pmbus_crc_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Different from Block Read as it sends data and waits for the slave to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * return a value dependent on that data. The protocol is simply a Write Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * followed by a Read Block without the Read-Block command field and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Write-Block STOP bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int adm1266_pmbus_block_xfer(struct adm1266_data *data, u8 cmd, u8 w_len, u8 *data_w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 *data_r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct i2c_msg msgs[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .flags = I2C_M_DMA_SAFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .buf = data->write_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .len = w_len + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .flags = I2C_M_RD | I2C_M_DMA_SAFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .buf = data->read_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .len = ADM1266_PMBUS_BLOCK_MAX + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mutex_lock(&data->buf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) msgs[0].buf[0] = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) msgs[0].buf[1] = w_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) memcpy(&msgs[0].buf[2], data_w, w_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = i2c_transfer(client->adapter, msgs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mutex_unlock(&data->buf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (client->flags & I2C_CLIENT_PEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) addr = i2c_8bit_addr_from_msg(&msgs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) crc = crc8(pmbus_crc_table, &addr, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) crc = crc8(pmbus_crc_table, msgs[0].buf, msgs[0].len, crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) addr = i2c_8bit_addr_from_msg(&msgs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) crc = crc8(pmbus_crc_table, &addr, 1, crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) crc = crc8(pmbus_crc_table, msgs[1].buf, msgs[1].buf[0] + 1, crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (crc != msgs[1].buf[msgs[1].buf[0] + 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mutex_unlock(&data->buf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) memcpy(data_r, &msgs[1].buf[1], msgs[1].buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = msgs[1].buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mutex_unlock(&data->buf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const unsigned int adm1266_gpio_mapping[ADM1266_GPIO_NR][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {2, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {3, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {4, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {5, 9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {6, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {7, 11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {8, 6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {9, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const char *adm1266_names[ADM1266_GPIO_NR + ADM1266_PDIO_NR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5", "GPIO6", "GPIO7", "GPIO8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "GPIO9", "PDIO1", "PDIO2", "PDIO3", "PDIO4", "PDIO5", "PDIO6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "PDIO7", "PDIO8", "PDIO9", "PDIO10", "PDIO11", "PDIO12", "PDIO13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "PDIO14", "PDIO15", "PDIO16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int adm1266_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct adm1266_data *data = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 read_buf[I2C_SMBUS_BLOCK_MAX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long pins_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int pmbus_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (offset < ADM1266_GPIO_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pmbus_cmd = ADM1266_GPIO_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pmbus_cmd = ADM1266_PDIO_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = i2c_smbus_read_block_data(data->client, pmbus_cmd, read_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pins_status = read_buf[0] + (read_buf[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (offset < ADM1266_GPIO_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return test_bit(adm1266_gpio_mapping[offset][1], &pins_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return test_bit(offset - ADM1266_GPIO_NR, &pins_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int adm1266_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct adm1266_data *data = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 read_buf[ADM1266_PMBUS_BLOCK_MAX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int gpio_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = i2c_smbus_read_block_data(data->client, ADM1266_GPIO_STATUS, read_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) status = read_buf[0] + (read_buf[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for_each_set_bit(gpio_nr, mask, ADM1266_GPIO_NR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (test_bit(adm1266_gpio_mapping[gpio_nr][1], &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) set_bit(gpio_nr, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = i2c_smbus_read_block_data(data->client, ADM1266_PDIO_STATUS, read_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) status = read_buf[0] + (read_buf[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for_each_set_bit_from(gpio_nr, mask, ADM1266_GPIO_NR + ADM1266_PDIO_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (test_bit(gpio_nr - ADM1266_GPIO_NR, &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) set_bit(gpio_nr, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void adm1266_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct adm1266_data *data = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 read_buf[ADM1266_PMBUS_BLOCK_MAX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long gpio_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long pdio_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long pin_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 write_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (i = 0; i < ADM1266_GPIO_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) write_cmd = adm1266_gpio_mapping[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = adm1266_pmbus_block_xfer(data, ADM1266_GPIO_CONFIG, 1, &write_cmd, read_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) gpio_config = read_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) seq_puts(s, adm1266_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) seq_puts(s, " ( ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!ADM1266_GPIO_FUNCTIONS(gpio_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) seq_puts(s, "high-Z )\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ADM1266_GPIO_INPUT_EN(gpio_config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) seq_puts(s, "input ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ADM1266_GPIO_OUTPUT_EN(gpio_config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) seq_puts(s, "output ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ADM1266_GPIO_OPEN_DRAIN(gpio_config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) seq_puts(s, "open-drain )\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) seq_puts(s, "push-pull )\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) write_cmd = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = adm1266_pmbus_block_xfer(data, ADM1266_PDIO_CONFIG, 1, &write_cmd, read_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret != 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (i = 0; i < ADM1266_PDIO_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) seq_puts(s, adm1266_names[ADM1266_GPIO_NR + i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pdio_config = read_buf[2 * i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pdio_config += (read_buf[2 * i + 1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pin_cfg = ADM1266_PDIO_PIN_CFG(pdio_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) seq_puts(s, " ( ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!pin_cfg || pin_cfg > 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) seq_puts(s, "high-Z )\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (pin_cfg & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) seq_puts(s, "output ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (pin_cfg & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) seq_puts(s, "input ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) seq_puts(s, ")\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int adm1266_config_gpio(struct adm1266_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const char *name = dev_name(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) char *gpio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) for (i = 0; i < ARRAY_SIZE(data->gpio_names); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) gpio_name = devm_kasprintf(&data->client->dev, GFP_KERNEL, "adm1266-%x-%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) data->client->addr, adm1266_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!gpio_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) data->gpio_names[i] = gpio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) data->gc.label = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) data->gc.parent = &data->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) data->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) data->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) data->gc.names = data->gpio_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) data->gc.ngpio = ARRAY_SIZE(data->gpio_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) data->gc.get = adm1266_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) data->gc.get_multiple = adm1266_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) data->gc.dbg_show = adm1266_gpio_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = devm_gpiochip_add_data(&data->client->dev, &data->gc, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(&data->client->dev, "GPIO registering failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int adm1266_state_read(struct seq_file *s, void *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct device *dev = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = i2c_smbus_read_word_data(client, ADM1266_READ_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) seq_printf(s, "%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void adm1266_init_debugfs(struct adm1266_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct dentry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) root = pmbus_get_debugfs_dir(data->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!root)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) data->debugfs_dir = debugfs_create_dir(data->client->name, root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!data->debugfs_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) debugfs_create_devm_seqfile(&data->client->dev, "sequencer_state", data->debugfs_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) adm1266_state_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int adm1266_nvmem_read_blackbox(struct adm1266_data *data, u8 *read_buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int record_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) char index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 buf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = i2c_smbus_read_block_data(data->client, ADM1266_BLACKBOX_INFO, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) record_count = buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) for (index = 0; index < record_count; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = adm1266_pmbus_block_xfer(data, ADM1266_READ_BLACKBOX, 1, &index, read_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret != ADM1266_BLACKBOX_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) read_buff += ADM1266_BLACKBOX_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int adm1266_nvmem_read(void *priv, unsigned int offset, void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct adm1266_data *data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (offset + bytes > data->nvmem_config.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (offset == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) memset(data->dev_mem, 0, data->nvmem_config.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = adm1266_nvmem_read_blackbox(data, data->dev_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(&data->client->dev, "Could not read blackbox!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) memcpy(val, data->dev_mem + offset, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int adm1266_config_nvmem(struct adm1266_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) data->nvmem_config.name = dev_name(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) data->nvmem_config.dev = &data->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) data->nvmem_config.root_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) data->nvmem_config.read_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) data->nvmem_config.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) data->nvmem_config.reg_read = adm1266_nvmem_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) data->nvmem_config.cells = adm1266_nvmem_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) data->nvmem_config.ncells = ARRAY_SIZE(adm1266_nvmem_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) data->nvmem_config.priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) data->nvmem_config.stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) data->nvmem_config.word_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) data->nvmem_config.size = adm1266_nvmem_cells[0].bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) data->dev_mem = devm_kzalloc(&data->client->dev, data->nvmem_config.size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!data->dev_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) data->nvmem = devm_nvmem_register(&data->client->dev, &data->nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (IS_ERR(data->nvmem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_err(&data->client->dev, "Could not register nvmem!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return PTR_ERR(data->nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int adm1266_set_rtc(struct adm1266_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) time64_t kt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) char write_buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) kt = ktime_get_seconds();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) memset(write_buf, 0, sizeof(write_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) write_buf[2 + i] = (kt >> (i * 8)) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return i2c_smbus_write_block_data(data->client, ADM1266_SET_RTC, sizeof(write_buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) write_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int adm1266_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct adm1266_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) data = devm_kzalloc(&client->dev, sizeof(struct adm1266_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) data->info.pages = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) data->info.format[PSC_VOLTAGE_OUT] = linear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) for (i = 0; i < data->info.pages; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) data->info.func[i] = PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) crc8_populate_msb(pmbus_crc_table, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mutex_init(&data->buf_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = adm1266_config_gpio(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = adm1266_set_rtc(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = adm1266_config_nvmem(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = pmbus_do_probe(client, &data->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) adm1266_init_debugfs(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct of_device_id adm1266_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { .compatible = "adi,adm1266" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MODULE_DEVICE_TABLE(of, adm1266_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const struct i2c_device_id adm1266_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { "adm1266", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MODULE_DEVICE_TABLE(i2c, adm1266_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct i2c_driver adm1266_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .name = "adm1266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .of_match_table = adm1266_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .probe_new = adm1266_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .remove = pmbus_do_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .id_table = adm1266_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) module_i2c_driver(adm1266_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_AUTHOR("Alexandru Tachici <alexandru.tachici@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_DESCRIPTION("PMBus driver for Analog Devices ADM1266");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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