^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2014-2018 Nuvoton Technology corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* NPCM7XX PWM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NPCM7XX_PWM_REG_CMRx(base, n, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NPCM7XX_PWM_REG_PDRx(base, n, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Define the maximum PWM channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NPCM7XX_PWM_MAX_CHN_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NPCM7XX_PWM_MAX_MODULES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Define the Counter Register, value = 100 for match 100% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NPCM7XX_PWM_CMR_DEFAULT_NUM 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NPCM7XX_PWM_CMR_MAX 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* default all PWM channels PRESCALE2 = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PWM_OUTPUT_FREQ_25KHZ 25000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PWN_CNT_DEFAULT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MIN_PRESCALE1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) NPCM7XX_PWM_CTRL_CH3_MODE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* NPCM7XX FAN Tacho registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define NPCM7XX_FAN_TCKC_CLKX_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define NPCM7XX_FAN_TMCTRL_TBEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NPCM7XX_FAN_TMCTRL_TAEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define NPCM7XX_FAN_TICLR_TFCLR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NPCM7XX_FAN_TICLR_TECLR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NPCM7XX_FAN_TICLR_TDCLR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NPCM7XX_FAN_TICLR_TCCLR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NPCM7XX_FAN_TICLR_TBCLR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NPCM7XX_FAN_TICLR_TACLR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NPCM7XX_FAN_TIEN_TFIEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define NPCM7XX_FAN_TIEN_TEIEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define NPCM7XX_FAN_TIEN_TDIEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define NPCM7XX_FAN_TIEN_TCIEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define NPCM7XX_FAN_TIEN_TBIEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NPCM7XX_FAN_TIEN_TAIEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define NPCM7XX_FAN_TICTRL_TFPND BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define NPCM7XX_FAN_TICTRL_TEPND BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define NPCM7XX_FAN_TICTRL_TDPND BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define NPCM7XX_FAN_TICTRL_TCPND BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define NPCM7XX_FAN_TICTRL_TBPND BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define NPCM7XX_FAN_TICTRL_TAPND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* FAN General Definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Define the maximum FAN channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define NPCM7XX_FAN_MAX_MODULE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define NPCM7XX_FAN_MAX_CHN_NUM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Timeout 94ms ~= 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * (The minimum FAN speed could to support ~640RPM/pulse 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * 320RPM/pulse 2, ...-- 10.6Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define NPCM7XX_FAN_TIMEOUT 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define NPCM7XX_FAN_TCNT 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define NPCM7XX_FAN_POLL_TIMER_200MS 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define NPCM7XX_FAN_CLK_PRESCALE 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define NPCM7XX_FAN_CMPA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define NPCM7XX_FAN_CMPB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Obtain the fan number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* fan sample status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FAN_DISABLE 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FAN_INIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FAN_ENOUGH_SAMPLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct npcm7xx_fan_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 fan_st_flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 fan_pls_per_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 fan_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 fan_cnt_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct npcm7xx_cooling_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) char name[THERMAL_NAME_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct npcm7xx_pwm_fan_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct thermal_cooling_device *tcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int pwm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 *cooling_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 max_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct npcm7xx_pwm_fan_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void __iomem *pwm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void __iomem *fan_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long pwm_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long fan_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk *pwm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct clk *fan_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct mutex pwm_lock[NPCM7XX_PWM_MAX_MODULES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int fan_irq[NPCM7XX_FAN_MAX_MODULE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 input_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct timer_list fan_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 fan_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int channel, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 tmp_buf, ctrl_en_bit, env_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Config PWM Comparator register for setting duty cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mutex_lock(&data->pwm_lock[module]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* write new CMR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) switch (pwm_ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mutex_unlock(&data->pwm_lock[module]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Disable PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) tmp_buf &= ~ctrl_en_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tmp_buf |= env_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Enable PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tmp_buf |= ctrl_en_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tmp_buf &= ~env_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mutex_unlock(&data->pwm_lock[module]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 fan, u8 cmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 fan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 reg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 reg_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* to check whether any fan tach is enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_lock_irqsave(&data->fan_lock[fan], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * the interrupt enable bits do not need to be cleared before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * it sets, the interrupt enable bits are cleared only on reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * the clock unit control register is behaving in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * manner that the interrupt enable register behave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (cmp == NPCM7XX_FAN_CMPA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) NPCM7XX_FAN_TIEN_TEIEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* start to Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) NPCM7XX_FAN_TIEN_TFIEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reg_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) NPCM7XX_FAN_TCKC_CLK2_APB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* start to Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) iowrite8(reg_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) spin_unlock_irqrestore(&data->fan_lock[fan], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Enable a background timer to poll fan tach value, (200ms * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * to polling all fan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void npcm7xx_fan_polling(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct npcm7xx_pwm_fan_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) data = from_timer(data, t, fan_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Polling two module per one round,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) i = i + 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* clear the flag and reset the counter (TCNT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) NPCM7XX_FAN_REG_TICLR(data->fan_base, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (data->fan_present[i * 2]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) iowrite16(NPCM7XX_FAN_TCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) NPCM7XX_FAN_REG_TCNT1(data->fan_base, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (data->fan_present[(i * 2) + 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) iowrite16(NPCM7XX_FAN_TCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) NPCM7XX_FAN_REG_TCNT2(data->fan_base, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) data->fan_select++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) data->fan_select &= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* reset the timer interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) data->fan_timer.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) add_timer(&data->fan_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 fan, u8 cmp, u8 fan_id, u8 flag_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 flag_mode, u8 flag_clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 reg_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 reg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u16 fan_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (cmp == NPCM7XX_FAN_CMPA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* First capture, drop it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) data->fan_dev[fan_id].fan_st_flg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FAN_PREPARE_TO_GET_FIRST_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* reset counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) data->fan_dev[fan_id].fan_cnt_tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * collect the enough sample,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * (ex: 2 pulse fan need to get 2 sample)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) data->fan_dev[fan_id].fan_cnt_tmp +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) (NPCM7XX_FAN_TCNT - fan_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) data->fan_dev[fan_id].fan_st_flg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* get enough sample or fan disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) data->fan_dev[fan_id].fan_cnt_tmp +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) (NPCM7XX_FAN_TCNT - fan_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* compute finial average cnt per pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) data->fan_dev[fan_id].fan_cnt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) data->fan_dev[fan_id].fan_cnt_tmp /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) FAN_ENOUGH_SAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) iowrite8((reg_int & ~flag_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* stop capturing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) iowrite8((reg_mode & ~flag_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u8 fan, u8 cmp, u8 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u8 reg_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u8 reg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u8 flag_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u8 flag_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u8 flag_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u8 flag_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u8 flag_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 fan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fan_id = NPCM7XX_FAN_INPUT(fan, cmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (cmp == NPCM7XX_FAN_CMPA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) flag_cap = NPCM7XX_FAN_TICTRL_TAPND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) flag_timeout = NPCM7XX_FAN_TICTRL_TEPND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) flag_cap = NPCM7XX_FAN_TICTRL_TBPND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) flag_timeout = NPCM7XX_FAN_TICTRL_TFPND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (flag & flag_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) iowrite8((reg_int & ~flag_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* clear interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) iowrite8(flag_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* stop capturing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) iowrite8((reg_mode & ~flag_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * connect or speed is lower than 10.6Hz (320RPM/pulse2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * In these situation, the RPM output should be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) data->fan_dev[fan_id].fan_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* input capture is occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (flag & flag_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) flag_mode, flag_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct npcm7xx_pwm_fan_data *data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) module = irq - data->fan_irq[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) spin_lock_irqsave(&data->fan_lock[module], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (flag > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) spin_unlock_irqrestore(&data->fan_lock[module], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) spin_unlock_irqrestore(&data->fan_lock[module], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case hwmon_pwm_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *val = ioread32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case hwmon_pwm_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (val < 0 || val > NPCM7XX_PWM_CMR_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) err = npcm7xx_pwm_config_set(data, channel, (u16)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) const struct npcm7xx_pwm_fan_data *data = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!data->pwm_present[channel])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case hwmon_pwm_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case hwmon_fan_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (data->fan_dev[channel].fan_cnt <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return data->fan_dev[channel].fan_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Convert the raw reading to RPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (data->fan_dev[channel].fan_cnt > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) data->fan_dev[channel].fan_pls_per_rev > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *val = ((data->input_clk_freq * 60) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) (data->fan_dev[channel].fan_cnt *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) data->fan_dev[channel].fan_pls_per_rev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) const struct npcm7xx_pwm_fan_data *data = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!data->fan_present[channel])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case hwmon_fan_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case hwmon_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return npcm7xx_read_pwm(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case hwmon_fan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return npcm7xx_read_fan(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case hwmon_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return npcm7xx_write_pwm(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static umode_t npcm7xx_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case hwmon_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return npcm7xx_pwm_is_visible(data, attr, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case hwmon_fan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return npcm7xx_fan_is_visible(data, attr, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const struct hwmon_channel_info *npcm7xx_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) HWMON_CHANNEL_INFO(pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) HWMON_PWM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) HWMON_PWM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) HWMON_PWM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) HWMON_PWM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) HWMON_PWM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) HWMON_PWM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) HWMON_PWM_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) HWMON_PWM_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) HWMON_CHANNEL_INFO(fan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) HWMON_F_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) HWMON_F_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const struct hwmon_ops npcm7xx_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .is_visible = npcm7xx_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .read = npcm7xx_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .write = npcm7xx_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const struct hwmon_chip_info npcm7xx_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .ops = &npcm7xx_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .info = npcm7xx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int m, ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 prescale_val, output_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) data->pwm_clk_freq = clk_get_rate(data->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Adjust NPCM7xx PWMs output frequency to ~25Khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) output_freq = data->pwm_clk_freq / PWN_CNT_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* If prescale_val = 0, then the prescale output clock is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (prescale_val < MIN_PRESCALE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) prescale_val = MIN_PRESCALE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * prescale_val need to decrement in one because in the PWM Prescale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * register the Prescale value increment by one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) prescale_val--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Setting PWM Prescale Register value register to both modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) for (m = 0; m < NPCM7XX_PWM_MAX_MODULES ; m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) NPCM7XX_PWM_REG_CSR(data->pwm_base, m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) NPCM7XX_PWM_REG_CR(data->pwm_base, m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return output_freq / ((prescale_val & 0xf) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 apb_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* stop FAN0~7 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) NPCM7XX_FAN_REG_TCKC(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* disable all interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* clear all interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) NPCM7XX_FAN_REG_TICLR(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* set FAN0~7 clock prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) iowrite8(NPCM7XX_FAN_CLK_PRESCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) NPCM7XX_FAN_REG_TPRSC(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* set FAN0~7 mode (high-to-low transition) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) NPCM7XX_FAN_TMCTRL_TAEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* set FAN0~7 Initial Count/Cap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) iowrite16(NPCM7XX_FAN_TCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) NPCM7XX_FAN_REG_TCNT1(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) iowrite16(NPCM7XX_FAN_TCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) NPCM7XX_FAN_REG_TCNT2(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* set FAN0~7 compare (equal to count) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* set FAN0~7 compare value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) iowrite16(NPCM7XX_FAN_TCPA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) NPCM7XX_FAN_REG_TCPA(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) iowrite16(NPCM7XX_FAN_TCPB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) NPCM7XX_FAN_REG_TCPB(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* set FAN0~7 fan input FANIN 0~15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) NPCM7XX_FAN_REG_TINASEL(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) data->fan_dev[ch].fan_st_flg = FAN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) data->fan_dev[ch].fan_pls_per_rev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) data->fan_dev[ch].fan_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) apb_clk_freq = clk_get_rate(data->fan_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Fan tach input clock = APB clock / prescalar, default is 255. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned long *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct npcm7xx_cooling_device *cdev = tcdev->devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) *state = cdev->max_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) unsigned long *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct npcm7xx_cooling_device *cdev = tcdev->devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) *state = cdev->cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) unsigned long state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct npcm7xx_cooling_device *cdev = tcdev->devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (state > cdev->max_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) cdev->cur_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) cdev->cooling_levels[cdev->cur_state]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .get_max_state = npcm7xx_pwm_cz_get_max_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .get_cur_state = npcm7xx_pwm_cz_get_cur_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .set_cur_state = npcm7xx_pwm_cz_set_cur_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int npcm7xx_create_pwm_cooling(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct device_node *child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct npcm7xx_pwm_fan_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 pwm_port, u8 num_levels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct npcm7xx_cooling_device *cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!cdev->cooling_levels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) cdev->max_state = num_levels - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ret = of_property_read_u8_array(child, "cooling-levels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) cdev->cooling_levels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) num_levels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pwm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) cdev->name, cdev, &npcm7xx_pwm_cool_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (IS_ERR(cdev->tcdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return PTR_ERR(cdev->tcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) cdev->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) cdev->pwm_port = pwm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) data->cdev[pwm_port] = cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int npcm7xx_en_pwm_fan(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct device_node *child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct npcm7xx_pwm_fan_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u8 *fan_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 pwm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int ret, fan_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u8 index, ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ret = of_property_read_u32(child, "reg", &pwm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) data->pwm_present[pwm_port] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = npcm7xx_pwm_config_set(data, pwm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) NPCM7XX_PWM_CMR_DEFAULT_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ret = of_property_count_u8_elems(child, "cooling-levels");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (fan_cnt < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!fan_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) for (ch = 0; ch < fan_cnt; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) index = fan_ch[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) data->fan_present[index] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) data->fan_dev[index].fan_st_flg = FAN_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct device_node *np, *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct npcm7xx_pwm_fan_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct device *hwmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) char name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int ret, cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u32 output_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev_err(dev, "pwm resource not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) data->pwm_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dev_dbg(dev, "pwm base resource is %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (IS_ERR(data->pwm_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return PTR_ERR(data->pwm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) data->pwm_clk = devm_clk_get(dev, "pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (IS_ERR(data->pwm_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dev_err(dev, "couldn't get pwm clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return PTR_ERR(data->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_err(dev, "fan resource not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) data->fan_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_dbg(dev, "fan base resource is %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (IS_ERR(data->fan_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return PTR_ERR(data->fan_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) data->fan_clk = devm_clk_get(dev, "fan");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (IS_ERR(data->fan_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dev_err(dev, "couldn't get fan clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return PTR_ERR(data->fan_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) output_freq = npcm7xx_pwm_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) npcm7xx_fan_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) for (cnt = 0; cnt < NPCM7XX_PWM_MAX_MODULES ; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) mutex_init(&data->pwm_lock[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) spin_lock_init(&data->fan_lock[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) data->fan_irq[i] = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (data->fan_irq[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return data->fan_irq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) sprintf(name, "NPCM7XX-FAN-MD%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) 0, name, (void *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_err(dev, "register IRQ fan%d failed\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = npcm7xx_en_pwm_fan(dev, child, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_err(dev, "enable pwm and fan failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) data, &npcm7xx_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (IS_ERR(hwmon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_err(dev, "unable to register hwmon device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return PTR_ERR(hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (data->fan_present[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* fan timer initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) data->fan_timer.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) timer_setup(&data->fan_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) npcm7xx_fan_polling, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) add_timer(&data->fan_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) output_freq, data->input_clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static const struct of_device_id of_pwm_fan_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) { .compatible = "nuvoton,npcm750-pwm-fan", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static struct platform_driver npcm7xx_pwm_fan_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .probe = npcm7xx_pwm_fan_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .name = "npcm7xx_pwm_fan",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .of_match_table = of_pwm_fan_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) module_platform_driver(npcm7xx_pwm_fan_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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