Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Hardware monitoring driver for Maxim MAX6621
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2017 Vadim Pasternak <vadimp@mellanox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MAX6621_DRV_NAME		"max6621"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MAX6621_TEMP_INPUT_REG_NUM	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MAX6621_TEMP_INPUT_MIN		-127000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MAX6621_TEMP_INPUT_MAX		128000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MAX6621_TEMP_ALERT_CHAN_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MAX6621_TEMP_S0D0_REG		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MAX6621_TEMP_S0D1_REG		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MAX6621_TEMP_S1D0_REG		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MAX6621_TEMP_S1D1_REG		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAX6621_TEMP_S2D0_REG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MAX6621_TEMP_S2D1_REG		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MAX6621_TEMP_S3D0_REG		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MAX6621_TEMP_S3D1_REG		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MAX6621_TEMP_MAX_REG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MAX6621_TEMP_MAX_ADDR_REG	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MAX6621_TEMP_ALERT_CAUSE_REG	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MAX6621_CONFIG0_REG		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MAX6621_CONFIG1_REG		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MAX6621_CONFIG2_REG		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MAX6621_CONFIG3_REG		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MAX6621_TEMP_S0_ALERT_REG	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MAX6621_TEMP_S1_ALERT_REG	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MAX6621_TEMP_S2_ALERT_REG	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MAX6621_TEMP_S3_ALERT_REG	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MAX6621_CLEAR_ALERT_REG		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MAX6621_REG_MAX			(MAX6621_CLEAR_ALERT_REG + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MAX6621_REG_TEMP_SHIFT		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MAX6621_ENABLE_TEMP_ALERTS_BIT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MAX6621_ENABLE_I2C_CRC_BIT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MAX6621_ENABLE_ALTERNATE_DATA	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MAX6621_ENABLE_LOCKUP_TO	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MAX6621_ENABLE_S0D0_BIT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MAX6621_ENABLE_S3D1_BIT		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MAX6621_ENABLE_TEMP_ALL		GENMASK(MAX6621_ENABLE_S3D1_BIT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 						MAX6621_ENABLE_S0D0_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MAX6621_POLL_DELAY_MASK		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MAX6621_CONFIG0_INIT		(MAX6621_ENABLE_TEMP_ALL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					 BIT(MAX6621_ENABLE_LOCKUP_TO) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 					 BIT(MAX6621_ENABLE_I2C_CRC_BIT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 					 MAX6621_POLL_DELAY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MAX6621_PECI_BIT_TIME		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MAX6621_PECI_RETRY_NUM		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MAX6621_CONFIG1_INIT		((MAX6621_PECI_BIT_TIME << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 					 MAX6621_PECI_RETRY_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* Error codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MAX6621_TRAN_FAILED	0x8100	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 					 * PECI transaction failed for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 					 * than the configured number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 					 * consecutive retries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MAX6621_POOL_DIS	0x8101	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 					 * Polling disabled for requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 					 * socket/domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MAX6621_POOL_UNCOMPLETE	0x8102	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 					 * First poll not yet completed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					 * requested socket/domain (on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 					 * startup).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MAX6621_SD_DIS		0x8103	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 					 * Read maximum temperature requested,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 					 * but no sockets/domains enabled or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 					 * all enabled sockets/domains have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 					 * errors; or read maximum temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 					 * address requested, but read maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 					 * temperature was not called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MAX6621_ALERT_DIS	0x8104	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 					 * Get alert socket/domain requested,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 					 * but no alert active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MAX6621_PECI_ERR_MIN	0x8000	/* Intel spec PECI error min value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MAX6621_PECI_ERR_MAX	0x80ff	/* Intel spec PECI error max value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static const u32 max6621_temp_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	MAX6621_TEMP_MAX_REG, MAX6621_TEMP_S0D0_REG, MAX6621_TEMP_S1D0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	MAX6621_TEMP_S2D0_REG, MAX6621_TEMP_S3D0_REG, MAX6621_TEMP_S0D1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	MAX6621_TEMP_S1D1_REG, MAX6621_TEMP_S2D1_REG, MAX6621_TEMP_S3D1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char *const max6621_temp_labels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	"maximum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	"socket0_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	"socket1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	"socket2_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	"socket3_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	"socket0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	"socket1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	"socket2_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	"socket3_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const int max6621_temp_alert_chan2reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	MAX6621_TEMP_S0_ALERT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	MAX6621_TEMP_S1_ALERT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	MAX6621_TEMP_S2_ALERT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	MAX6621_TEMP_S3_ALERT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * struct max6621_data - private data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * @client: I2C client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * @regmap: register map handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * @input_chan2reg: mapping from channel to register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct max6621_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct i2c_client	*client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct regmap		*regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	int			input_chan2reg[MAX6621_TEMP_INPUT_REG_NUM + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static long max6621_temp_mc2reg(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return (val / 1000L) << MAX6621_REG_TEMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static umode_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) max6621_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		   int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/* Skip channels which are not physically conncted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (((struct max6621_data *)data)->input_chan2reg[channel] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		case hwmon_temp_label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int max6621_verify_reg_data(struct device *dev, int regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (regval >= MAX6621_PECI_ERR_MIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	    regval <= MAX6621_PECI_ERR_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		dev_dbg(dev, "PECI error code - err 0x%04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	switch (regval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case MAX6621_TRAN_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		dev_dbg(dev, "PECI transaction failed - err 0x%04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	case MAX6621_POOL_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		dev_dbg(dev, "Polling disabled - err 0x%04x.\n", regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	case MAX6621_POOL_UNCOMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		dev_dbg(dev, "First poll not completed on startup - err 0x%04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	case MAX6621_SD_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		dev_dbg(dev, "Resource is disabled - err 0x%04x.\n", regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case MAX6621_ALERT_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		dev_dbg(dev, "No alert active - err 0x%04x.\n", regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) max6621_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	     int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct max6621_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	s8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			reg = data->input_chan2reg[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			ret = regmap_read(data->regmap, reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			ret = max6621_verify_reg_data(dev, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			 * Bit MAX6621_REG_TEMP_SHIFT represents 1 degree step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			 * The temperature is given in two's complement and 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			 * bits is used for the register conversion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			temp = (regval >> MAX6621_REG_TEMP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			*val = temp * 1000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			ret = regmap_read(data->regmap, MAX6621_CONFIG2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					  &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			ret = max6621_verify_reg_data(dev, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			*val = (regval >> MAX6621_REG_TEMP_SHIFT) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			       1000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			channel -= MAX6621_TEMP_ALERT_CHAN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			reg = max6621_temp_alert_chan2reg[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			ret = regmap_read(data->regmap, reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			ret = max6621_verify_reg_data(dev, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			*val = regval * 1000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			 * Set val to zero to recover the case, when reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			 * MAX6621_TEMP_ALERT_CAUSE_REG results in for example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			 * MAX6621_ALERT_DIS. Reading will return with error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			 * but in such case alarm should be returned as 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			ret = regmap_read(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 					  MAX6621_TEMP_ALERT_CAUSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 					  &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			ret = max6621_verify_reg_data(dev, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				/* Do not report error if alert is disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				if (regval == MAX6621_ALERT_DIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 					return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 					return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			 * Clear the alert automatically, using send-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			 * smbus protocol for clearing alert.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			if (regval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				ret = i2c_smbus_write_byte(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 						MAX6621_CLEAR_ALERT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 					return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			*val = !!regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) max6621_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	      int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct max6621_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			/* Clamp to allowed range to prevent overflow. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			val = clamp_val(val, MAX6621_TEMP_INPUT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 					MAX6621_TEMP_INPUT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			val = max6621_temp_mc2reg(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			return regmap_write(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 					    MAX6621_CONFIG2_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			channel -= MAX6621_TEMP_ALERT_CHAN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			reg = max6621_temp_alert_chan2reg[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			/* Clamp to allowed range to prevent overflow. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			val = clamp_val(val, MAX6621_TEMP_INPUT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 					MAX6621_TEMP_INPUT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			val = val / 1000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			return regmap_write(data->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) max6621_read_string(struct device *dev, enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		    int channel, const char **str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		case hwmon_temp_label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			*str = max6621_temp_labels[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static bool max6621_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	case MAX6621_CONFIG0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	case MAX6621_CONFIG1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	case MAX6621_CONFIG2_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	case MAX6621_CONFIG3_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	case MAX6621_TEMP_S0_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	case MAX6621_TEMP_S1_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	case MAX6621_TEMP_S2_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	case MAX6621_TEMP_S3_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	case MAX6621_TEMP_ALERT_CAUSE_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static bool max6621_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	case MAX6621_TEMP_S0D0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	case MAX6621_TEMP_S0D1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	case MAX6621_TEMP_S1D0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	case MAX6621_TEMP_S1D1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	case MAX6621_TEMP_S2D0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	case MAX6621_TEMP_S2D1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	case MAX6621_TEMP_S3D0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	case MAX6621_TEMP_S3D1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	case MAX6621_TEMP_MAX_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	case MAX6621_TEMP_MAX_ADDR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	case MAX6621_CONFIG0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	case MAX6621_CONFIG1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	case MAX6621_CONFIG2_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	case MAX6621_CONFIG3_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	case MAX6621_TEMP_S0_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	case MAX6621_TEMP_S1_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	case MAX6621_TEMP_S2_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	case MAX6621_TEMP_S3_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static bool max6621_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	case MAX6621_TEMP_S0D0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	case MAX6621_TEMP_S0D1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	case MAX6621_TEMP_S1D0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	case MAX6621_TEMP_S1D1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	case MAX6621_TEMP_S2D0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	case MAX6621_TEMP_S2D1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	case MAX6621_TEMP_S3D0_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	case MAX6621_TEMP_S3D1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	case MAX6621_TEMP_MAX_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	case MAX6621_TEMP_S0_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	case MAX6621_TEMP_S1_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	case MAX6621_TEMP_S2_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	case MAX6621_TEMP_S3_ALERT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	case MAX6621_TEMP_ALERT_CAUSE_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct reg_default max6621_regmap_default[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	{ MAX6621_CONFIG0_REG, MAX6621_CONFIG0_INIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	{ MAX6621_CONFIG1_REG, MAX6621_CONFIG1_INIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const struct regmap_config max6621_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.max_register = MAX6621_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	.writeable_reg = max6621_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	.readable_reg = max6621_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	.volatile_reg = max6621_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	.reg_defaults = max6621_regmap_default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.num_reg_defaults = ARRAY_SIZE(max6621_regmap_default),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct hwmon_channel_info *max6621_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	HWMON_CHANNEL_INFO(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 			   HWMON_C_REGISTER_TZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			   HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 			   HWMON_T_INPUT | HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 			   HWMON_T_INPUT | HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 			   HWMON_T_INPUT | HWMON_T_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 			   HWMON_T_INPUT | HWMON_T_LABEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct hwmon_ops max6621_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	.read = max6621_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	.write = max6621_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.read_string = max6621_read_string,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.is_visible = max6621_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct hwmon_chip_info max6621_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	.ops = &max6621_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	.info = max6621_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int max6621_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	struct max6621_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	data->regmap = devm_regmap_init_i2c(client, &max6621_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	if (IS_ERR(data->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	/* Set CONFIG0 register masking temperature alerts and PEC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	ret = regmap_write(data->regmap, MAX6621_CONFIG0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 			   MAX6621_CONFIG0_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	/* Set CONFIG1 register for PEC access retry number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	ret = regmap_write(data->regmap, MAX6621_CONFIG1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 			   MAX6621_CONFIG1_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	/* Sync registers with hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	regcache_mark_dirty(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	ret = regcache_sync(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	/* Verify which temperature input registers are enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	for (i = 0; i < MAX6621_TEMP_INPUT_REG_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		ret = i2c_smbus_read_word_data(client, max6621_temp_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		ret = max6621_verify_reg_data(dev, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 			data->input_chan2reg[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		data->input_chan2reg[i] = max6621_temp_regs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 							 data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 							 &max6621_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 							 NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct i2c_device_id max6621_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	{ MAX6621_DRV_NAME, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MODULE_DEVICE_TABLE(i2c, max6621_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct of_device_id __maybe_unused max6621_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	{ .compatible = "maxim,max6621" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MODULE_DEVICE_TABLE(of, max6621_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static struct i2c_driver max6621_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	.class		= I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		.name = MAX6621_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		.of_match_table = of_match_ptr(max6621_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	.probe_new	= max6621_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	.id_table	= max6621_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) module_i2c_driver(max6621_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MODULE_DESCRIPTION("Driver for Maxim MAX6621");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MODULE_LICENSE("GPL");