Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for MAX31730 3-Channel Remote Temperature Sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2019 Guenter Roeck <linux@roeck-us.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* Addresses scanned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static const unsigned short normal_i2c[] = { 0x1c, 0x1d, 0x1e, 0x1f, 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 					     0x4d, 0x4e, 0x4f, I2C_CLIENT_END };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* The MAX31730 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MAX31730_REG_TEMP		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MAX31730_REG_CONF		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define  MAX31730_STOP			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define  MAX31730_EXTRANGE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MAX31730_REG_TEMP_OFFSET	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define  MAX31730_TEMP_OFFSET_BASELINE	0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MAX31730_REG_OFFSET_ENABLE	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MAX31730_REG_TEMP_MAX		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MAX31730_REG_TEMP_MIN		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MAX31730_REG_STATUS_HIGH	0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MAX31730_REG_STATUS_LOW		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MAX31730_REG_CHANNEL_ENABLE	0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MAX31730_REG_TEMP_FAULT		0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MAX31730_REG_MFG_ID		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define  MAX31730_MFG_ID		0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MAX31730_REG_MFG_REV		0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define  MAX31730_MFG_REV		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MAX31730_TEMP_MIN		(-128000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MAX31730_TEMP_MAX		127937
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* Each client has this additional data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct max31730_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct i2c_client	*client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u8			orig_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8			current_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8			offset_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u8			channel_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /*-----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static inline long max31730_reg_to_mc(s16 temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return DIV_ROUND_CLOSEST((temp >> 4) * 1000, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static int max31730_write_config(struct max31730_data *data, u8 set_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 				 u8 clr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	clr_mask |= MAX31730_EXTRANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	value = data->current_conf & ~clr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	value |= set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (data->current_conf != value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		s32 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		err = i2c_smbus_write_byte_data(data->client, MAX31730_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 						value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		data->current_conf = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static int max31730_set_enable(struct i2c_client *client, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			       u8 *confdata, int channel, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 regval = *confdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		regval |= BIT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		regval &= ~BIT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (regval != *confdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		err = i2c_smbus_write_byte_data(client, reg, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		*confdata = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int max31730_set_offset_enable(struct max31730_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				      bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return max31730_set_enable(data->client, MAX31730_REG_OFFSET_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				   &data->offset_enable, channel, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int max31730_set_channel_enable(struct max31730_data *data, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				       bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return max31730_set_enable(data->client, MAX31730_REG_CHANNEL_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				   &data->channel_enable, channel, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int max31730_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			 u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct max31730_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int regval, reg, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (!(data->channel_enable & BIT(channel)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		reg = MAX31730_REG_TEMP + (channel * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		reg = MAX31730_REG_TEMP_MAX + (channel * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		reg = MAX31730_REG_TEMP_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	case hwmon_temp_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		*val = !!(data->channel_enable & BIT(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		if (!channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		if (!(data->offset_enable & BIT(channel))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		offset = i2c_smbus_read_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 						  MAX31730_REG_TEMP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (offset < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		*val = (offset - MAX31730_TEMP_OFFSET_BASELINE) * 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		regval = i2c_smbus_read_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 						  MAX31730_REG_TEMP_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (regval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		*val = !!(regval & BIT(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		regval = i2c_smbus_read_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 						  MAX31730_REG_STATUS_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (regval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		*val = !!(regval & BIT(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		regval = i2c_smbus_read_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 						  MAX31730_REG_STATUS_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (regval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		*val = !!(regval & BIT(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	regval = i2c_smbus_read_word_swapped(data->client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (regval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	*val = max31730_reg_to_mc(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int max31730_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			  u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct max31730_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int reg, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		reg = MAX31730_REG_TEMP_MAX + channel * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		reg = MAX31730_REG_TEMP_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case hwmon_temp_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		if (val != 0 && val != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return max31730_set_channel_enable(data, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		val = clamp_val(val, -14875, 17000) + 14875;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		val = DIV_ROUND_CLOSEST(val, 125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		err = max31730_set_offset_enable(data, channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 					val != MAX31730_TEMP_OFFSET_BASELINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 						 MAX31730_REG_TEMP_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	val = clamp_val(val, MAX31730_TEMP_MIN, MAX31730_TEMP_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	val = DIV_ROUND_CLOSEST(val << 4, 1000) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return i2c_smbus_write_word_swapped(data->client, reg, (u16)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static umode_t max31730_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				   enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				   u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			return channel ? 0444 : 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		case hwmon_temp_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct hwmon_channel_info *max31730_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	HWMON_CHANNEL_INFO(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			   HWMON_C_REGISTER_TZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			   HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			   HWMON_T_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			   HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			   HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			   HWMON_T_OFFSET | HWMON_T_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			   HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			   HWMON_T_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			   HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			   HWMON_T_OFFSET | HWMON_T_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			   HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			   HWMON_T_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			   HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			   HWMON_T_OFFSET | HWMON_T_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			   HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			   HWMON_T_FAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			   ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct hwmon_ops max31730_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.is_visible = max31730_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.read = max31730_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.write = max31730_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct hwmon_chip_info max31730_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.ops = &max31730_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.info = max31730_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void max31730_remove(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct max31730_data *max31730 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	struct i2c_client *client = max31730->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	i2c_smbus_write_byte_data(client, MAX31730_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				  max31730->orig_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) max31730_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct max31730_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	int status, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	data = devm_kzalloc(dev, sizeof(struct max31730_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/* Cache original configuration and enable status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	status = i2c_smbus_read_byte_data(client, MAX31730_REG_CHANNEL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	data->channel_enable = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	status = i2c_smbus_read_byte_data(client, MAX31730_REG_OFFSET_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	data->offset_enable = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	status = i2c_smbus_read_byte_data(client, MAX31730_REG_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	data->orig_conf = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	data->current_conf = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	err = max31730_write_config(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				    data->channel_enable ? 0 : MAX31730_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 				    data->channel_enable ? MAX31730_STOP : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	dev_set_drvdata(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	err = devm_add_action_or_reset(dev, max31730_remove, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 							 data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 							 &max31730_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 							 NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct i2c_device_id max31730_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{ "max31730", 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_DEVICE_TABLE(i2c, max31730_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct of_device_id __maybe_unused max31730_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.compatible = "maxim,max31730",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_DEVICE_TABLE(of, max31730_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static bool max31730_check_reg_temp(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 				    int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	regval = i2c_smbus_read_byte_data(client, reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return regval < 0 || (regval & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Return 0 if detection is successful, -ENODEV otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int max31730_detect(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			   struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 				     I2C_FUNC_SMBUS_WORD_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	regval = i2c_smbus_read_byte_data(client, MAX31730_REG_MFG_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (regval != MAX31730_MFG_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	regval = i2c_smbus_read_byte_data(client, MAX31730_REG_MFG_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (regval != MAX31730_MFG_REV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	/* lower 4 bit of temperature and limit registers must be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (max31730_check_reg_temp(client, MAX31730_REG_TEMP_MIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		if (max31730_check_reg_temp(client, MAX31730_REG_TEMP + i * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		if (max31730_check_reg_temp(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 					    MAX31730_REG_TEMP_MAX + i * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	strlcpy(info->type, "max31730", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int __maybe_unused max31730_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	struct max31730_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	return max31730_write_config(data, MAX31730_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int __maybe_unused max31730_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	struct max31730_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	return max31730_write_config(data, 0, MAX31730_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static SIMPLE_DEV_PM_OPS(max31730_pm_ops, max31730_suspend, max31730_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct i2c_driver max31730_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	.class		= I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		.name	= "max31730",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		.of_match_table = of_match_ptr(max31730_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		.pm	= &max31730_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.probe_new	= max31730_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.id_table	= max31730_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.detect		= max31730_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	.address_list	= normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) module_i2c_driver(max31730_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_DESCRIPTION("MAX31730 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MODULE_LICENSE("GPL");