^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Lantiq cpu temperature sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Florian Eckert <fe@dev.tdt.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* gphy1 configuration register contains cpu temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CGU_GPHY1_CR 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CGU_TEMP_PD BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void ltq_cputemp_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void ltq_cputemp_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int ltq_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 attr, int channel, long *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* get the temperature including one decimal place */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) value = value * 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* range -38 to +154 °C, register value zero is -38.0 °C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) value -= 380;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* scale temp to millidegree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) value = value * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *temp = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static umode_t ltq_is_visible(const void *_data, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct hwmon_channel_info *ltq_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) HWMON_CHANNEL_INFO(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) HWMON_C_REGISTER_TZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) HWMON_T_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct hwmon_ops ltq_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .is_visible = ltq_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .read = ltq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct hwmon_chip_info ltq_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .ops = <q_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .info = ltq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int ltq_cputemp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* available on vr9 v1.2 SoCs only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ltq_soc_type() != SOC_TYPE_VR9_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) err = devm_add_action(&pdev->dev, ltq_cputemp_disable, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ltq_cputemp_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "ltq_cputemp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) <q_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (IS_ERR(hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(&pdev->dev, "Failed to register as hwmon device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return PTR_ERR(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const struct of_device_id ltq_cputemp_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .compatible = "lantiq,cputemp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MODULE_DEVICE_TABLE(of, ltq_cputemp_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct platform_driver ltq_cputemp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .probe = ltq_cputemp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .name = "ltq-cputemp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .of_match_table = ltq_cputemp_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) module_platform_driver(ltq_cputemp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MODULE_AUTHOR("Florian Eckert <fe@dev.tdt.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MODULE_DESCRIPTION("Lantiq cpu temperature sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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