^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Linear Technology LTC2945 I2C Power Monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Guenter Roeck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LTC2945_CONTROL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LTC2945_ALERT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LTC2945_STATUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LTC2945_FAULT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LTC2945_POWER_H 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LTC2945_MAX_POWER_H 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LTC2945_MIN_POWER_H 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LTC2945_MAX_POWER_THRES_H 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LTC2945_MIN_POWER_THRES_H 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LTC2945_SENSE_H 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LTC2945_MAX_SENSE_H 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LTC2945_MIN_SENSE_H 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LTC2945_MAX_SENSE_THRES_H 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LTC2945_MIN_SENSE_THRES_H 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LTC2945_VIN_H 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LTC2945_MAX_VIN_H 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LTC2945_MIN_VIN_H 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LTC2945_MAX_VIN_THRES_H 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LTC2945_MIN_VIN_THRES_H 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LTC2945_ADIN_H 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LTC2945_MAX_ADIN_H 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LTC2945_MIN_ADIN_H 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LTC2945_MAX_ADIN_THRES_H 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LTC2945_MIN_ADIN_THRES_H 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LTC2945_MIN_ADIN_THRES_L 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Fault register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FAULT_ADIN_UV (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FAULT_ADIN_OV (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FAULT_VIN_UV (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FAULT_VIN_OV (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FAULT_SENSE_UV (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FAULT_SENSE_OV (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FAULT_POWER_UV (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FAULT_POWER_OV (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CONTROL_MULT_SELECT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CONTROL_TEST_MODE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline bool is_power_reg(u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return reg < LTC2945_SENSE_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Return the value from the given register in uW, mV, or mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static long long ltc2945_reg_to_val(struct device *dev, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct regmap *regmap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) long long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = regmap_bulk_read(regmap, reg, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) is_power_reg(reg) ? 3 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (is_power_reg(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val = (buf[0] << 16) + (buf[1] << 8) + buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* current, voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val = (buf[0] << 4) + (buf[1] >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case LTC2945_POWER_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case LTC2945_MAX_POWER_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case LTC2945_MIN_POWER_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case LTC2945_MAX_POWER_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case LTC2945_MIN_POWER_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Convert to uW by assuming current is measured with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * an 1mOhm sense resistor, similar to current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * measurements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Control register bit 0 selects if voltage at SENSE+/VDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * or voltage at ADIN is used to measure power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = regmap_read(regmap, LTC2945_CONTROL, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (control & CONTROL_MULT_SELECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* 25 mV * 25 uV = 0.625 uV resolution. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val *= 625LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* 0.5 mV * 25 uV = 0.0125 uV resolution. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val = (val * 25LL) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case LTC2945_VIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case LTC2945_MAX_VIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case LTC2945_MIN_VIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case LTC2945_MAX_VIN_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case LTC2945_MIN_VIN_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* 25 mV resolution. Convert to mV. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val *= 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case LTC2945_ADIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case LTC2945_MAX_ADIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case LTC2945_MIN_ADIN_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case LTC2945_MAX_ADIN_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case LTC2945_MIN_ADIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* 0.5mV resolution. Convert to mV. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val = val >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case LTC2945_SENSE_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case LTC2945_MAX_SENSE_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case LTC2945_MIN_SENSE_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case LTC2945_MAX_SENSE_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case LTC2945_MIN_SENSE_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * 25 uV resolution. Convert to current as measured with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * an 1 mOhm sense resistor, in mA. If a different sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * resistor is installed, calculate the actual current by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * dividing the reported current by the sense resistor value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * in mOhm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) val *= 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int ltc2945_val_to_reg(struct device *dev, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct regmap *regmap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case LTC2945_POWER_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case LTC2945_MAX_POWER_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case LTC2945_MIN_POWER_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case LTC2945_MAX_POWER_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case LTC2945_MIN_POWER_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Convert to register value by assuming current is measured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * with an 1mOhm sense resistor, similar to current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * measurements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Control register bit 0 selects if voltage at SENSE+/VDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * or voltage at ADIN is used to measure power, which in turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * determines register calculations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = regmap_read(regmap, LTC2945_CONTROL, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (control & CONTROL_MULT_SELECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* 25 mV * 25 uV = 0.625 uV resolution. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) val = DIV_ROUND_CLOSEST(val, 625);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * 0.5 mV * 25 uV = 0.0125 uV resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Divide first to avoid overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * accept loss of accuracy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) val = DIV_ROUND_CLOSEST(val, 25) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case LTC2945_VIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case LTC2945_MAX_VIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case LTC2945_MIN_VIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case LTC2945_MAX_VIN_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case LTC2945_MIN_VIN_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* 25 mV resolution. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) val /= 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case LTC2945_ADIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case LTC2945_MAX_ADIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case LTC2945_MIN_ADIN_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case LTC2945_MAX_ADIN_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case LTC2945_MIN_ADIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* 0.5mV resolution. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case LTC2945_SENSE_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case LTC2945_MAX_SENSE_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case LTC2945_MIN_SENSE_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case LTC2945_MAX_SENSE_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case LTC2945_MIN_SENSE_THRES_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * 25 uV resolution. Convert to current as measured with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * an 1 mOhm sense resistor, in mA. If a different sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * resistor is installed, calculate the actual current by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * dividing the reported current by the sense resistor value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * in mOhm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val = DIV_ROUND_CLOSEST(val, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static ssize_t ltc2945_value_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct device_attribute *da, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) long long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) value = ltc2945_reg_to_val(dev, attr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return snprintf(buf, PAGE_SIZE, "%lld\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static ssize_t ltc2945_value_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct regmap *regmap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 reg = attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 regbuf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* convert to register value, then clamp and write result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) regval = ltc2945_val_to_reg(dev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (is_power_reg(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) regval = clamp_val(regval, 0, 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) regbuf[0] = regval >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) regbuf[1] = (regval >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regbuf[2] = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) num_regs = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) regval = clamp_val(regval, 0, 0xfff) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regbuf[0] = regval >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) regbuf[1] = regval & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) num_regs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = regmap_bulk_write(regmap, reg, regbuf, num_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret < 0 ? ret : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static ssize_t ltc2945_history_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct regmap *regmap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 reg = attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int num_regs = is_power_reg(reg) ? 3 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 buf_min[3] = { 0xff, 0xff, 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 buf_max[3] = { 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (val != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = regmap_update_bits(regmap, LTC2945_CONTROL, CONTROL_TEST_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CONTROL_TEST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Reset minimum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = regmap_bulk_write(regmap, reg, buf_min, num_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case LTC2945_MIN_POWER_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) reg = LTC2945_MAX_POWER_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case LTC2945_MIN_SENSE_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) reg = LTC2945_MAX_SENSE_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case LTC2945_MIN_VIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) reg = LTC2945_MAX_VIN_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case LTC2945_MIN_ADIN_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) reg = LTC2945_MAX_ADIN_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) WARN_ONCE(1, "Bad register: 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Reset maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = regmap_bulk_write(regmap, reg, buf_max, num_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Try resetting test mode even if there was an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) regmap_update_bits(regmap, LTC2945_CONTROL, CONTROL_TEST_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret ? : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static ssize_t ltc2945_bool_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct device_attribute *da, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct regmap *regmap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = regmap_read(regmap, LTC2945_FAULT, &fault);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) fault &= attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (fault) /* Clear reported faults in chip register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) regmap_update_bits(regmap, LTC2945_FAULT, attr->index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return snprintf(buf, PAGE_SIZE, "%d\n", !!fault);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Input voltages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static SENSOR_DEVICE_ATTR_RO(in1_input, ltc2945_value, LTC2945_VIN_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static SENSOR_DEVICE_ATTR_RW(in1_min, ltc2945_value, LTC2945_MIN_VIN_THRES_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static SENSOR_DEVICE_ATTR_RW(in1_max, ltc2945_value, LTC2945_MAX_VIN_THRES_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static SENSOR_DEVICE_ATTR_RO(in1_lowest, ltc2945_value, LTC2945_MIN_VIN_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static SENSOR_DEVICE_ATTR_RO(in1_highest, ltc2945_value, LTC2945_MAX_VIN_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static SENSOR_DEVICE_ATTR_WO(in1_reset_history, ltc2945_history,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) LTC2945_MIN_VIN_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static SENSOR_DEVICE_ATTR_RO(in2_input, ltc2945_value, LTC2945_ADIN_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static SENSOR_DEVICE_ATTR_RW(in2_min, ltc2945_value, LTC2945_MIN_ADIN_THRES_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static SENSOR_DEVICE_ATTR_RW(in2_max, ltc2945_value, LTC2945_MAX_ADIN_THRES_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static SENSOR_DEVICE_ATTR_RO(in2_lowest, ltc2945_value, LTC2945_MIN_ADIN_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static SENSOR_DEVICE_ATTR_RO(in2_highest, ltc2945_value, LTC2945_MAX_ADIN_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static SENSOR_DEVICE_ATTR_WO(in2_reset_history, ltc2945_history,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) LTC2945_MIN_ADIN_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Voltage alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static SENSOR_DEVICE_ATTR_RO(in1_min_alarm, ltc2945_bool, FAULT_VIN_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static SENSOR_DEVICE_ATTR_RO(in1_max_alarm, ltc2945_bool, FAULT_VIN_OV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static SENSOR_DEVICE_ATTR_RO(in2_min_alarm, ltc2945_bool, FAULT_ADIN_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static SENSOR_DEVICE_ATTR_RO(in2_max_alarm, ltc2945_bool, FAULT_ADIN_OV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Currents (via sense resistor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static SENSOR_DEVICE_ATTR_RO(curr1_input, ltc2945_value, LTC2945_SENSE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static SENSOR_DEVICE_ATTR_RW(curr1_min, ltc2945_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) LTC2945_MIN_SENSE_THRES_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static SENSOR_DEVICE_ATTR_RW(curr1_max, ltc2945_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) LTC2945_MAX_SENSE_THRES_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static SENSOR_DEVICE_ATTR_RO(curr1_lowest, ltc2945_value, LTC2945_MIN_SENSE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static SENSOR_DEVICE_ATTR_RO(curr1_highest, ltc2945_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) LTC2945_MAX_SENSE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static SENSOR_DEVICE_ATTR_WO(curr1_reset_history, ltc2945_history,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) LTC2945_MIN_SENSE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Current alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static SENSOR_DEVICE_ATTR_RO(curr1_min_alarm, ltc2945_bool, FAULT_SENSE_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static SENSOR_DEVICE_ATTR_RO(curr1_max_alarm, ltc2945_bool, FAULT_SENSE_OV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static SENSOR_DEVICE_ATTR_RO(power1_input, ltc2945_value, LTC2945_POWER_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static SENSOR_DEVICE_ATTR_RW(power1_min, ltc2945_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) LTC2945_MIN_POWER_THRES_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static SENSOR_DEVICE_ATTR_RW(power1_max, ltc2945_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) LTC2945_MAX_POWER_THRES_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static SENSOR_DEVICE_ATTR_RO(power1_input_lowest, ltc2945_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) LTC2945_MIN_POWER_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static SENSOR_DEVICE_ATTR_RO(power1_input_highest, ltc2945_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) LTC2945_MAX_POWER_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static SENSOR_DEVICE_ATTR_WO(power1_reset_history, ltc2945_history,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) LTC2945_MIN_POWER_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Power alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static SENSOR_DEVICE_ATTR_RO(power1_min_alarm, ltc2945_bool, FAULT_POWER_UV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static SENSOR_DEVICE_ATTR_RO(power1_max_alarm, ltc2945_bool, FAULT_POWER_OV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct attribute *ltc2945_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) &sensor_dev_attr_in1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) &sensor_dev_attr_in1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) &sensor_dev_attr_in1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &sensor_dev_attr_in1_lowest.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) &sensor_dev_attr_in1_highest.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) &sensor_dev_attr_in1_reset_history.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &sensor_dev_attr_in1_min_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) &sensor_dev_attr_in1_max_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &sensor_dev_attr_in2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) &sensor_dev_attr_in2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) &sensor_dev_attr_in2_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) &sensor_dev_attr_in2_lowest.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) &sensor_dev_attr_in2_highest.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) &sensor_dev_attr_in2_reset_history.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &sensor_dev_attr_in2_min_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) &sensor_dev_attr_in2_max_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) &sensor_dev_attr_curr1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) &sensor_dev_attr_curr1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) &sensor_dev_attr_curr1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) &sensor_dev_attr_curr1_lowest.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) &sensor_dev_attr_curr1_highest.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) &sensor_dev_attr_curr1_reset_history.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &sensor_dev_attr_curr1_min_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) &sensor_dev_attr_curr1_max_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) &sensor_dev_attr_power1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) &sensor_dev_attr_power1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) &sensor_dev_attr_power1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) &sensor_dev_attr_power1_input_lowest.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &sensor_dev_attr_power1_input_highest.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) &sensor_dev_attr_power1_reset_history.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &sensor_dev_attr_power1_min_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) &sensor_dev_attr_power1_max_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ATTRIBUTE_GROUPS(ltc2945);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct regmap_config ltc2945_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .max_register = LTC2945_MIN_ADIN_THRES_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int ltc2945_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) regmap = devm_regmap_init_i2c(client, <c2945_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(dev, "failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Clear faults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regmap_write(regmap, LTC2945_FAULT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ltc2945_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct i2c_device_id ltc2945_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {"ltc2945", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_DEVICE_TABLE(i2c, ltc2945_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static struct i2c_driver ltc2945_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .name = "ltc2945",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .probe_new = ltc2945_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .id_table = ltc2945_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) module_i2c_driver(ltc2945_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MODULE_DESCRIPTION("LTC2945 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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