^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Alexander Stein <alexander.stein@systec-electronic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * The LM95245 is a sensor chip made by TI / National Semiconductor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * It reports up to two temperatures (its own plus an external one).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This driver is based on lm95241.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const unsigned short normal_i2c[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 0x18, 0x19, 0x29, 0x4c, 0x4d, I2C_CLIENT_END };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* LM95245 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* general registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LM95245_REG_RW_CONFIG1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LM95245_REG_RW_CONVERS_RATE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LM95245_REG_W_ONE_SHOT 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* diode configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LM95245_REG_RW_CONFIG2 0xBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LM95245_REG_RW_REMOTE_OFFH 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LM95245_REG_RW_REMOTE_OFFL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LM95245_REG_R_STATUS1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LM95245_REG_R_STATUS2 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* limit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LM95245_REG_RW_REMOTE_OS_LIMIT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LM95245_REG_RW_REMOTE_TCRIT_LIMIT 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LM95245_REG_RW_COMMON_HYSTERESIS 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* temperature signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LM95245_REG_R_LOCAL_TEMPH_S 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LM95245_REG_R_LOCAL_TEMPL_S 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LM95245_REG_R_REMOTE_TEMPH_S 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LM95245_REG_R_REMOTE_TEMPL_S 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* temperature unsigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LM95245_REG_R_REMOTE_TEMPH_U 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LM95245_REG_R_REMOTE_TEMPL_U 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* id registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LM95245_REG_R_MAN_ID 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LM95245_REG_R_CHIP_ID 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* LM95245 specific bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CFG_STOP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CFG_REMOTE_TCRIT_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CFG_REMOTE_OS_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CFG_LOCAL_TCRIT_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CFG_LOCAL_OS_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CFG2_OS_A0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CFG2_DIODE_FAULT_OS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CFG2_DIODE_FAULT_TCRIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CFG2_REMOTE_TT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CFG2_REMOTE_FILTER_DIS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CFG2_REMOTE_FILTER_EN 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* conversation rate in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RATE_CR0063 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RATE_CR0364 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RATE_CR1000 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RATE_CR2500 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STATUS1_ROS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STATUS1_DIODE_FAULT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STATUS1_RTCRIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STATUS1_LOC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MANUFACTURER_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LM95235_REVISION 0xB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LM95245_REVISION 0xB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Client data (each client gets its own) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct lm95245_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int interval; /* in msecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int temp_from_reg_unsigned(u8 val_h, u8 val_l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return val_h * 1000 + val_l * 1000 / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int temp_from_reg_signed(u8 val_h, u8 val_l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (val_h & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return (val_h - 0x100) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return temp_from_reg_unsigned(val_h, val_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int lm95245_read_conversion_rate(struct lm95245_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = regmap_read(data->regmap, LM95245_REG_RW_CONVERS_RATE, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case RATE_CR0063:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) data->interval = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case RATE_CR0364:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) data->interval = 364;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case RATE_CR1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) data->interval = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case RATE_CR2500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) data->interval = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int lm95245_set_conversion_rate(struct lm95245_data *data, long interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int ret, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (interval <= 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) interval = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rate = RATE_CR0063;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) } else if (interval <= 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) interval = 364;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rate = RATE_CR0364;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) } else if (interval <= 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) interval = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rate = RATE_CR1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) interval = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rate = RATE_CR2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = regmap_write(data->regmap, LM95245_REG_RW_CONVERS_RATE, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) data->interval = interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int lm95245_read_temp(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct lm95245_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ret, regl, regh, regvall, regvalh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) regl = channel ? LM95245_REG_R_REMOTE_TEMPL_S :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) LM95245_REG_R_LOCAL_TEMPL_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) regh = channel ? LM95245_REG_R_REMOTE_TEMPH_S :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) LM95245_REG_R_LOCAL_TEMPH_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = regmap_read(regmap, regl, ®vall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = regmap_read(regmap, regh, ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Local temp is always signed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Remote temp has both signed and unsigned data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Use signed calculation for remote if signed bit is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * or if reported temperature is below signed limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!channel || (regvalh & 0x80) || regvalh < 0x7f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *val = temp_from_reg_signed(regvalh, regvall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = regmap_read(regmap, LM95245_REG_R_REMOTE_TEMPL_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ®vall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = regmap_read(regmap, LM95245_REG_R_REMOTE_TEMPH_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *val = temp_from_reg_unsigned(regvalh, regvall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = regmap_read(regmap, LM95245_REG_RW_REMOTE_OS_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *val = regvalh * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) regh = channel ? LM95245_REG_RW_REMOTE_TCRIT_LIMIT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = regmap_read(regmap, regh, ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *val = regvalh * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case hwmon_temp_max_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = regmap_read(regmap, LM95245_REG_RW_REMOTE_OS_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = regmap_read(regmap, LM95245_REG_RW_COMMON_HYSTERESIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ®vall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *val = (regvalh - regvall) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case hwmon_temp_crit_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) regh = channel ? LM95245_REG_RW_REMOTE_TCRIT_LIMIT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = regmap_read(regmap, regh, ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = regmap_read(regmap, LM95245_REG_RW_COMMON_HYSTERESIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ®vall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *val = (regvalh - regvall) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case hwmon_temp_type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = regmap_read(regmap, LM95245_REG_RW_CONFIG2, ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *val = (regvalh & CFG2_REMOTE_TT) ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = regmap_read(regmap, LM95245_REG_RW_REMOTE_OFFL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ®vall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = regmap_read(regmap, LM95245_REG_RW_REMOTE_OFFH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *val = temp_from_reg_signed(regvalh, regvall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = regmap_read(regmap, LM95245_REG_R_STATUS1, ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *val = !!(regvalh & STATUS1_ROS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = regmap_read(regmap, LM95245_REG_R_STATUS1, ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *val = !!(regvalh & (channel ? STATUS1_RTCRIT : STATUS1_LOC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = regmap_read(regmap, LM95245_REG_R_STATUS1, ®valh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *val = !!(regvalh & STATUS1_DIODE_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int lm95245_write_temp(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct lm95245_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct regmap *regmap = data->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val = clamp_val(val / 1000, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = regmap_write(regmap, LM95245_REG_RW_REMOTE_OS_LIMIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) reg = channel ? LM95245_REG_RW_REMOTE_TCRIT_LIMIT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val = clamp_val(val / 1000, 0, channel ? 255 : 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = regmap_write(regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case hwmon_temp_crit_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = regmap_read(regmap, LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Clamp to reasonable range to prevent overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val = clamp_val(val, -1000000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val = regval - val / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val = clamp_val(val, 0, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = regmap_write(regmap, LM95245_REG_RW_COMMON_HYSTERESIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val = clamp_val(val, -128000, 127875);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val = val * 256 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = regmap_write(regmap, LM95245_REG_RW_REMOTE_OFFL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) val & 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = regmap_write(regmap, LM95245_REG_RW_REMOTE_OFFH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) (val >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case hwmon_temp_type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (val != 1 && val != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = regmap_update_bits(regmap, LM95245_REG_RW_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CFG2_REMOTE_TT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) val == 1 ? CFG2_REMOTE_TT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int lm95245_read_chip(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct lm95245_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *val = data->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int lm95245_write_chip(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct lm95245_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = lm95245_set_conversion_rate(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int lm95245_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return lm95245_read_chip(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return lm95245_read_temp(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int lm95245_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return lm95245_write_chip(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return lm95245_write_temp(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static umode_t lm95245_temp_is_visible(const void *data, u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case hwmon_temp_max_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case hwmon_temp_type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case hwmon_temp_crit_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return (channel == 0) ? 0644 : 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static umode_t lm95245_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return lm95245_temp_is_visible(data, attr, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Return 0 if detection is successful, -ENODEV otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int lm95245_detect(struct i2c_client *new_client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct i2c_adapter *adapter = new_client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int address = new_client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int rev, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) id = i2c_smbus_read_byte_data(new_client, LM95245_REG_R_MAN_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (id != MANUFACTURER_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rev = i2c_smbus_read_byte_data(new_client, LM95245_REG_R_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case LM95235_REVISION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (address != 0x18 && address != 0x29 && address != 0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) name = "lm95235";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case LM95245_REVISION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) name = "lm95245";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) strlcpy(info->type, name, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int lm95245_init_client(struct lm95245_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = lm95245_read_conversion_rate(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return regmap_update_bits(data->regmap, LM95245_REG_RW_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) CFG_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static bool lm95245_is_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case LM95245_REG_RW_CONFIG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case LM95245_REG_RW_CONVERS_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case LM95245_REG_W_ONE_SHOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case LM95245_REG_RW_CONFIG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case LM95245_REG_RW_REMOTE_OFFH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case LM95245_REG_RW_REMOTE_OFFL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case LM95245_REG_RW_REMOTE_OS_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case LM95245_REG_RW_LOCAL_OS_TCRIT_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case LM95245_REG_RW_REMOTE_TCRIT_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case LM95245_REG_RW_COMMON_HYSTERESIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static bool lm95245_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case LM95245_REG_R_STATUS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case LM95245_REG_R_STATUS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case LM95245_REG_R_LOCAL_TEMPH_S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case LM95245_REG_R_LOCAL_TEMPL_S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case LM95245_REG_R_REMOTE_TEMPH_S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case LM95245_REG_R_REMOTE_TEMPL_S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case LM95245_REG_R_REMOTE_TEMPH_U:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case LM95245_REG_R_REMOTE_TEMPL_U:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct regmap_config lm95245_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .writeable_reg = lm95245_is_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .volatile_reg = lm95245_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .use_single_read = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct hwmon_channel_info *lm95245_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) HWMON_CHANNEL_INFO(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) HWMON_C_UPDATE_INTERVAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_HYST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) HWMON_T_CRIT_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_FAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) HWMON_T_TYPE | HWMON_T_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct hwmon_ops lm95245_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .is_visible = lm95245_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .read = lm95245_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .write = lm95245_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct hwmon_chip_info lm95245_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .ops = &lm95245_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .info = lm95245_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int lm95245_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct lm95245_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) data = devm_kzalloc(dev, sizeof(struct lm95245_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) data->regmap = devm_regmap_init_i2c(client, &lm95245_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (IS_ERR(data->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Initialize the LM95245 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = lm95245_init_client(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) &lm95245_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Driver data (common to all clients) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct i2c_device_id lm95245_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { "lm95235", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { "lm95245", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MODULE_DEVICE_TABLE(i2c, lm95245_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static const struct of_device_id __maybe_unused lm95245_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { .compatible = "national,lm95235" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { .compatible = "national,lm95245" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MODULE_DEVICE_TABLE(of, lm95245_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct i2c_driver lm95245_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .name = "lm95245",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .of_match_table = of_match_ptr(lm95245_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .probe_new = lm95245_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .id_table = lm95245_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .detect = lm95245_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .address_list = normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) module_i2c_driver(lm95245_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MODULE_AUTHOR("Alexander Stein <alexander.stein@systec-electronic.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MODULE_DESCRIPTION("LM95235/LM95245 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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