Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2008, 2010 Davide Rizzo <elpa.rizzo@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * The LM95241 is a sensor chip made by National Semiconductors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * It reports up to three temperatures (its own plus up to two external ones).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Complete datasheet can be obtained from National's website at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *   http://www.national.com/ds.cgi/LM/LM95241.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DEVNAME "lm95241"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static const unsigned short normal_i2c[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	0x19, 0x2a, 0x2b, I2C_CLIENT_END };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* LM95241 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LM95241_REG_R_MAN_ID		0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LM95241_REG_R_CHIP_ID		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LM95241_REG_R_STATUS		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LM95241_REG_RW_CONFIG		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LM95241_REG_RW_REM_FILTER	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LM95241_REG_RW_TRUTHERM		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LM95241_REG_W_ONE_SHOT		0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LM95241_REG_R_LOCAL_TEMPH	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LM95241_REG_R_REMOTE1_TEMPH	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LM95241_REG_R_REMOTE2_TEMPH	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LM95241_REG_R_LOCAL_TEMPL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LM95241_REG_R_REMOTE1_TEMPL	0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LM95241_REG_R_REMOTE2_TEMPL	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LM95241_REG_RW_REMOTE_MODEL	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* LM95241 specific bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CFG_STOP	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CFG_CR0076	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CFG_CR0182	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CFG_CR1000	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CFG_CR2700	(BIT(4) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CFG_CRMASK	(BIT(4) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define R1MS_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define R2MS_MASK	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define R1DF_MASK	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define R2DF_MASK	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define R1FE_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define R2FE_MASK	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define R1DM		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define R2DM		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TT1_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define TT2_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TT_OFF		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TT_ON		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TT_MASK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define NATSEMI_MAN_ID	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define LM95231_CHIP_ID	0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define LM95241_CHIP_ID	0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static const u8 lm95241_reg_address[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	LM95241_REG_R_LOCAL_TEMPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	LM95241_REG_R_LOCAL_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	LM95241_REG_R_REMOTE1_TEMPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	LM95241_REG_R_REMOTE1_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	LM95241_REG_R_REMOTE2_TEMPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	LM95241_REG_R_REMOTE2_TEMPL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* Client data (each client gets its own) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) struct lm95241_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned long last_updated;	/* in jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned long interval;		/* in milli-seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	char valid;		/* zero until following fields are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* registers values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u8 temp[ARRAY_SIZE(lm95241_reg_address)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u8 status, config, model, trutherm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* Conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int temp_from_reg_signed(u8 val_h, u8 val_l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	s16 val_hl = (val_h << 8) | val_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return val_hl * 1000 / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int temp_from_reg_unsigned(u8 val_h, u8 val_l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u16 val_hl = (val_h << 8) | val_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return val_hl * 1000 / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct lm95241_data *lm95241_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct lm95241_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (time_after(jiffies, data->last_updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		       + msecs_to_jiffies(data->interval)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	    !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		dev_dbg(dev, "Updating lm95241 data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		for (i = 0; i < ARRAY_SIZE(lm95241_reg_address); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			data->temp[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			  = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 						     lm95241_reg_address[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		data->status = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 							LM95241_REG_R_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		data->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int lm95241_read_chip(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			     long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct lm95241_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		*val = data->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int lm95241_read_temp(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			     long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct lm95241_data *data = lm95241_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		if (!channel || (data->config & BIT(channel - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			*val = temp_from_reg_signed(data->temp[channel * 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 						data->temp[channel * 2 + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			*val = temp_from_reg_unsigned(data->temp[channel * 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 						data->temp[channel * 2 + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		if (channel == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			*val = (data->config & R1DF_MASK) ? -128000 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			*val = (data->config & R2DF_MASK) ? -128000 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		if (channel == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			*val = (data->config & R1DF_MASK) ? 127875 : 255875;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			*val = (data->config & R2DF_MASK) ? 127875 : 255875;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	case hwmon_temp_type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (channel == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			*val = (data->model & R1MS_MASK) ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			*val = (data->model & R2MS_MASK) ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (channel == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			*val = !!(data->status & R1DM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			*val = !!(data->status & R2DM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int lm95241_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return lm95241_read_chip(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return lm95241_read_temp(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int lm95241_write_chip(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			      long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct lm95241_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	int convrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		config = data->config & ~CFG_CRMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		if (val < 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			convrate = 76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			config |= CFG_CR0076;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		} else if (val < 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			convrate = 182;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			config |= CFG_CR0182;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		} else if (val < 1850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			convrate = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			config |= CFG_CR1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			convrate = 2700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			config |= CFG_CR2700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		data->interval = convrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		data->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 						LM95241_REG_RW_CONFIG, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int lm95241_write_temp(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			      long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct lm95241_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		if (channel == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 				data->config |= R1DF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				data->config &= ~R1DF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 				data->config |= R2DF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				data->config &= ~R2DF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		data->valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		ret = i2c_smbus_write_byte_data(client, LM95241_REG_RW_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 						data->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		if (channel == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			if (val <= 127875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				data->config |= R1DF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				data->config &= ~R1DF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			if (val <= 127875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				data->config |= R2DF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 				data->config &= ~R2DF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		data->valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		ret = i2c_smbus_write_byte_data(client, LM95241_REG_RW_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 						data->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	case hwmon_temp_type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		if (val != 1 && val != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (channel == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			data->trutherm &= ~(TT_MASK << TT1_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			if (val == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				data->model |= R1MS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 				data->trutherm |= (TT_ON << TT1_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				data->model &= ~R1MS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				data->trutherm |= (TT_OFF << TT1_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			data->trutherm &= ~(TT_MASK << TT2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			if (val == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				data->model |= R2MS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				data->trutherm |= (TT_ON << TT2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 				data->model &= ~R2MS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				data->trutherm |= (TT_OFF << TT2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		ret = i2c_smbus_write_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 						LM95241_REG_RW_REMOTE_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 						data->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		ret = i2c_smbus_write_byte_data(client, LM95241_REG_RW_TRUTHERM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 						data->trutherm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int lm95241_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			 u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return lm95241_write_chip(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return lm95241_write_temp(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static umode_t lm95241_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 				  enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				  u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		case hwmon_temp_type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Return 0 if detection is successful, -ENODEV otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int lm95241_detect(struct i2c_client *new_client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			  struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	struct i2c_adapter *adapter = new_client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	int mfg_id, chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	mfg_id = i2c_smbus_read_byte_data(new_client, LM95241_REG_R_MAN_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (mfg_id != NATSEMI_MAN_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	chip_id = i2c_smbus_read_byte_data(new_client, LM95241_REG_R_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	switch (chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	case LM95231_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		name = "lm95231";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	case LM95241_CHIP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		name = "lm95241";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	/* Fill the i2c board info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	strlcpy(info->type, name, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void lm95241_init_client(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 				struct lm95241_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	data->interval = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	data->config = CFG_CR1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	data->trutherm = (TT_OFF << TT1_SHIFT) | (TT_OFF << TT2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	i2c_smbus_write_byte_data(client, LM95241_REG_RW_CONFIG, data->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	i2c_smbus_write_byte_data(client, LM95241_REG_RW_REM_FILTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 				  R1FE_MASK | R2FE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	i2c_smbus_write_byte_data(client, LM95241_REG_RW_TRUTHERM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 				  data->trutherm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	i2c_smbus_write_byte_data(client, LM95241_REG_RW_REMOTE_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 				  data->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct hwmon_channel_info *lm95241_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	HWMON_CHANNEL_INFO(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 			   HWMON_C_UPDATE_INTERVAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			   HWMON_T_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			   HWMON_T_TYPE | HWMON_T_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			   HWMON_T_TYPE | HWMON_T_FAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct hwmon_ops lm95241_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	.is_visible = lm95241_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	.read = lm95241_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	.write = lm95241_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const struct hwmon_chip_info lm95241_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.ops = &lm95241_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.info = lm95241_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int lm95241_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	struct lm95241_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	data = devm_kzalloc(dev, sizeof(struct lm95241_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	/* Initialize the LM95241 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	lm95241_init_client(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 							   data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 							   &lm95241_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 							   NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Driver data (common to all clients) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct i2c_device_id lm95241_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	{ "lm95231", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	{ "lm95241", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_DEVICE_TABLE(i2c, lm95241_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static struct i2c_driver lm95241_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	.class		= I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		.name	= DEVNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.probe_new	= lm95241_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.id_table	= lm95241_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.detect		= lm95241_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	.address_list	= normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) module_i2c_driver(lm95241_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MODULE_AUTHOR("Davide Rizzo <elpa.rizzo@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MODULE_DESCRIPTION("LM95231/LM95241 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MODULE_LICENSE("GPL");