^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * lm90.c - Part of lm_sensors, Linux kernel modules for hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003-2010 Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the lm83 driver. The LM90 is a sensor chip made by National
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Semiconductor. It reports up to two temperatures (its own plus up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * one external one) with a 0.125 deg resolution (1 deg for local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * temperature) and a 3-4 deg accuracy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This driver also supports the LM89 and LM99, two other sensor chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * made by National Semiconductor. Both have an increased remote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * temperature measurement accuracy (1 degree), and the LM99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * additionally shifts remote temperatures (measured and limits) by 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * degrees, which allows for higher temperatures measurement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Note that there is no way to differentiate between both chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * When device is auto-detected, the driver will assume an LM99.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * This driver also supports the LM86, another sensor chip made by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * National Semiconductor. It is exactly similar to the LM90 except it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * has a higher accuracy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This driver also supports the ADM1032, a sensor chip made by Analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Devices. That chip is similar to the LM90, with a few differences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * that are not handled by this driver. Among others, it has a higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * accuracy than the LM90, much like the LM86 does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * This driver also supports the MAX6657, MAX6658 and MAX6659 sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * chips made by Maxim. These chips are similar to the LM86.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Note that there is no easy way to differentiate between the three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * variants. We use the device address to detect MAX6659, which will result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * in a detection as max6657 if it is on address 0x4c. The extra address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * and features of the MAX6659 are only supported if the chip is configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * explicitly as max6659, or if its address is not 0x4c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * These chips lack the remote temperature offset feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * This driver also supports the MAX6654 chip made by Maxim. This chip can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * at 9 different addresses, similar to MAX6680/MAX6681. The MAX6654 is similar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * to MAX6657/MAX6658/MAX6659, but does not support critical temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * limits. Extended range is available by setting the configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * accordingly, and is done during initialization. Extended precision is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * available at conversion rates of 1 Hz and slower. Note that extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * precision is not enabled by default, as this driver initializes all chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * to 2 Hz by design.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * This driver also supports the MAX6646, MAX6647, MAX6648, MAX6649 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * MAX6692 chips made by Maxim. These are again similar to the LM86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * but they use unsigned temperature values and can report temperatures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * from 0 to 145 degrees.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * This driver also supports the MAX6680 and MAX6681, two other sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * chips made by Maxim. These are quite similar to the other Maxim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * chips. The MAX6680 and MAX6681 only differ in the pinout so they can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * be treated identically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * This driver also supports the MAX6695 and MAX6696, two other sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * chips made by Maxim. These are also quite similar to other Maxim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * chips, but support three temperature sensors instead of two. MAX6695
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * and MAX6696 only differ in the pinout so they can be treated identically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * This driver also supports ADT7461 and ADT7461A from Analog Devices as well as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * NCT1008 from ON Semiconductor. The chips are supported in both compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * and extended mode. They are mostly compatible with LM90 except for a data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * format difference for the temperature value registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * This driver also supports the SA56004 from Philips. This device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * pin-compatible with the LM86, the ED/EDP parts are also address-compatible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * This driver also supports the G781 from GMT. This device is compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * with the ADM1032.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * This driver also supports TMP451 and TMP461 from Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Those devices are supported in both compatibility and extended mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * They are mostly compatible with ADT7461 except for local temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * low byte register and max conversion rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Since the LM90 was the first chipset supported by this driver, most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * comments will refer to this chipset, but are actually general and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * concern all supported chipsets, unless mentioned otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Addresses to scan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Address is fully defined internally and cannot be changed except for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * MAX6659, MAX6680 and MAX6681.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * LM86, LM89, LM90, LM99, ADM1032, ADM1032-1, ADT7461, ADT7461A, MAX6649,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * MAX6657, MAX6658, NCT1008 and W83L771 have address 0x4c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * ADM1032-2, ADT7461-2, ADT7461A-2, LM89-1, LM99-1, MAX6646, and NCT1008D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * have address 0x4d.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * MAX6647 has address 0x4e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * MAX6659 can have address 0x4c, 0x4d or 0x4e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * MAX6654, MAX6680, and MAX6681 can have address 0x18, 0x19, 0x1a, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 0x2a, 0x2b, 0x4c, 0x4d or 0x4e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * SA56004 can have address 0x48 through 0x4F.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const unsigned short normal_i2c[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x48, 0x49, 0x4a, 0x4b, 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x4d, 0x4e, 0x4f, I2C_CLIENT_END };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum chips { lm90, adm1032, lm99, lm86, max6657, max6659, adt7461, max6680,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) max6646, w83l771, max6696, sa56004, g781, tmp451, tmp461, max6654 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * The LM90 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LM90_REG_R_MAN_ID 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LM90_REG_R_CHIP_ID 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LM90_REG_R_CONFIG1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LM90_REG_W_CONFIG1 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LM90_REG_R_CONFIG2 0xBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LM90_REG_W_CONFIG2 0xBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LM90_REG_R_CONVRATE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LM90_REG_W_CONVRATE 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LM90_REG_R_STATUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LM90_REG_R_LOCAL_TEMP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LM90_REG_R_LOCAL_HIGH 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LM90_REG_W_LOCAL_HIGH 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LM90_REG_R_LOCAL_LOW 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LM90_REG_W_LOCAL_LOW 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LM90_REG_R_LOCAL_CRIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LM90_REG_W_LOCAL_CRIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LM90_REG_R_REMOTE_TEMPH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LM90_REG_R_REMOTE_TEMPL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LM90_REG_R_REMOTE_OFFSH 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LM90_REG_W_REMOTE_OFFSH 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LM90_REG_R_REMOTE_OFFSL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LM90_REG_W_REMOTE_OFFSL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LM90_REG_R_REMOTE_HIGHH 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LM90_REG_W_REMOTE_HIGHH 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LM90_REG_R_REMOTE_HIGHL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LM90_REG_W_REMOTE_HIGHL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LM90_REG_R_REMOTE_LOWH 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LM90_REG_W_REMOTE_LOWH 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LM90_REG_R_REMOTE_LOWL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LM90_REG_W_REMOTE_LOWL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LM90_REG_R_REMOTE_CRIT 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LM90_REG_W_REMOTE_CRIT 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LM90_REG_R_TCRIT_HYST 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LM90_REG_W_TCRIT_HYST 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* MAX6646/6647/6649/6654/6657/6658/6659/6695/6696 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MAX6657_REG_R_LOCAL_TEMPL 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MAX6696_REG_R_STATUS2 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MAX6659_REG_R_REMOTE_EMERG 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MAX6659_REG_W_REMOTE_EMERG 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MAX6659_REG_R_LOCAL_EMERG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MAX6659_REG_W_LOCAL_EMERG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* SA56004 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SA56004_REG_R_LOCAL_TEMPL 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LM90_MAX_CONVRATE_MS 16000 /* Maximum conversion rate in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* TMP451/TMP461 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TMP451_REG_R_LOCAL_TEMPL 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TMP451_REG_CONALERT 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TMP461_REG_CHEN 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TMP461_REG_DFC 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Device flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define LM90_FLAG_ADT7461_EXT (1 << 0) /* ADT7461 extended mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Device features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define LM90_HAVE_OFFSET (1 << 1) /* temperature offset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define LM90_HAVE_REM_LIMIT_EXT (1 << 3) /* extended remote limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define LM90_HAVE_EMERGENCY (1 << 4) /* 3rd upper (emergency) limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define LM90_HAVE_EMERGENCY_ALARM (1 << 5)/* emergency alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LM90_HAVE_TEMP3 (1 << 6) /* 3rd temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LM90_HAVE_BROKEN_ALERT (1 << 7) /* Broken alert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define LM90_HAVE_EXTENDED_TEMP (1 << 8) /* extended temperature support*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define LM90_PAUSE_FOR_CONFIG (1 << 9) /* Pause conversion for config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LM90_HAVE_CRIT (1 << 10)/* Chip supports CRIT/OVERT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define LM90_HAVE_CRIT_ALRM_SWP (1 << 11)/* critical alarm bits swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* LM90 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define LM90_STATUS_LTHRM (1 << 0) /* local THERM limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define LM90_STATUS_RTHRM (1 << 1) /* remote THERM limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LM90_STATUS_ROPEN (1 << 2) /* remote is an open circuit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LM90_STATUS_RLOW (1 << 3) /* remote low temp limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define LM90_STATUS_RHIGH (1 << 4) /* remote high temp limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define LM90_STATUS_LLOW (1 << 5) /* local low temp limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LM90_STATUS_LHIGH (1 << 6) /* local high temp limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LM90_STATUS_BUSY (1 << 7) /* conversion is ongoing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MAX6696_STATUS2_R2THRM (1 << 1) /* remote2 THERM limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MAX6696_STATUS2_R2OPEN (1 << 2) /* remote2 is an open circuit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MAX6696_STATUS2_R2LOW (1 << 3) /* remote2 low temp limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MAX6696_STATUS2_R2HIGH (1 << 4) /* remote2 high temp limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MAX6696_STATUS2_ROT2 (1 << 5) /* remote emergency limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MAX6696_STATUS2_R2OT2 (1 << 6) /* remote2 emergency limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MAX6696_STATUS2_LOT2 (1 << 7) /* local emergency limit tripped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Driver data (common to all clients)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct i2c_device_id lm90_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { "adm1032", adm1032 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { "adt7461", adt7461 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { "adt7461a", adt7461 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { "g781", g781 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { "lm90", lm90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { "lm86", lm86 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { "lm89", lm86 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { "lm99", lm99 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { "max6646", max6646 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { "max6647", max6646 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { "max6649", max6646 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { "max6654", max6654 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { "max6657", max6657 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { "max6658", max6657 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { "max6659", max6659 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { "max6680", max6680 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { "max6681", max6680 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { "max6695", max6696 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { "max6696", max6696 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { "nct1008", adt7461 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { "w83l771", w83l771 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { "sa56004", sa56004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { "tmp451", tmp451 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { "tmp461", tmp461 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_DEVICE_TABLE(i2c, lm90_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct of_device_id __maybe_unused lm90_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .compatible = "adi,adm1032",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .data = (void *)adm1032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .compatible = "adi,adt7461",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .data = (void *)adt7461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .compatible = "adi,adt7461a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .data = (void *)adt7461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .compatible = "gmt,g781",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .data = (void *)g781
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .compatible = "national,lm90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .data = (void *)lm90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .compatible = "national,lm86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .data = (void *)lm86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .compatible = "national,lm89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .data = (void *)lm86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .compatible = "national,lm99",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .data = (void *)lm99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .compatible = "dallas,max6646",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .data = (void *)max6646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .compatible = "dallas,max6647",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .data = (void *)max6646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .compatible = "dallas,max6649",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .data = (void *)max6646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .compatible = "dallas,max6654",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .data = (void *)max6654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .compatible = "dallas,max6657",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .data = (void *)max6657
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .compatible = "dallas,max6658",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .data = (void *)max6657
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .compatible = "dallas,max6659",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .data = (void *)max6659
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .compatible = "dallas,max6680",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .data = (void *)max6680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .compatible = "dallas,max6681",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .data = (void *)max6680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .compatible = "dallas,max6695",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .data = (void *)max6696
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .compatible = "dallas,max6696",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .data = (void *)max6696
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .compatible = "onnn,nct1008",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .data = (void *)adt7461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .compatible = "winbond,w83l771",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .data = (void *)w83l771
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .compatible = "nxp,sa56004",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .data = (void *)sa56004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .compatible = "ti,tmp451",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .data = (void *)tmp451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .compatible = "ti,tmp461",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .data = (void *)tmp461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_DEVICE_TABLE(of, lm90_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * chip type specific parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct lm90_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 flags; /* Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u16 alert_alarms; /* Which alarm bits trigger ALERT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Upper 8 bits for max6695/96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 max_convrate; /* Maximum conversion rate register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 reg_local_ext; /* Extended local temp register (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct lm90_params lm90_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [adm1032] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) | LM90_HAVE_BROKEN_ALERT | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .max_convrate = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [adt7461] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) | LM90_HAVE_BROKEN_ALERT | LM90_HAVE_EXTENDED_TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .max_convrate = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [g781] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) | LM90_HAVE_BROKEN_ALERT | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .max_convrate = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [lm86] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .alert_alarms = 0x7b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .max_convrate = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) [lm90] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .alert_alarms = 0x7b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .max_convrate = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) [lm99] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .alert_alarms = 0x7b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .max_convrate = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [max6646] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .flags = LM90_HAVE_CRIT | LM90_HAVE_BROKEN_ALERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .max_convrate = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .reg_local_ext = MAX6657_REG_R_LOCAL_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [max6654] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .flags = LM90_HAVE_BROKEN_ALERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .max_convrate = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .reg_local_ext = MAX6657_REG_R_LOCAL_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) [max6657] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .flags = LM90_PAUSE_FOR_CONFIG | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .max_convrate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .reg_local_ext = MAX6657_REG_R_LOCAL_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [max6659] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .flags = LM90_HAVE_EMERGENCY | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .max_convrate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .reg_local_ext = MAX6657_REG_R_LOCAL_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [max6680] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .flags = LM90_HAVE_OFFSET | LM90_HAVE_CRIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) | LM90_HAVE_CRIT_ALRM_SWP | LM90_HAVE_BROKEN_ALERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .max_convrate = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [max6696] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .flags = LM90_HAVE_EMERGENCY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) | LM90_HAVE_EMERGENCY_ALARM | LM90_HAVE_TEMP3 | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .alert_alarms = 0x1c7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .max_convrate = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .reg_local_ext = MAX6657_REG_R_LOCAL_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) [w83l771] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .max_convrate = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [sa56004] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .alert_alarms = 0x7b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .max_convrate = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .reg_local_ext = SA56004_REG_R_LOCAL_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [tmp451] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) | LM90_HAVE_BROKEN_ALERT | LM90_HAVE_EXTENDED_TEMP | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .max_convrate = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .reg_local_ext = TMP451_REG_R_LOCAL_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [tmp461] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .flags = LM90_HAVE_OFFSET | LM90_HAVE_REM_LIMIT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) | LM90_HAVE_BROKEN_ALERT | LM90_HAVE_EXTENDED_TEMP | LM90_HAVE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .alert_alarms = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .max_convrate = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .reg_local_ext = TMP451_REG_R_LOCAL_TEMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * TEMP8 register index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) enum lm90_temp8_reg_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) LOCAL_LOW = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) LOCAL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) LOCAL_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) REMOTE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) LOCAL_EMERG, /* max6659 and max6695/96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) REMOTE_EMERG, /* max6659 and max6695/96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) REMOTE2_CRIT, /* max6695/96 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) REMOTE2_EMERG, /* max6695/96 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) TEMP8_REG_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * TEMP11 register index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) enum lm90_temp11_reg_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) REMOTE_TEMP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) REMOTE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) REMOTE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) REMOTE_OFFSET, /* except max6646, max6657/58/59, and max6695/96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) LOCAL_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) REMOTE2_TEMP, /* max6695/96 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) REMOTE2_LOW, /* max6695/96 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) REMOTE2_HIGH, /* max6695/96 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) TEMP11_REG_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Client data (each client gets its own)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct lm90_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 channel_config[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct hwmon_channel_info temp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) const struct hwmon_channel_info *info[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct hwmon_chip_info chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bool valid; /* true if register values are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned long last_updated; /* in jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int kind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned int update_interval; /* in milliseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u8 config; /* Current configuration register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 config_orig; /* Original configuration register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 convrate_orig; /* Original conversion rate register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u16 alert_alarms; /* Which alarm bits trigger ALERT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Upper 8 bits for max6695/96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 max_convrate; /* Maximum conversion rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 reg_local_ext; /* local extension register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* registers values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) s8 temp8[TEMP8_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) s16 temp11[TEMP11_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 temp_hyst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u16 alarms; /* bitvector (upper 8 bits for max6695/96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Support functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * The ADM1032 supports PEC but not on write byte transactions, so we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * to explicitly ask for a transaction without PEC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static inline s32 adm1032_write_byte(struct i2c_client *client, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return i2c_smbus_xfer(client->adapter, client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) client->flags & ~I2C_CLIENT_PEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) I2C_SMBUS_WRITE, value, I2C_SMBUS_BYTE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * It is assumed that client->update_lock is held (unless we are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * detection or initialization steps). This matters when PEC is enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * because we don't want the address pointer to change between the write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * byte and the read byte transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int lm90_read_reg(struct i2c_client *client, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (client->flags & I2C_CLIENT_PEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) err = adm1032_write_byte(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) err = i2c_smbus_read_byte(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) err = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int lm90_read16(struct i2c_client *client, u8 regh, u8 regl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int oldh, newh, l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * There is a trick here. We have to read two registers to have the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * sensor temperature, but we have to beware a conversion could occur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * between the readings. The datasheet says we should either use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * the one-shot conversion register, which we don't want to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * (disables hardware monitoring) or monitor the busy bit, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * impossible (we can't read the values and monitor that bit at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * exact same time). So the solution used here is to read the high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * byte once, then the low byte, then the high byte again. If the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * high byte matches the old one, then we have a valid reading. Else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * we have to read the low byte again, and now we believe we have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * correct reading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) oldh = lm90_read_reg(client, regh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (oldh < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return oldh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) l = lm90_read_reg(client, regl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (l < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) newh = lm90_read_reg(client, regh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (newh < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return newh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (oldh != newh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) l = lm90_read_reg(client, regl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (l < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return (newh << 8) | l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int lm90_update_confreg(struct lm90_data *data, u8 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (data->config != config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) err = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) LM90_REG_W_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) data->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * client->update_lock must be held when calling this function (unless we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * in detection or initialization steps), and while a remote channel other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * than channel 0 is selected. Also, calling code must make sure to re-select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * external channel 0 before releasing the lock. This is necessary because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * various registers have different meanings as a result of selecting a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * non-default remote channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int lm90_select_remote_channel(struct lm90_data *data, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (data->kind == max6696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u8 config = data->config & ~0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) config |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) err = lm90_update_confreg(data, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int lm90_write_convrate(struct lm90_data *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u8 config = data->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Save config and pause conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (data->flags & LM90_PAUSE_FOR_CONFIG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) err = lm90_update_confreg(data, config | 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Set conv rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) err = i2c_smbus_write_byte_data(data->client, LM90_REG_W_CONVRATE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Revert change to config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) lm90_update_confreg(data, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Set conversion rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * client->update_lock must be held when calling this function (unless we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * in detection or initialization steps).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int lm90_set_convrate(struct i2c_client *client, struct lm90_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned int interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned int update_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Shift calculations to avoid rounding errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) interval <<= 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* find the nearest update rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) for (i = 0, update_interval = LM90_MAX_CONVRATE_MS << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) i < data->max_convrate; i++, update_interval >>= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (interval >= update_interval * 3 / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) err = lm90_write_convrate(data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) data->update_interval = DIV_ROUND_CLOSEST(update_interval, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int lm90_update_limits(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct lm90_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (data->flags & LM90_HAVE_CRIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) val = lm90_read_reg(client, LM90_REG_R_LOCAL_CRIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) data->temp8[LOCAL_CRIT] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) val = lm90_read_reg(client, LM90_REG_R_REMOTE_CRIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) data->temp8[REMOTE_CRIT] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val = lm90_read_reg(client, LM90_REG_R_TCRIT_HYST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) data->temp_hyst = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) val = lm90_read_reg(client, LM90_REG_R_REMOTE_LOWH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) data->temp11[REMOTE_LOW] = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (data->flags & LM90_HAVE_REM_LIMIT_EXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) val = lm90_read_reg(client, LM90_REG_R_REMOTE_LOWL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) data->temp11[REMOTE_LOW] |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) val = lm90_read_reg(client, LM90_REG_R_REMOTE_HIGHH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) data->temp11[REMOTE_HIGH] = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (data->flags & LM90_HAVE_REM_LIMIT_EXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) val = lm90_read_reg(client, LM90_REG_R_REMOTE_HIGHL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) data->temp11[REMOTE_HIGH] |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (data->flags & LM90_HAVE_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) val = lm90_read16(client, LM90_REG_R_REMOTE_OFFSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) LM90_REG_R_REMOTE_OFFSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) data->temp11[REMOTE_OFFSET] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (data->flags & LM90_HAVE_EMERGENCY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) val = lm90_read_reg(client, MAX6659_REG_R_LOCAL_EMERG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) data->temp8[LOCAL_EMERG] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) val = lm90_read_reg(client, MAX6659_REG_R_REMOTE_EMERG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) data->temp8[REMOTE_EMERG] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (data->kind == max6696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) val = lm90_select_remote_channel(data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) val = lm90_read_reg(client, LM90_REG_R_REMOTE_CRIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) data->temp8[REMOTE2_CRIT] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) val = lm90_read_reg(client, MAX6659_REG_R_REMOTE_EMERG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) data->temp8[REMOTE2_EMERG] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) val = lm90_read_reg(client, LM90_REG_R_REMOTE_LOWH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) data->temp11[REMOTE2_LOW] = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) val = lm90_read_reg(client, LM90_REG_R_REMOTE_HIGHH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) data->temp11[REMOTE2_HIGH] = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) lm90_select_remote_channel(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static int lm90_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct lm90_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned long next_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) val = lm90_update_limits(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) next_update = data->last_updated +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) msecs_to_jiffies(data->update_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (time_after(jiffies, next_update) || !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_dbg(&client->dev, "Updating lm90 data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) data->valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) val = lm90_read_reg(client, LM90_REG_R_LOCAL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) data->temp8[LOCAL_LOW] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) val = lm90_read_reg(client, LM90_REG_R_LOCAL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) data->temp8[LOCAL_HIGH] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (data->reg_local_ext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) val = lm90_read16(client, LM90_REG_R_LOCAL_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) data->reg_local_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) data->temp11[LOCAL_TEMP] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) val = lm90_read_reg(client, LM90_REG_R_LOCAL_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) data->temp11[LOCAL_TEMP] = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) val = lm90_read16(client, LM90_REG_R_REMOTE_TEMPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) LM90_REG_R_REMOTE_TEMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) data->temp11[REMOTE_TEMP] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) val = lm90_read_reg(client, LM90_REG_R_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) data->alarms = val & ~LM90_STATUS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (data->kind == max6696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) val = lm90_select_remote_channel(data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) val = lm90_read16(client, LM90_REG_R_REMOTE_TEMPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) LM90_REG_R_REMOTE_TEMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) lm90_select_remote_channel(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) data->temp11[REMOTE2_TEMP] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) lm90_select_remote_channel(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) val = lm90_read_reg(client, MAX6696_REG_R_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) data->alarms |= val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * Re-enable ALERT# output if it was originally enabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * relevant alarms are all clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!(data->config_orig & 0x80) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) !(data->alarms & data->alert_alarms)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (data->config & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dev_dbg(&client->dev, "Re-enabling ALERT#\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) lm90_update_confreg(data, data->config & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) data->valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * Conversions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * For local temperatures and limits, critical limits and the hysteresis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * value, the LM90 uses signed 8-bit values with LSB = 1 degree Celsius.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * For remote temperatures and limits, it uses signed 11-bit values with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * LSB = 0.125 degree Celsius, left-justified in 16-bit registers. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * Maxim chips use unsigned values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static inline int temp_from_s8(s8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return val * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static inline int temp_from_u8(u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return val * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static inline int temp_from_s16(s16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return val / 32 * 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static inline int temp_from_u16(u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return val / 32 * 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static s8 temp_to_s8(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (val <= -128000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (val >= 127000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return (val - 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return (val + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static u8 temp_to_u8(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (val <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (val >= 255000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return (val + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static s16 temp_to_s16(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (val <= -128000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (val >= 127875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0x7FE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return (val - 62) / 125 * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return (val + 62) / 125 * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static u8 hyst_to_reg(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (val <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (val >= 30500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return (val + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * ADT7461 in compatibility mode is almost identical to LM90 except that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * attempts to write values that are outside the range 0 < temp < 127 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * treated as the boundary value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * ADT7461 in "extended mode" operation uses unsigned integers offset by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * 64 (e.g., 0 -> -64 degC). The range is restricted to -64..191 degC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static inline int temp_from_u8_adt7461(struct lm90_data *data, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (data->flags & LM90_FLAG_ADT7461_EXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return (val - 64) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return temp_from_s8(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static inline int temp_from_u16_adt7461(struct lm90_data *data, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (data->flags & LM90_FLAG_ADT7461_EXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return (val - 0x4000) / 64 * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return temp_from_s16(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static u8 temp_to_u8_adt7461(struct lm90_data *data, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (data->flags & LM90_FLAG_ADT7461_EXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (val <= -64000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (val >= 191000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return (val + 500 + 64000) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (val <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (val >= 127000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return (val + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static u16 temp_to_u16_adt7461(struct lm90_data *data, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (data->flags & LM90_FLAG_ADT7461_EXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (val <= -64000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (val >= 191750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return 0xFFC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return (val + 64000 + 125) / 250 * 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (val <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (val >= 127750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return 0x7FC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return (val + 125) / 250 * 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* pec used for ADM1032 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static ssize_t pec_show(struct device *dev, struct device_attribute *dummy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return sprintf(buf, "%d\n", !!(client->flags & I2C_CLIENT_PEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static ssize_t pec_store(struct device *dev, struct device_attribute *dummy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) client->flags &= ~I2C_CLIENT_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) client->flags |= I2C_CLIENT_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static DEVICE_ATTR_RW(pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static int lm90_get_temp11(struct lm90_data *data, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) s16 temp11 = data->temp11[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (data->flags & LM90_HAVE_EXTENDED_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) temp = temp_from_u16_adt7461(data, temp11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) else if (data->kind == max6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) temp = temp_from_u16(temp11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) temp = temp_from_s16(temp11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* +16 degrees offset for temp2 for the LM99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (data->kind == lm99 && index <= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) temp += 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int lm90_set_temp11(struct lm90_data *data, int index, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static struct reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u8 high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u8 low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) } reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [REMOTE_LOW] = { LM90_REG_W_REMOTE_LOWH, LM90_REG_W_REMOTE_LOWL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [REMOTE_HIGH] = { LM90_REG_W_REMOTE_HIGHH, LM90_REG_W_REMOTE_HIGHL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) [REMOTE_OFFSET] = { LM90_REG_W_REMOTE_OFFSH, LM90_REG_W_REMOTE_OFFSL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [REMOTE2_LOW] = { LM90_REG_W_REMOTE_LOWH, LM90_REG_W_REMOTE_LOWL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [REMOTE2_HIGH] = { LM90_REG_W_REMOTE_HIGHH, LM90_REG_W_REMOTE_HIGHL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct reg *regp = ®[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* +16 degrees offset for temp2 for the LM99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (data->kind == lm99 && index <= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) val -= 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (data->flags & LM90_HAVE_EXTENDED_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) data->temp11[index] = temp_to_u16_adt7461(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) else if (data->kind == max6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) data->temp11[index] = temp_to_u8(val) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) else if (data->flags & LM90_HAVE_REM_LIMIT_EXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) data->temp11[index] = temp_to_s16(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) data->temp11[index] = temp_to_s8(val) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) lm90_select_remote_channel(data, index >= 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) err = i2c_smbus_write_byte_data(client, regp->high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) data->temp11[index] >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (data->flags & LM90_HAVE_REM_LIMIT_EXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) err = i2c_smbus_write_byte_data(client, regp->low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) data->temp11[index] & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) lm90_select_remote_channel(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static int lm90_get_temp8(struct lm90_data *data, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) s8 temp8 = data->temp8[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (data->flags & LM90_HAVE_EXTENDED_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) temp = temp_from_u8_adt7461(data, temp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) else if (data->kind == max6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) temp = temp_from_u8(temp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) temp = temp_from_s8(temp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* +16 degrees offset for temp2 for the LM99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (data->kind == lm99 && index == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) temp += 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int lm90_set_temp8(struct lm90_data *data, int index, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static const u8 reg[TEMP8_REG_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) LM90_REG_W_LOCAL_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) LM90_REG_W_LOCAL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) LM90_REG_W_LOCAL_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) LM90_REG_W_REMOTE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) MAX6659_REG_W_LOCAL_EMERG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) MAX6659_REG_W_REMOTE_EMERG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) LM90_REG_W_REMOTE_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) MAX6659_REG_W_REMOTE_EMERG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* +16 degrees offset for temp2 for the LM99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (data->kind == lm99 && index == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) val -= 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (data->flags & LM90_HAVE_EXTENDED_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) data->temp8[index] = temp_to_u8_adt7461(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) else if (data->kind == max6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) data->temp8[index] = temp_to_u8(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) data->temp8[index] = temp_to_s8(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) lm90_select_remote_channel(data, index >= 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) err = i2c_smbus_write_byte_data(client, reg[index], data->temp8[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) lm90_select_remote_channel(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static int lm90_get_temphyst(struct lm90_data *data, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (data->flags & LM90_HAVE_EXTENDED_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) temp = temp_from_u8_adt7461(data, data->temp8[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) else if (data->kind == max6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) temp = temp_from_u8(data->temp8[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) temp = temp_from_s8(data->temp8[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* +16 degrees offset for temp2 for the LM99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (data->kind == lm99 && index == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) temp += 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return temp - temp_from_s8(data->temp_hyst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static int lm90_set_temphyst(struct lm90_data *data, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (data->flags & LM90_HAVE_EXTENDED_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) temp = temp_from_u8_adt7461(data, data->temp8[LOCAL_CRIT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) else if (data->kind == max6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) temp = temp_from_u8(data->temp8[LOCAL_CRIT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) temp = temp_from_s8(data->temp8[LOCAL_CRIT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) data->temp_hyst = hyst_to_reg(temp - val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) err = i2c_smbus_write_byte_data(client, LM90_REG_W_TCRIT_HYST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) data->temp_hyst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static const u8 lm90_temp_index[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) LOCAL_TEMP, REMOTE_TEMP, REMOTE2_TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static const u8 lm90_temp_min_index[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) LOCAL_LOW, REMOTE_LOW, REMOTE2_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static const u8 lm90_temp_max_index[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) LOCAL_HIGH, REMOTE_HIGH, REMOTE2_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static const u8 lm90_temp_crit_index[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) LOCAL_CRIT, REMOTE_CRIT, REMOTE2_CRIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static const u8 lm90_temp_emerg_index[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) LOCAL_EMERG, REMOTE_EMERG, REMOTE2_EMERG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static const u8 lm90_min_alarm_bits[3] = { 5, 3, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static const u8 lm90_max_alarm_bits[3] = { 6, 4, 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static const u8 lm90_crit_alarm_bits[3] = { 0, 1, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const u8 lm90_crit_alarm_bits_swapped[3] = { 1, 0, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static const u8 lm90_emergency_alarm_bits[3] = { 15, 13, 14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const u8 lm90_fault_bits[3] = { 0, 2, 10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int lm90_temp_read(struct device *dev, u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct lm90_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) err = lm90_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) *val = lm90_get_temp11(data, lm90_temp_index[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) *val = (data->alarms >> lm90_min_alarm_bits[channel]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) *val = (data->alarms >> lm90_max_alarm_bits[channel]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (data->flags & LM90_HAVE_CRIT_ALRM_SWP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) *val = (data->alarms >> lm90_crit_alarm_bits_swapped[channel]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) *val = (data->alarms >> lm90_crit_alarm_bits[channel]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) case hwmon_temp_emergency_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) *val = (data->alarms >> lm90_emergency_alarm_bits[channel]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) *val = (data->alarms >> lm90_fault_bits[channel]) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) *val = lm90_get_temp8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) lm90_temp_min_index[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) *val = lm90_get_temp11(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) lm90_temp_min_index[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) *val = lm90_get_temp8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) lm90_temp_max_index[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) *val = lm90_get_temp11(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) lm90_temp_max_index[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) *val = lm90_get_temp8(data, lm90_temp_crit_index[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case hwmon_temp_crit_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) *val = lm90_get_temphyst(data, lm90_temp_crit_index[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) case hwmon_temp_emergency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) *val = lm90_get_temp8(data, lm90_temp_emerg_index[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) case hwmon_temp_emergency_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) *val = lm90_get_temphyst(data, lm90_temp_emerg_index[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) *val = lm90_get_temp11(data, REMOTE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static int lm90_temp_write(struct device *dev, u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct lm90_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) err = lm90_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) err = lm90_set_temp8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) lm90_temp_min_index[channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) err = lm90_set_temp11(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) lm90_temp_min_index[channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) err = lm90_set_temp8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) lm90_temp_max_index[channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) err = lm90_set_temp11(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) lm90_temp_max_index[channel],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) err = lm90_set_temp8(data, lm90_temp_crit_index[channel], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) case hwmon_temp_crit_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) err = lm90_set_temphyst(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case hwmon_temp_emergency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) err = lm90_set_temp8(data, lm90_temp_emerg_index[channel], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) err = lm90_set_temp11(data, REMOTE_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static umode_t lm90_temp_is_visible(const void *data, u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) case hwmon_temp_emergency_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) case hwmon_temp_emergency_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) case hwmon_temp_emergency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) case hwmon_temp_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) case hwmon_temp_crit_hyst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static int lm90_chip_read(struct device *dev, u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct lm90_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) err = lm90_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) *val = data->update_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) case hwmon_chip_alarms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) *val = data->alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static int lm90_chip_write(struct device *dev, u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) struct lm90_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) err = lm90_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) err = lm90_set_convrate(client, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) clamp_val(val, 0, 100000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static umode_t lm90_chip_is_visible(const void *data, u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) case hwmon_chip_update_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) case hwmon_chip_alarms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static int lm90_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return lm90_chip_read(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return lm90_temp_read(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static int lm90_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return lm90_chip_write(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return lm90_temp_write(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static umode_t lm90_is_visible(const void *data, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) case hwmon_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return lm90_chip_is_visible(data, attr, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return lm90_temp_is_visible(data, attr, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* Return 0 if detection is successful, -ENODEV otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static int lm90_detect(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) int address = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) const char *name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) int man_id, chip_id, config1, config2, convrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* detection and identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) man_id = i2c_smbus_read_byte_data(client, LM90_REG_R_MAN_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) chip_id = i2c_smbus_read_byte_data(client, LM90_REG_R_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) config1 = i2c_smbus_read_byte_data(client, LM90_REG_R_CONFIG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) convrate = i2c_smbus_read_byte_data(client, LM90_REG_R_CONVRATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (man_id < 0 || chip_id < 0 || config1 < 0 || convrate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (man_id == 0x01 || man_id == 0x5C || man_id == 0xA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) config2 = i2c_smbus_read_byte_data(client, LM90_REG_R_CONFIG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (config2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if ((address == 0x4C || address == 0x4D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) && man_id == 0x01) { /* National Semiconductor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if ((config1 & 0x2A) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) && (config2 & 0xF8) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) && convrate <= 0x09) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (address == 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) && (chip_id & 0xF0) == 0x20) { /* LM90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) name = "lm90";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if ((chip_id & 0xF0) == 0x30) { /* LM89/LM99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) name = "lm99";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) dev_info(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) "Assuming LM99 chip at 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) dev_info(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) "If it is an LM89, instantiate it "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) "with the new_device sysfs "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) "interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (address == 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) && (chip_id & 0xF0) == 0x10) { /* LM86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) name = "lm86";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if ((address == 0x4C || address == 0x4D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) && man_id == 0x41) { /* Analog Devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if ((chip_id & 0xF0) == 0x40 /* ADM1032 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) && (config1 & 0x3F) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) && convrate <= 0x0A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) name = "adm1032";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * The ADM1032 supports PEC, but only if combined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * transactions are not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (i2c_check_functionality(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) I2C_FUNC_SMBUS_BYTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) info->flags |= I2C_CLIENT_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (chip_id == 0x51 /* ADT7461 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) && (config1 & 0x1B) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) && convrate <= 0x0A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) name = "adt7461";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (chip_id == 0x57 /* ADT7461A, NCT1008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) && (config1 & 0x1B) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) && convrate <= 0x0A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) name = "adt7461a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (man_id == 0x4D) { /* Maxim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) int emerg, emerg2, status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * We read MAX6659_REG_R_REMOTE_EMERG twice, and re-read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * LM90_REG_R_MAN_ID in between. If MAX6659_REG_R_REMOTE_EMERG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * exists, both readings will reflect the same value. Otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * the readings will be different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) emerg = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) MAX6659_REG_R_REMOTE_EMERG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) man_id = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) LM90_REG_R_MAN_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) emerg2 = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) MAX6659_REG_R_REMOTE_EMERG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) status2 = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) MAX6696_REG_R_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (emerg < 0 || man_id < 0 || emerg2 < 0 || status2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * The MAX6657, MAX6658 and MAX6659 do NOT have a chip_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * register. Reading from that address will return the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * read value, which in our case is those of the man_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * register. Likewise, the config1 register seems to lack a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * low nibble, so the value will be those of the previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * read, so in our case those of the man_id register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * MAX6659 has a third set of upper temperature limit registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * Those registers also return values on MAX6657 and MAX6658,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * thus the only way to detect MAX6659 is by its address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * For this reason it will be mis-detected as MAX6657 if its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * address is 0x4C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (chip_id == man_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) && (address == 0x4C || address == 0x4D || address == 0x4E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) && (config1 & 0x1F) == (man_id & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) && convrate <= 0x09) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (address == 0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) name = "max6657";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) name = "max6659";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) * Even though MAX6695 and MAX6696 do not have a chip ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * register, reading it returns 0x01. Bit 4 of the config1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) * register is unused and should return zero when read. Bit 0 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * the status2 register is unused and should return zero when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) * MAX6695 and MAX6696 have an additional set of temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * limit registers. We can detect those chips by checking if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * one of those registers exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (chip_id == 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) && (config1 & 0x10) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) && (status2 & 0x01) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) && emerg == emerg2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) && convrate <= 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) name = "max6696";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * The chip_id register of the MAX6680 and MAX6681 holds the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * revision of the chip. The lowest bit of the config1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) * is unused and should return zero when read, so should the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) * second to last bit of config1 (software reset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (chip_id == 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) && (config1 & 0x03) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) && convrate <= 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) name = "max6680";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * The chip_id register of the MAX6646/6647/6649 holds the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * revision of the chip. The lowest 6 bits of the config1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * register are unused and should return zero when read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (chip_id == 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) && (config1 & 0x3f) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) && convrate <= 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) name = "max6646";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * The chip_id of the MAX6654 holds the revision of the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * The lowest 3 bits of the config1 register are unused and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * should return zero when read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (chip_id == 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) && (config1 & 0x07) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) && convrate <= 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) name = "max6654";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (address == 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) && man_id == 0x5C) { /* Winbond/Nuvoton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if ((config1 & 0x2A) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) && (config2 & 0xF8) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (chip_id == 0x01 /* W83L771W/G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) && convrate <= 0x09) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) name = "w83l771";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if ((chip_id & 0xFE) == 0x10 /* W83L771AWG/ASG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) && convrate <= 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) name = "w83l771";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (address >= 0x48 && address <= 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) && man_id == 0xA1) { /* NXP Semiconductor/Philips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (chip_id == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) && (config1 & 0x2A) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) && (config2 & 0xFE) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) && convrate <= 0x09) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) name = "sa56004";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if ((address == 0x4C || address == 0x4D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) && man_id == 0x47) { /* GMT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (chip_id == 0x01 /* G781 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) && (config1 & 0x3F) == 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) && convrate <= 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) name = "g781";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (man_id == 0x55 && chip_id == 0x00 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) (config1 & 0x1B) == 0x00 && convrate <= 0x09) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) int local_ext, conalert, chen, dfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) local_ext = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) TMP451_REG_R_LOCAL_TEMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) conalert = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) TMP451_REG_CONALERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) chen = i2c_smbus_read_byte_data(client, TMP461_REG_CHEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) dfc = i2c_smbus_read_byte_data(client, TMP461_REG_DFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if ((local_ext & 0x0F) == 0x00 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) (conalert & 0xf1) == 0x01 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) (chen & 0xfc) == 0x00 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) (dfc & 0xfc) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (address == 0x4c && !(chen & 0x03))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) name = "tmp451";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) else if (address >= 0x48 && address <= 0x4f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) name = "tmp461";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (!name) { /* identification failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) dev_dbg(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) "Unsupported chip at 0x%02x (man_id=0x%02X, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) "chip_id=0x%02X)\n", address, man_id, chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) strlcpy(info->type, name, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) static void lm90_restore_conf(void *_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct lm90_data *data = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /* Restore initial configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) lm90_write_convrate(data, data->convrate_orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) i2c_smbus_write_byte_data(client, LM90_REG_W_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) data->config_orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static int lm90_init_client(struct i2c_client *client, struct lm90_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) int config, convrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) convrate = lm90_read_reg(client, LM90_REG_R_CONVRATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (convrate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return convrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) data->convrate_orig = convrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) * Start the conversions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) config = lm90_read_reg(client, LM90_REG_R_CONFIG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (config < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) data->config_orig = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) data->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) lm90_set_convrate(client, data, 500); /* 500ms; 2Hz conversion rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* Check Temperature Range Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (data->flags & LM90_HAVE_EXTENDED_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (config & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) data->flags |= LM90_FLAG_ADT7461_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) * Put MAX6680/MAX8881 into extended resolution (bit 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) * 0.125 degree resolution) and range (0x08, extend range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) * to -64 degree) mode for the remote temperature sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (data->kind == max6680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) config |= 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) * Put MAX6654 into extended range (0x20, extend minimum range from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * 0 degrees to -64 degrees). Note that extended resolution is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * possible on the MAX6654 unless conversion rate is set to 1 Hz or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * slower, which is intentionally not done by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (data->kind == max6654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) config |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * Select external channel 0 for max6695/96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (data->kind == max6696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) config &= ~0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) config &= 0xBF; /* run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) lm90_update_confreg(data, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) return devm_add_action_or_reset(&client->dev, lm90_restore_conf, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static bool lm90_is_tripped(struct i2c_client *client, u16 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) struct lm90_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) int st, st2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) st = lm90_read_reg(client, LM90_REG_R_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (st < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (data->kind == max6696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) st2 = lm90_read_reg(client, MAX6696_REG_R_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (st2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) *status = st | (st2 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if ((st & 0x7f) == 0 && (st2 & 0xfe) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if ((st & (LM90_STATUS_LLOW | LM90_STATUS_LHIGH | LM90_STATUS_LTHRM)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) (st2 & MAX6696_STATUS2_LOT2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) "temp%d out of range, please check!\n", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if ((st & (LM90_STATUS_RLOW | LM90_STATUS_RHIGH | LM90_STATUS_RTHRM)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) (st2 & MAX6696_STATUS2_ROT2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) "temp%d out of range, please check!\n", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (st & LM90_STATUS_ROPEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) "temp%d diode open, please check!\n", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (st2 & (MAX6696_STATUS2_R2LOW | MAX6696_STATUS2_R2HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) MAX6696_STATUS2_R2THRM | MAX6696_STATUS2_R2OT2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) "temp%d out of range, please check!\n", 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (st2 & MAX6696_STATUS2_R2OPEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) "temp%d diode open, please check!\n", 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static irqreturn_t lm90_irq_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) struct i2c_client *client = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (lm90_is_tripped(client, &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static void lm90_remove_pec(void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) device_remove_file(dev, &dev_attr_pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static void lm90_regulator_disable(void *regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) regulator_disable(regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static const struct hwmon_ops lm90_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .is_visible = lm90_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .read = lm90_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .write = lm90_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static int lm90_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct hwmon_channel_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct lm90_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) regulator = devm_regulator_get(dev, "vcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (IS_ERR(regulator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return PTR_ERR(regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) err = regulator_enable(regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) dev_err(dev, "Failed to enable regulator: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) err = devm_add_action_or_reset(dev, lm90_regulator_disable, regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) data = devm_kzalloc(dev, sizeof(struct lm90_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /* Set the device type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) data->kind = (enum chips)of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) data->kind = i2c_match_id(lm90_id, client)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (data->kind == adm1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) client->flags &= ~I2C_CLIENT_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * Different devices have different alarm bits triggering the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * ALERT# output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) data->alert_alarms = lm90_params[data->kind].alert_alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /* Set chip capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) data->flags = lm90_params[data->kind].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) data->chip.ops = &lm90_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) data->chip.info = data->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) data->info[0] = HWMON_CHANNEL_INFO(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL | HWMON_C_ALARMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) data->info[1] = &data->temp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) info = &data->temp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) info->type = hwmon_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) info->config = data->channel_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) data->channel_config[0] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) data->channel_config[1] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | HWMON_T_FAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (data->flags & LM90_HAVE_CRIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) data->channel_config[0] |= HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_CRIT_HYST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) data->channel_config[1] |= HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_CRIT_HYST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (data->flags & LM90_HAVE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) data->channel_config[1] |= HWMON_T_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (data->flags & LM90_HAVE_EMERGENCY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) data->channel_config[0] |= HWMON_T_EMERGENCY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) HWMON_T_EMERGENCY_HYST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) data->channel_config[1] |= HWMON_T_EMERGENCY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) HWMON_T_EMERGENCY_HYST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (data->flags & LM90_HAVE_EMERGENCY_ALARM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) data->channel_config[0] |= HWMON_T_EMERGENCY_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) data->channel_config[1] |= HWMON_T_EMERGENCY_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (data->flags & LM90_HAVE_TEMP3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) data->channel_config[2] = HWMON_T_INPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) HWMON_T_MIN | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) HWMON_T_CRIT | HWMON_T_CRIT_HYST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) HWMON_T_EMERGENCY | HWMON_T_EMERGENCY_HYST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) HWMON_T_CRIT_ALARM | HWMON_T_EMERGENCY_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) HWMON_T_FAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) data->reg_local_ext = lm90_params[data->kind].reg_local_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) /* Set maximum conversion rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) data->max_convrate = lm90_params[data->kind].max_convrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* Initialize the LM90 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) err = lm90_init_client(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) dev_err(dev, "Failed to initialize device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * The 'pec' attribute is attached to the i2c device and thus created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) * separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (client->flags & I2C_CLIENT_PEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) err = device_create_file(dev, &dev_attr_pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) err = devm_add_action_or_reset(dev, lm90_remove_pec, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) data, &data->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (IS_ERR(hwmon_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) return PTR_ERR(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) dev_dbg(dev, "IRQ: %d\n", client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) err = devm_request_threaded_irq(dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) NULL, lm90_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) "lm90", client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) dev_err(dev, "cannot request IRQ %d\n", client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static void lm90_alert(struct i2c_client *client, enum i2c_alert_protocol type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) unsigned int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) u16 alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (type != I2C_PROTOCOL_SMBUS_ALERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) if (lm90_is_tripped(client, &alarms)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * Disable ALERT# output, because these chips don't implement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * SMBus alert correctly; they should only hold the alert line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) * low briefly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) struct lm90_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if ((data->flags & LM90_HAVE_BROKEN_ALERT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) (alarms & data->alert_alarms)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) dev_dbg(&client->dev, "Disabling ALERT#\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) lm90_update_confreg(data, data->config | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) dev_info(&client->dev, "Everything OK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) static struct i2c_driver lm90_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .name = "lm90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .of_match_table = of_match_ptr(lm90_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .probe_new = lm90_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .alert = lm90_alert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .id_table = lm90_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .detect = lm90_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .address_list = normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) module_i2c_driver(lm90_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) MODULE_DESCRIPTION("LM90/ADM1032 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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