^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * k8temp.c - Linux kernel module for hardware monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Rudolf Marek <r.marek@assembler.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Inspired from the w83785 and amd756 drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEMP_FROM_REG(val) (((((val) >> 16) & 0xff) - 49) * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_TEMP 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SEL_PLACE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SEL_CORE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct k8temp_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* registers values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 sensorsp; /* sensor presence bits - SEL_CORE, SEL_PLACE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 swap_core_select; /* meaning of SEL_CORE is inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 temp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct pci_device_id k8temp_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MODULE_DEVICE_TABLE(pci, k8temp_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int is_rev_g_desktop(u8 model)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 brandidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (model < 0x69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (model == 0xc1 || model == 0x6c || model == 0x7c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Differentiate between AM2 and ASB1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * See "Constructing the processor Name String" in "Revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Guide for AMD NPT Family 0Fh Processors" (33610).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) brandidx = cpuid_ebx(0x80000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) brandidx = (brandidx >> 9) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Single core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if ((model == 0x6f || model == 0x7f) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (brandidx == 0x7 || brandidx == 0x9 || brandidx == 0xc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Dual core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (model == 0x6b &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (brandidx == 0xb || brandidx == 0xc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static umode_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) k8temp_is_visible(const void *drvdata, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const struct k8temp_data *data = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if ((channel & 1) && !(data->sensorsp & SEL_PLACE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if ((channel & 2) && !(data->sensorsp & SEL_CORE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) k8temp_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct k8temp_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct pci_dev *pdev = to_pci_dev(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int core, place;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) core = (channel >> 1) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) place = channel & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) core ^= data->swap_core_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pci_read_config_byte(pdev, REG_TEMP, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tmp &= ~(SEL_PLACE | SEL_CORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tmp |= SEL_CORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (place)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tmp |= SEL_PLACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pci_write_config_byte(pdev, REG_TEMP, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pci_read_config_dword(pdev, REG_TEMP, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *val = TEMP_FROM_REG(temp) + data->temp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct hwmon_ops k8temp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .is_visible = k8temp_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .read = k8temp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct hwmon_channel_info *k8temp_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) HWMON_T_INPUT, HWMON_T_INPUT, HWMON_T_INPUT, HWMON_T_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct hwmon_chip_info k8temp_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .ops = &k8temp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .info = k8temp_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int k8temp_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 scfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 model, stepping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct k8temp_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) data = devm_kzalloc(&pdev->dev, sizeof(struct k8temp_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) model = boot_cpu_data.x86_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) stepping = boot_cpu_data.x86_stepping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* feature available since SH-C0, exclude older revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if ((model == 4 && stepping == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) (model == 5 && stepping <= 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * AMD NPT family 0fh, i.e. RevF and RevG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * meaning of SEL_CORE bit is inverted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (model >= 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) data->swap_core_select = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "Temperature readouts might be wrong - check erratum #141\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * RevG desktop CPUs (i.e. no socket S1G1 or ASB1 parts) need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * additional offset, otherwise reported temperature is below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * ambient temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (is_rev_g_desktop(model))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) data->temp_offset = 21000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pci_read_config_byte(pdev, REG_TEMP, &scfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) scfg &= ~(SEL_PLACE | SEL_CORE); /* Select sensor 0, core0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pci_write_config_byte(pdev, REG_TEMP, scfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pci_read_config_byte(pdev, REG_TEMP, &scfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (scfg & (SEL_PLACE | SEL_CORE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(&pdev->dev, "Configuration bit(s) stuck at 1!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) scfg |= (SEL_PLACE | SEL_CORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pci_write_config_byte(pdev, REG_TEMP, scfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* now we know if we can change core and/or sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pci_read_config_byte(pdev, REG_TEMP, &data->sensorsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (data->sensorsp & SEL_PLACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) scfg &= ~SEL_CORE; /* Select sensor 1, core0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pci_write_config_byte(pdev, REG_TEMP, scfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pci_read_config_dword(pdev, REG_TEMP, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) scfg |= SEL_CORE; /* prepare for next selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!((temp >> 16) & 0xff)) /* if temp is 0 -49C is unlikely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) data->sensorsp &= ~SEL_PLACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (data->sensorsp & SEL_CORE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) scfg &= ~SEL_PLACE; /* Select sensor 0, core1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pci_write_config_byte(pdev, REG_TEMP, scfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pci_read_config_dword(pdev, REG_TEMP, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!((temp >> 16) & 0xff)) /* if temp is 0 -49C is unlikely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) data->sensorsp &= ~SEL_CORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "k8temp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) &k8temp_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct pci_driver k8temp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "k8temp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .id_table = k8temp_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .probe = k8temp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) module_pci_driver(k8temp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_DESCRIPTION("AMD K8 core temperature monitor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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