^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * it87.c - Part of lm_sensors, Linux kernel modules for hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * monitoring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * addition to an Environment Controller (Enhanced Hardware Monitor and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Fan Controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This driver supports only the Environment Controller in the IT8705F and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * similar parts. The other devices are supported by different drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Supports: IT8603E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IT8620E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * IT8622E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IT8623E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * IT8628E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * IT8705F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * IT8712F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * IT8716F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * IT8718F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * IT8720F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * IT8721F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * IT8726F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * IT8728F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * IT8732F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * IT8758E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * IT8771E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * IT8772E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * IT8781F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * IT8782F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * IT8783E/F Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * IT8786E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * IT8790E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * IT8792E Super I/O chip w/LPC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Sis950 A clone of the IT8705F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Copyright (C) 2001 Chris Gauthron
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/hwmon-vid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRVNAME "it87"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) it8771, it8772, it8781, it8782, it8783, it8786, it8790,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) it8792, it8603, it8620, it8622, it8628 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static unsigned short force_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) module_param(force_id, ushort, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_PARM_DESC(force_id, "Override the detected device ID");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct platform_device *it87_pdev[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_2E 0x2e /* The register to read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_4E 0x4e /* Secondary register to read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DEV 0x07 /* Register: Logical device select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PME 0x04 /* The device with the fan registers in it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* The device with the IT8718F/IT8720F VID value in it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GPIO 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DEVID 0x20 /* Register: Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DEVREV 0x22 /* Register: Device Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline int superio_inb(int ioreg, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) outb(reg, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return inb(ioreg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline void superio_outb(int ioreg, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) outb(reg, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) outb(val, ioreg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int superio_inw(int ioreg, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) outb(reg++, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) val = inb(ioreg + 1) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) outb(reg, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val |= inb(ioreg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline void superio_select(int ioreg, int ldn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) outb(DEV, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) outb(ldn, ioreg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline int superio_enter(int ioreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Try to reserve ioreg and ioreg + 1 for exclusive access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!request_muxed_region(ioreg, 2, DRVNAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) outb(0x87, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) outb(0x01, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) outb(0x55, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline void superio_exit(int ioreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) outb(0x02, ioreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) outb(0x02, ioreg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) release_region(ioreg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Logical device 4 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IT8712F_DEVID 0x8712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IT8705F_DEVID 0x8705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IT8716F_DEVID 0x8716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IT8718F_DEVID 0x8718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IT8720F_DEVID 0x8720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IT8721F_DEVID 0x8721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IT8726F_DEVID 0x8726
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IT8728F_DEVID 0x8728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IT8732F_DEVID 0x8732
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IT8792E_DEVID 0x8733
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IT8771E_DEVID 0x8771
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IT8772E_DEVID 0x8772
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IT8781F_DEVID 0x8781
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IT8782F_DEVID 0x8782
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IT8783E_DEVID 0x8783
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IT8786E_DEVID 0x8786
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IT8790E_DEVID 0x8790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IT8603E_DEVID 0x8603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IT8620E_DEVID 0x8620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IT8622E_DEVID 0x8622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IT8623E_DEVID 0x8623
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IT8628E_DEVID 0x8628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IT87_ACT_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IT87_BASE_REG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Logical device 7 registers (IT8712F and later) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IT87_SIO_GPIO1_REG 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IT87_SIO_GPIO2_REG 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IT87_SIO_GPIO3_REG 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IT87_SIO_GPIO4_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IT87_SIO_GPIO5_REG 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IT87_SIO_VID_REG 0xfc /* VID value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Update battery voltage after every reading if true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static bool update_vbat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Not all BIOSes properly configure the PWM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static bool fix_pwm_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Many IT87 constants specified below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Length of ISA address segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IT87_EXTENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Length of ISA address segment for Environmental Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IT87_EC_EXTENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Offset of EC registers from ISA base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IT87_EC_OFFSET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Where are the ISA address/data registers relative to the EC base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IT87_ADDR_REG_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IT87_DATA_REG_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*----- The IT87 registers -----*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IT87_REG_CONFIG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IT87_REG_ALARM1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IT87_REG_ALARM2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IT87_REG_ALARM3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * The IT8718F and IT8720F have the VID value in a different register, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Super-I/O configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IT87_REG_VID 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IT87_REG_FAN_DIV 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IT87_REG_FAN_16BIT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Monitors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * - up to 6 temp (1 to 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * - up to 6 fan (1 to 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IT87_REG_FAN_MAIN_CTRL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IT87_REG_FAN_CTL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IT87_REG_TEMP(nr) (0x29 + (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IT87_REG_VIN_ENABLE 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IT87_REG_TEMP_ENABLE 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IT87_REG_TEMP_EXTRA 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IT87_REG_BEEP_ENABLE 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IT87_REG_CHIPID 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IT87_REG_TEMP456_ENABLE 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define NUM_VIN_LIMIT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define NUM_TEMP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define NUM_TEMP_LIMIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define NUM_FAN_DIV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct it87_devices {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const char * const suffix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 peci_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 old_peci_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FEAT_12MV_ADC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define FEAT_NEWER_AUTOPWM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define FEAT_OLD_AUTOPWM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define FEAT_16BIT_FANS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define FEAT_TEMP_OFFSET BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define FEAT_TEMP_PECI BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define FEAT_TEMP_OLD_PECI BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define FEAT_VID BIT(9) /* Set if chip supports VID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define FEAT_SIX_FANS BIT(11) /* Supports six fans */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define FEAT_10_9MV_ADC BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct it87_devices it87_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [it87] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .name = "it87",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [it8712] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "it8712",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .features = FEAT_OLD_AUTOPWM | FEAT_VID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* may need to overwrite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [it8716] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "it8716",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [it8718] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .name = "it8718",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .old_peci_mask = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [it8720] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "it8720",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .old_peci_mask = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [it8721] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .name = "it8721",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .peci_mask = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .old_peci_mask = 0x02, /* Actually reports PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [it8728] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .name = "it8728",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [it8732] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "it8732",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .old_peci_mask = 0x02, /* Actually reports PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) [it8771] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .name = "it8771",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .suffix = "E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* PECI: guesswork */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* 12mV ADC (OHM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* 16 bit fans (OHM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* three fans, always 16 bit (guesswork) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [it8772] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .name = "it8772",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .suffix = "E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* PECI (coreboot) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* 12mV ADC (HWSensors4, OHM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* 16 bit fans (HWSensors4, OHM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* three fans, always 16 bit (datasheet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [it8781] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .name = "it8781",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .old_peci_mask = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [it8782] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = "it8782",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .suffix = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .old_peci_mask = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [it8783] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .name = "it8783",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .suffix = "E/F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .old_peci_mask = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [it8786] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .name = "it8786",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .suffix = "E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [it8790] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "it8790",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .suffix = "E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [it8792] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .name = "it8792",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .suffix = "E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .old_peci_mask = 0x02, /* Actually reports PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [it8603] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .name = "it8603",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .suffix = "E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) | FEAT_AVCC3 | FEAT_PWM_FREQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) [it8620] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .name = "it8620",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .suffix = "E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) | FEAT_SIX_TEMP | FEAT_VIN3_5V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [it8622] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .name = "it8622",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .suffix = "E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) | FEAT_AVCC3 | FEAT_VIN3_5V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) [it8628] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .name = "it8628",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .suffix = "E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) | FEAT_SIX_TEMP | FEAT_VIN3_5V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .peci_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ((data)->peci_mask & BIT(nr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define has_temp_old_peci(data, nr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (((data)->features & FEAT_TEMP_OLD_PECI) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ((data)->old_peci_mask & BIT(nr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) FEAT_SIX_FANS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define has_vid(data) ((data)->features & FEAT_VID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define has_avcc3(data) ((data)->features & FEAT_AVCC3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) | FEAT_SIX_PWM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct it87_sio_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int sioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) enum chips type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Values read from Super-I/O config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 vid_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 beep_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 internal; /* Internal sensors can be labeled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bool need_in7_reroute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Features skipped based on config or DMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u16 skip_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 skip_vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 skip_fan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 skip_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 skip_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * For each registered chip, we need to keep some data in memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * The structure is dynamically allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct it87_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) const struct attribute_group *groups[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int sioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) enum chips type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 peci_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 old_peci_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned short addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) char valid; /* !=0 if following fields are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned long last_updated; /* In jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u16 in_scaled; /* Internal voltage sensors are scaled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u16 in_internal; /* Bitfield, internal sensors (for labels) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u16 has_in; /* Bitfield, voltage sensors enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bool need_in7_reroute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 has_fan; /* Bitfield, fans enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u8 has_temp; /* Bitfield, temp sensors enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) bool has_vid; /* True if VID supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u8 vid; /* Register encoding, combined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u8 vrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 alarms; /* Register encoding, combined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) bool has_beep; /* true if beep supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u8 beeps; /* Register encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 fan_main_ctrl; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u8 fan_ctl; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * The following 3 arrays correspond to the same registers up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * the IT8720F. The meaning of bits 6-0 depends on the value of bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * 7, and we want to preserve settings on mode changes, so we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * to track all values separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * Starting with the IT8721F, the manual PWM duty cycles are stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * in separate registers (8-bit values), so the separate tracking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * is no longer needed, but it is still done to keep the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * simple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u8 has_pwm; /* Bitfield, pwm control enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u8 pwm_ctrl[NUM_PWM]; /* Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Automatic fan speed control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int adc_lsb(const struct it87_data *data, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (has_12mv_adc(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) lsb = 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) else if (has_10_9mv_adc(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) lsb = 109;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) lsb = 160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (data->in_scaled & BIT(nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) lsb <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static u8 in_to_reg(const struct it87_data *data, int nr, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int in_from_reg(const struct it87_data *data, int nr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static inline u8 FAN_TO_REG(long rpm, int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (rpm == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) rpm = clamp_val(rpm, 1, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static inline u16 FAN16_TO_REG(long rpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (rpm == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 1350000 / ((val) * (div)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* The divider is fixed to 2 in 16-bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 1350000 / ((val) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ((val) + 500) / 1000), -128, 127))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define TEMP_FROM_REG(val) ((val) * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static u8 pwm_to_reg(const struct it87_data *data, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (has_newer_autopwm(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return val >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int pwm_from_reg(const struct it87_data *data, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (has_newer_autopwm(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return (reg & 0x7f) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int DIV_TO_REG(int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int answer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) while (answer < 7 && (val >>= 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) answer++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return answer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define DIV_FROM_REG(val) BIT(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * PWM base frequencies. The frequency has to be divided by either 128 or 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * depending on the chip type, to calculate the actual PWM frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Some of the chip datasheets suggest a base frequency of 51 kHz instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * of 200 Hz. Sometimes both PWM frequency select registers are affected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * sometimes just one. It is unknown if this is a datasheet error or real,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * so this is ignored for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const unsigned int pwm_freq[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 8000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 750000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Must be called with data->update_lock held, except during initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * would slow down the IT87 access and should not be necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int it87_read_value(struct it87_data *data, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return inb_p(data->addr + IT87_DATA_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * Must be called with data->update_lock held, except during initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * would slow down the IT87 access and should not be necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (has_newer_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) data->pwm_duty[nr] = it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) IT87_REG_PWM_DUTY[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) else /* Manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (has_old_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) for (i = 0; i < 5 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) data->auto_temp[nr][i] = it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) IT87_REG_AUTO_TEMP(nr, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) for (i = 0; i < 3 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) data->auto_pwm[nr][i] = it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) IT87_REG_AUTO_PWM(nr, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) } else if (has_newer_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * 0: temperature hysteresis (base + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * 1: fan off temperature (base + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * 2: fan start temperature (base + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * 3: fan max temperature (base + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) data->auto_temp[nr][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) for (i = 0; i < 3 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) data->auto_temp[nr][i + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) IT87_REG_AUTO_TEMP(nr, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * 0: start pwm value (base + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * 1: pwm slope (base + 4, 1/8th pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) data->auto_pwm[nr][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) data->auto_pwm[nr][1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static struct it87_data *it87_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (update_vbat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * Cleared after each update, so reenable. Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * returned by this read will be previous value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) it87_write_value(data, IT87_REG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) it87_read_value(data, IT87_REG_CONFIG) | 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) for (i = 0; i < NUM_VIN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!(data->has_in & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) data->in[i][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) it87_read_value(data, IT87_REG_VIN[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* VBAT and AVCC don't have limit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (i >= NUM_VIN_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) data->in[i][1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) it87_read_value(data, IT87_REG_VIN_MIN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) data->in[i][2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) it87_read_value(data, IT87_REG_VIN_MAX(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) for (i = 0; i < NUM_FAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Skip disabled fans */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!(data->has_fan & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) data->fan[i][1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) it87_read_value(data, IT87_REG_FAN_MIN[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) data->fan[i][0] = it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) IT87_REG_FAN[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Add high byte if in 16-bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (has_16bit_fans(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) data->fan[i][0] |= it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) IT87_REG_FANX[i]) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) data->fan[i][1] |= it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) IT87_REG_FANX_MIN[i]) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) for (i = 0; i < NUM_TEMP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!(data->has_temp & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) data->temp[i][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) it87_read_value(data, IT87_REG_TEMP(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) data->temp[i][3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) IT87_REG_TEMP_OFFSET[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (i >= NUM_TEMP_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) data->temp[i][1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) it87_read_value(data, IT87_REG_TEMP_LOW(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) data->temp[i][2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) it87_read_value(data, IT87_REG_TEMP_HIGH(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Newer chips don't have clock dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) i = it87_read_value(data, IT87_REG_FAN_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) data->fan_div[0] = i & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) data->fan_div[1] = (i >> 3) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) data->fan_div[2] = (i & 0x40) ? 3 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) data->alarms =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) it87_read_value(data, IT87_REG_ALARM1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) (it87_read_value(data, IT87_REG_ALARM2) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) (it87_read_value(data, IT87_REG_ALARM3) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) data->fan_main_ctrl = it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) IT87_REG_FAN_MAIN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) for (i = 0; i < NUM_PWM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (!(data->has_pwm & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) it87_update_pwm_ctrl(data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * The IT8705F does not have VID capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * The IT8718F and later don't use IT87_REG_VID for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * same purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (data->type == it8712 || data->type == it8716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) data->vid = it87_read_value(data, IT87_REG_VID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * The older IT8712F revisions had only 5 VID pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * but we assume it is always safe to read 6 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) data->vid &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) data->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static ssize_t show_in(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) int index = sattr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) int nr = sattr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static ssize_t set_in(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int index = sattr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int nr = sattr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) data->in[nr][index] = in_to_reg(data, nr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) it87_write_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) index == 1 ? IT87_REG_VIN_MIN(nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) : IT87_REG_VIN_MAX(nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) data->in[nr][index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) 3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) 4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) 5, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) 6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) 7, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* Up to 6 temperatures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) int nr = sattr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int index = sattr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) int nr = sattr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int index = sattr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u8 reg, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (kstrtol(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) reg = IT87_REG_TEMP_LOW(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) reg = IT87_REG_TEMP_HIGH(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!(regval & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) regval |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) data->valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) reg = IT87_REG_TEMP_OFFSET[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) data->temp[nr][index] = TEMP_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) it87_write_value(data, reg, data->temp[nr][index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) set_temp, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) set_temp, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) set_temp, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) u8 reg = data->sensor; /* In case value is updated while used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) u8 extra = data->extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) (has_temp_old_peci(data, nr) && (extra & 0x80)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return sprintf(buf, "6\n"); /* Intel PECI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (reg & (1 << nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return sprintf(buf, "3\n"); /* thermal diode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (reg & (8 << nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return sprintf(buf, "4\n"); /* thermistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return sprintf(buf, "0\n"); /* disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u8 reg, extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (kstrtol(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) reg &= ~(1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) reg &= ~(8 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) reg &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) extra &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (val == 2) { /* backwards compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) "Sensor type 2 is deprecated, please use 4 instead\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) val = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (val == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) reg |= 1 << nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) else if (val == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) reg |= 8 << nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) else if (has_temp_peci(data, nr) && val == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) reg |= (nr + 1) << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) else if (has_temp_old_peci(data, nr) && val == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) extra |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) else if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) data->sensor = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) data->extra = extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (has_temp_old_peci(data, nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) data->valid = 0; /* Force cache refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) set_temp_type, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) set_temp_type, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) set_temp_type, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* 6 Fans */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static int pwm_mode(const struct it87_data *data, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return 0; /* Full speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (data->pwm_ctrl[nr] & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return 2; /* Automatic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if ((data->type == it8603 || nr >= 3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return 0; /* Full speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return 1; /* Manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) int nr = sattr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int index = sattr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) speed = has_16bit_fans(data) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) FAN16_FROM_REG(data->fan[nr][index]) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) FAN_FROM_REG(data->fan[nr][index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) DIV_FROM_REG(data->fan_div[nr]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return sprintf(buf, "%d\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static ssize_t show_pwm_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return sprintf(buf, "%d\n", pwm_mode(data, nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return sprintf(buf, "%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) pwm_from_reg(data, data->pwm_duty[nr]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (has_pwm_freq2(data) && nr == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) index = (data->extra >> 4) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) index = (data->fan_ctl >> 4) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return sprintf(buf, "%u\n", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int nr = sattr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) int index = sattr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (kstrtol(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (has_16bit_fans(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) data->fan[nr][index] = FAN16_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) it87_write_value(data, IT87_REG_FAN_MIN[nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) data->fan[nr][index] & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) it87_write_value(data, IT87_REG_FANX_MIN[nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) data->fan[nr][index] >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) reg = it87_read_value(data, IT87_REG_FAN_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) data->fan_div[nr] = reg & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) data->fan_div[nr] = (reg >> 3) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) data->fan[nr][index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) it87_write_value(data, IT87_REG_FAN_MIN[nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) data->fan[nr][index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) int min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) u8 old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) old = it87_read_value(data, IT87_REG_FAN_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* Save fan min limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) switch (nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) data->fan_div[nr] = DIV_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (val < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) data->fan_div[nr] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) data->fan_div[nr] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) val = old & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) val |= (data->fan_div[0] & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) val |= (data->fan_div[1] & 0x07) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (data->fan_div[2] == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) val |= 0x1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) it87_write_value(data, IT87_REG_FAN_DIV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Restore fan min limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* Returns 0 if OK, -EINVAL otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int check_trip_points(struct device *dev, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) const struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) int i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (has_old_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) } else if (has_newer_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) for (i = 1; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) "Inconsistent trip points, not switching to automatic mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(dev, "Adjust the trip points and try again\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* Check trip points before switching to automatic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (val == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (check_trip_points(dev, nr) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (nr < 3 && data->type != it8603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* make sure the fan is on when in on/off mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) tmp = it87_read_value(data, IT87_REG_FAN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* set on/off mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) data->fan_main_ctrl &= ~BIT(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) data->fan_main_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* No on/off mode, set maximum pwm value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) it87_write_value(data, IT87_REG_PWM_DUTY[nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) data->pwm_duty[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* and set manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (has_newer_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ctrl = (data->pwm_ctrl[nr] & 0x7c) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) data->pwm_temp_map[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ctrl = data->pwm_duty[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) data->pwm_ctrl[nr] = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) it87_write_value(data, IT87_REG_PWM[nr], ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (has_newer_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ctrl = (data->pwm_ctrl[nr] & 0x7c) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) data->pwm_temp_map[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (val != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ctrl |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) data->pwm_ctrl[nr] = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) it87_write_value(data, IT87_REG_PWM[nr], ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (data->type != it8603 && nr < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* set SmartGuardian mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) data->fan_main_ctrl |= BIT(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) data->fan_main_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) it87_update_pwm_ctrl(data, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (has_newer_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * If we are in automatic mode, the PWM duty cycle register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * is read-only so we can't write the value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (data->pwm_ctrl[nr] & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) data->pwm_duty[nr] = pwm_to_reg(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) it87_write_value(data, IT87_REG_PWM_DUTY[nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) data->pwm_duty[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) data->pwm_duty[nr] = pwm_to_reg(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * If we are in manual mode, write the duty cycle immediately;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * otherwise, just store it for later use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (!(data->pwm_ctrl[nr] & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) data->pwm_ctrl[nr] = data->pwm_duty[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) it87_write_value(data, IT87_REG_PWM[nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) data->pwm_ctrl[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) val = clamp_val(val, 0, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) val *= has_newer_autopwm(data) ? 256 : 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* Search for the nearest available frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) for (i = 0; i < 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (nr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) data->fan_ctl |= i << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) data->extra |= i << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static ssize_t show_pwm_temp_map(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) map = data->pwm_temp_map[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (map >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) map = 0; /* Should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) map += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return sprintf(buf, "%d\n", (int)BIT(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static ssize_t set_pwm_temp_map(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (kstrtol(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (nr >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) val -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) case BIT(0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) reg = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) case BIT(1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) reg = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) case BIT(2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) reg = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) it87_update_pwm_ctrl(data, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) data->pwm_temp_map[nr] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * If we are in automatic mode, write the temp mapping immediately;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * otherwise, just store it for later use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (data->pwm_ctrl[nr] & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) data->pwm_temp_map[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) int point = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return sprintf(buf, "%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) pwm_from_reg(data, data->auto_pwm[nr][point]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) int point = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) int regaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) data->auto_pwm[nr][point] = pwm_to_reg(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (has_newer_autopwm(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) regaddr = IT87_REG_AUTO_TEMP(nr, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) regaddr = IT87_REG_AUTO_PWM(nr, point);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static ssize_t show_auto_pwm_slope(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static ssize_t set_auto_pwm_slope(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) int nr = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (kstrtoul(buf, 10, &val) < 0 || val > 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) data->auto_pwm[nr][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) int point = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (has_old_autopwm(data) || point)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) reg = data->auto_temp[nr][point];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct sensor_device_attribute_2 *sensor_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) int nr = sensor_attr->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) int point = sensor_attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (has_newer_autopwm(data) && !point) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) data->auto_temp[nr][0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) reg = TEMP_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) data->auto_temp[nr][point] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (has_newer_autopwm(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) point--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) set_fan_div, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) set_fan_div, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) set_fan_div, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) show_pwm_enable, set_pwm_enable, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) set_pwm_freq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) show_pwm_temp_map, set_pwm_temp_map, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) show_auto_pwm, set_auto_pwm, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) show_auto_pwm, set_auto_pwm, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) show_auto_pwm, set_auto_pwm, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) show_auto_pwm, NULL, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) show_auto_temp, set_auto_temp, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) show_auto_temp, set_auto_temp, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) show_auto_temp, set_auto_temp, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) show_auto_temp, set_auto_temp, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) show_auto_temp, set_auto_temp, 0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) show_auto_pwm, set_auto_pwm, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) show_auto_pwm_slope, set_auto_pwm_slope, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) show_pwm_enable, set_pwm_enable, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) show_pwm_temp_map, set_pwm_temp_map, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) show_auto_pwm, set_auto_pwm, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) show_auto_pwm, set_auto_pwm, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) show_auto_pwm, set_auto_pwm, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) show_auto_pwm, NULL, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) show_auto_temp, set_auto_temp, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) show_auto_temp, set_auto_temp, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) show_auto_temp, set_auto_temp, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) show_auto_temp, set_auto_temp, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) show_auto_temp, set_auto_temp, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) show_auto_pwm, set_auto_pwm, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) show_auto_pwm_slope, set_auto_pwm_slope, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) show_pwm_enable, set_pwm_enable, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) show_pwm_temp_map, set_pwm_temp_map, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) show_auto_pwm, set_auto_pwm, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) show_auto_pwm, set_auto_pwm, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) show_auto_pwm, set_auto_pwm, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) show_auto_pwm, NULL, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) show_auto_temp, set_auto_temp, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) show_auto_temp, set_auto_temp, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) show_auto_temp, set_auto_temp, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) show_auto_temp, set_auto_temp, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) show_auto_temp, set_auto_temp, 2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) show_auto_pwm, set_auto_pwm, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) show_auto_pwm_slope, set_auto_pwm_slope, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) show_pwm_enable, set_pwm_enable, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) show_pwm_temp_map, set_pwm_temp_map, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) show_auto_temp, set_auto_temp, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) show_auto_temp, set_auto_temp, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) show_auto_temp, set_auto_temp, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) show_auto_temp, set_auto_temp, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) show_auto_pwm, set_auto_pwm, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) show_auto_pwm_slope, set_auto_pwm_slope, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) show_pwm_enable, set_pwm_enable, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) show_pwm_temp_map, set_pwm_temp_map, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) show_auto_temp, set_auto_temp, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) show_auto_temp, set_auto_temp, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) show_auto_temp, set_auto_temp, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) show_auto_temp, set_auto_temp, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) show_auto_pwm, set_auto_pwm, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) show_auto_pwm_slope, set_auto_pwm_slope, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) show_pwm_enable, set_pwm_enable, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) show_pwm_temp_map, set_pwm_temp_map, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) show_auto_temp, set_auto_temp, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) show_auto_temp, set_auto_temp, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) show_auto_temp, set_auto_temp, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) show_auto_temp, set_auto_temp, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) show_auto_pwm, set_auto_pwm, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) show_auto_pwm_slope, set_auto_pwm_slope, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) /* Alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) return sprintf(buf, "%u\n", data->alarms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static DEVICE_ATTR_RO(alarms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) int bitnr = to_sensor_dev_attr(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static ssize_t clear_intrusion(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) if (kstrtol(buf, 10, &val) < 0 || val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) config = it87_read_value(data, IT87_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (config < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) count = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) config |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) it87_write_value(data, IT87_REG_CONFIG, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* Invalidate cache to force re-read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) data->valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) show_alarm, clear_intrusion, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) int bitnr = to_sensor_dev_attr(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) int bitnr = to_sensor_dev_attr(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) data->beeps |= BIT(bitnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) data->beeps &= ~BIT(bitnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) show_beep, set_beep, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* fanX_beep writability is set later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) show_beep, set_beep, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static ssize_t vrm_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return sprintf(buf, "%u\n", data->vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static ssize_t vrm_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (kstrtoul(buf, 10, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) data->vrm = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static DEVICE_ATTR_RW(vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static ssize_t cpu0_vid_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) struct it87_data *data = it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static DEVICE_ATTR_RO(cpu0_vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static ssize_t show_label(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static const char * const labels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) "+5V",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) "5VSB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) "Vbat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) "AVCC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static const char * const labels_it8721[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) "+3.3V",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) "3VSB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) "Vbat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) "+3.3V",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) int nr = to_sensor_dev_attr(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (has_vin3_5v(data) && nr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) label = labels[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) else if (has_12mv_adc(data) || has_10_9mv_adc(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) label = labels_it8721[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) label = labels[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return sprintf(buf, "%s\n", label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /* AVCC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static umode_t it87_in_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) struct attribute *attr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct device *dev = container_of(kobj, struct device, kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) int i = index / 5; /* voltage index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) int a = index % 5; /* attribute index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (index >= 40) { /* in8 and higher only have input attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) i = index - 40 + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) a = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (!(data->has_in & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if (a == 4 && !data->has_beep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static struct attribute *it87_attributes_in[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) &sensor_dev_attr_in0_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) &sensor_dev_attr_in0_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) &sensor_dev_attr_in0_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) &sensor_dev_attr_in0_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) &sensor_dev_attr_in1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) &sensor_dev_attr_in1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) &sensor_dev_attr_in1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) &sensor_dev_attr_in1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) &sensor_dev_attr_in2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) &sensor_dev_attr_in2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) &sensor_dev_attr_in2_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) &sensor_dev_attr_in2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) &sensor_dev_attr_in3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) &sensor_dev_attr_in3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) &sensor_dev_attr_in3_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) &sensor_dev_attr_in3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) &sensor_dev_attr_in4_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) &sensor_dev_attr_in4_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) &sensor_dev_attr_in4_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) &sensor_dev_attr_in4_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) &sensor_dev_attr_in5_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) &sensor_dev_attr_in5_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) &sensor_dev_attr_in5_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) &sensor_dev_attr_in5_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) &sensor_dev_attr_in6_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) &sensor_dev_attr_in6_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) &sensor_dev_attr_in6_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) &sensor_dev_attr_in6_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) &sensor_dev_attr_in7_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) &sensor_dev_attr_in7_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) &sensor_dev_attr_in7_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) &sensor_dev_attr_in7_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) &sensor_dev_attr_in9_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) &sensor_dev_attr_in10_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) &sensor_dev_attr_in11_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) &sensor_dev_attr_in12_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) static const struct attribute_group it87_group_in = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .attrs = it87_attributes_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .is_visible = it87_in_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static umode_t it87_temp_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) struct attribute *attr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) struct device *dev = container_of(kobj, struct device, kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) int i = index / 7; /* temperature index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) int a = index % 7; /* attribute index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (index >= 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) i = index - 21 + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) a = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (!(data->has_temp & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (a == 5 && !has_temp_offset(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (a == 6 && !data->has_beep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) static struct attribute *it87_attributes_temp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) &sensor_dev_attr_temp1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) &sensor_dev_attr_temp1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) &sensor_dev_attr_temp1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) &sensor_dev_attr_temp1_type.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) &sensor_dev_attr_temp1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) &sensor_dev_attr_temp2_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) &sensor_dev_attr_temp2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) &sensor_dev_attr_temp2_type.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) &sensor_dev_attr_temp2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) &sensor_dev_attr_temp2_offset.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) &sensor_dev_attr_temp2_beep.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) &sensor_dev_attr_temp3_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) &sensor_dev_attr_temp3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) &sensor_dev_attr_temp3_type.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) &sensor_dev_attr_temp3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) &sensor_dev_attr_temp3_offset.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) &sensor_dev_attr_temp3_beep.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) &sensor_dev_attr_temp5_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) &sensor_dev_attr_temp6_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static const struct attribute_group it87_group_temp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .attrs = it87_attributes_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .is_visible = it87_temp_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) static umode_t it87_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) struct attribute *attr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) struct device *dev = container_of(kobj, struct device, kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if ((index == 2 || index == 3) && !data->has_vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (index > 3 && !(data->in_internal & BIT(index - 4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) static struct attribute *it87_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) &dev_attr_alarms.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) &dev_attr_vrm.attr, /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) &dev_attr_cpu0_vid.attr, /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) &sensor_dev_attr_in7_label.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) &sensor_dev_attr_in8_label.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) &sensor_dev_attr_in9_label.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) static const struct attribute_group it87_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .attrs = it87_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .is_visible = it87_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static umode_t it87_fan_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) struct attribute *attr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) struct device *dev = container_of(kobj, struct device, kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) int i = index / 5; /* fan index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) int a = index % 5; /* attribute index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (index >= 15) { /* fan 4..6 don't have divisor attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) i = (index - 15) / 4 + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) a = (index - 15) % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) if (!(data->has_fan & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (a == 3) { /* beep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) if (!data->has_beep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /* first fan beep attribute is writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (i == __ffs(data->has_fan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) return attr->mode | S_IWUSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (a == 4 && has_16bit_fans(data)) /* divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) static struct attribute *it87_attributes_fan[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) &sensor_dev_attr_fan1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) &sensor_dev_attr_fan1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) &sensor_dev_attr_fan1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) &sensor_dev_attr_fan2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) &sensor_dev_attr_fan2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) &sensor_dev_attr_fan2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) &sensor_dev_attr_fan2_beep.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) &sensor_dev_attr_fan3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) &sensor_dev_attr_fan3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) &sensor_dev_attr_fan3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) &sensor_dev_attr_fan3_beep.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) &sensor_dev_attr_fan4_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) &sensor_dev_attr_fan4_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) &sensor_dev_attr_fan4_beep.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) &sensor_dev_attr_fan5_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) &sensor_dev_attr_fan5_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) &sensor_dev_attr_fan5_beep.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) &sensor_dev_attr_fan6_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) &sensor_dev_attr_fan6_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) &sensor_dev_attr_fan6_beep.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static const struct attribute_group it87_group_fan = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .attrs = it87_attributes_fan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .is_visible = it87_fan_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static umode_t it87_pwm_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) struct attribute *attr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) struct device *dev = container_of(kobj, struct device, kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) int i = index / 4; /* pwm index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) int a = index % 4; /* attribute index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) if (!(data->has_pwm & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) return attr->mode | S_IWUSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) /* pwm2_freq is writable if there are two pwm frequency selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (has_pwm_freq2(data) && i == 1 && a == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) return attr->mode | S_IWUSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static struct attribute *it87_attributes_pwm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) &sensor_dev_attr_pwm1_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) &sensor_dev_attr_pwm1.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) &sensor_dev_attr_pwm1_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) &sensor_dev_attr_pwm2_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) &sensor_dev_attr_pwm2.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) &sensor_dev_attr_pwm2_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) &sensor_dev_attr_pwm3_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) &sensor_dev_attr_pwm3.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) &sensor_dev_attr_pwm3_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) &sensor_dev_attr_pwm4_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) &sensor_dev_attr_pwm4.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) &sensor_dev_attr_pwm4_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) &sensor_dev_attr_pwm5_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) &sensor_dev_attr_pwm5.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) &sensor_dev_attr_pwm5_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) &sensor_dev_attr_pwm6_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) &sensor_dev_attr_pwm6.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) &sensor_dev_attr_pwm6_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) static const struct attribute_group it87_group_pwm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .attrs = it87_attributes_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .is_visible = it87_pwm_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) struct attribute *attr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) struct device *dev = container_of(kobj, struct device, kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) int i = index / 11; /* pwm index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) int a = index % 11; /* attribute index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) if (index >= 33) { /* pwm 4..6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) i = (index - 33) / 6 + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) a = (index - 33) % 6 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (!(data->has_pwm & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (has_newer_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) if (a < 4) /* no auto point pwm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) if (a == 8) /* no auto_point4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (has_old_autopwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) static struct attribute *it87_attributes_auto_pwm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) static const struct attribute_group it87_group_auto_pwm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .attrs = it87_attributes_auto_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .is_visible = it87_auto_pwm_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) /* SuperIO detection - will change isa_address if a chip is found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) static int __init it87_find(int sioaddr, unsigned short *address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) struct it87_sio_data *sio_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) u16 chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) const char *board_vendor, *board_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) const struct it87_devices *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) err = superio_enter(sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) switch (chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) case IT8705F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) sio_data->type = it87;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) case IT8712F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) sio_data->type = it8712;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) case IT8716F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) case IT8726F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) sio_data->type = it8716;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) case IT8718F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) sio_data->type = it8718;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) case IT8720F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) sio_data->type = it8720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) case IT8721F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) sio_data->type = it8721;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) case IT8728F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) sio_data->type = it8728;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) case IT8732F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) sio_data->type = it8732;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) case IT8792E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) sio_data->type = it8792;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) case IT8771E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) sio_data->type = it8771;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) case IT8772E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) sio_data->type = it8772;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) case IT8781F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) sio_data->type = it8781;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) case IT8782F_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) sio_data->type = it8782;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) case IT8783E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) sio_data->type = it8783;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) case IT8786E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) sio_data->type = it8786;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) case IT8790E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) sio_data->type = it8790;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) case IT8603E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) case IT8623E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) sio_data->type = it8603;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) case IT8620E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) sio_data->type = it8620;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) case IT8622E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) sio_data->type = it8622;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) case IT8628E_DEVID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) sio_data->type = it8628;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) case 0xffff: /* No device at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) superio_select(sioaddr, PME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) pr_info("Device not activated, skipping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) if (*address == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) pr_info("Base address not set, skipping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) sio_data->sioaddr = sioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) it87_devices[sio_data->type].suffix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) *address, sio_data->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) config = &it87_devices[sio_data->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) /* in7 (VSB or VCCH5V) is always internal on some chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) if (has_in7_internal(config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) sio_data->internal |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) /* in8 (Vbat) is always internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) sio_data->internal |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /* in9 (AVCC3), always internal if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) if (has_avcc3(config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) sio_data->internal |= BIT(3); /* in9 is AVCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) sio_data->skip_in |= BIT(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) if (!has_five_pwm(config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) else if (!has_six_pwm(config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) sio_data->skip_pwm |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) if (!has_vid(config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) sio_data->skip_vid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) /* Read GPIO config and VID value from LDN 7 (GPIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) if (sio_data->type == it87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* The IT8705F has a different LD number for GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) superio_select(sioaddr, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) sio_data->beep_pin = superio_inb(sioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) IT87_SIO_BEEP_PIN_REG) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) } else if (sio_data->type == it8783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) int reg25, reg27, reg2a, reg2c, regef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) superio_select(sioaddr, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) /* Check if fan3 is there or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) sio_data->skip_fan |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if ((reg25 & BIT(4)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) (!(reg2a & BIT(1)) && (regef & BIT(0))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) sio_data->skip_pwm |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) /* Check if fan2 is there or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) if (reg27 & BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) sio_data->skip_fan |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (reg27 & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) sio_data->skip_pwm |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* VIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) sio_data->skip_in |= BIT(5); /* No VIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /* VIN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) if (reg27 & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) sio_data->skip_in |= BIT(6); /* No VIN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) * VIN7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) * Does not depend on bit 2 of Reg2C, contrary to datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (reg27 & BIT(2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) * The data sheet is a bit unclear regarding the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) * internal voltage divider for VCCH5V. It says
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) * "This bit enables and switches VIN7 (pin 91) to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) * internal voltage divider for VCCH5V".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) * This is different to other chips, where the internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) * voltage divider would connect VIN7 to an internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) * voltage source. Maybe that is the case here as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) * Since we don't know for sure, re-route it if that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) * not the case, and ask the user to report if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) * resulting voltage is sane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) if (!(reg2c & BIT(1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) reg2c |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) superio_outb(sioaddr, IT87_SIO_PINX2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) reg2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) sio_data->need_in7_reroute = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) pr_notice("Routing internal VCCH5V to in7.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) pr_notice("Please report if it displays a reasonable voltage.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) if (reg2c & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) sio_data->internal |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) if (reg2c & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) sio_data->internal |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) sio_data->beep_pin = superio_inb(sioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) IT87_SIO_BEEP_PIN_REG) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) } else if (sio_data->type == it8603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) int reg27, reg29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) superio_select(sioaddr, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /* Check if fan3 is there or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (reg27 & BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) sio_data->skip_pwm |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) if (reg27 & BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) sio_data->skip_fan |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) /* Check if fan2 is there or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (reg29 & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) sio_data->skip_pwm |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) if (reg29 & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) sio_data->skip_fan |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) sio_data->skip_in |= BIT(5); /* No VIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) sio_data->skip_in |= BIT(6); /* No VIN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) sio_data->beep_pin = superio_inb(sioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) IT87_SIO_BEEP_PIN_REG) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) } else if (sio_data->type == it8620 || sio_data->type == it8628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) superio_select(sioaddr, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) /* Check for pwm5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (reg & BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) sio_data->skip_pwm |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /* Check for fan4, fan5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) if (!(reg & BIT(5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) sio_data->skip_fan |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (!(reg & BIT(4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) sio_data->skip_fan |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) /* Check for pwm3, fan3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) if (reg & BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) sio_data->skip_pwm |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) if (reg & BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) sio_data->skip_fan |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) /* Check for pwm4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) if (reg & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) sio_data->skip_pwm |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) /* Check for pwm2, fan2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) if (reg & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) sio_data->skip_pwm |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) if (reg & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) sio_data->skip_fan |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) /* Check for pwm6, fan6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) if (!(reg & BIT(7))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) sio_data->skip_pwm |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) sio_data->skip_fan |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) /* Check if AVCC is on VIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) if (reg & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) sio_data->internal |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) sio_data->skip_in |= BIT(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) sio_data->beep_pin = superio_inb(sioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) IT87_SIO_BEEP_PIN_REG) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) } else if (sio_data->type == it8622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) superio_select(sioaddr, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) /* Check for pwm4, fan4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if (reg & BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) sio_data->skip_fan |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) if (reg & BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) sio_data->skip_pwm |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) /* Check for pwm3, fan3, pwm5, fan5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) if (reg & BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) sio_data->skip_pwm |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) if (reg & BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) sio_data->skip_fan |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) if (reg & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) sio_data->skip_pwm |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) if (reg & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) sio_data->skip_fan |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) /* Check for pwm2, fan2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) if (reg & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) sio_data->skip_pwm |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) if (reg & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) sio_data->skip_fan |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) /* Check for AVCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) if (!(reg & BIT(0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) sio_data->skip_in |= BIT(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) sio_data->beep_pin = superio_inb(sioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) IT87_SIO_BEEP_PIN_REG) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) bool uart6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) superio_select(sioaddr, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) /* Check for fan4, fan5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) if (has_five_fans(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) switch (sio_data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) case it8718:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) if (reg & BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) sio_data->skip_fan |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) if (reg & BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) sio_data->skip_fan |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) case it8720:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) case it8721:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) case it8728:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) if (!(reg & BIT(5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) sio_data->skip_fan |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) if (!(reg & BIT(4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) sio_data->skip_fan |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) if (!sio_data->skip_vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /* We need at least 4 VID pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) if (reg & 0x0f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) pr_info("VID is disabled (pins used for GPIO)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) sio_data->skip_vid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) /* Check if fan3 is there or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) if (reg & BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) sio_data->skip_pwm |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) if (reg & BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) sio_data->skip_fan |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) /* Check if fan2 is there or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) if (reg & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) sio_data->skip_pwm |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (reg & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) sio_data->skip_fan |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if ((sio_data->type == it8718 || sio_data->type == it8720) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) !(sio_data->skip_vid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) sio_data->vid_value = superio_inb(sioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) IT87_SIO_VID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) uart6 = sio_data->type == it8782 && (reg & BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) * The IT8720F has no VIN7 pin, so VCCH5V should always be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) * routed internally to VIN7 with an internal divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) * Curiously, there still is a configuration bit to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) * this, which means it can be set incorrectly. And even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) * more curiously, many boards out there are improperly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) * configured, even though the IT8720F datasheet claims
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) * that the internal routing of VCCH5V to VIN7 is the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) * setting. So we force the internal routing in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) * If UART6 is enabled, re-route VIN7 to the internal divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) * if that is not already the case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) reg |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) sio_data->need_in7_reroute = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) pr_notice("Routing internal VCCH5V to in7\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) if (reg & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) sio_data->internal |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (reg & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) sio_data->internal |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) * While VIN7 can be routed to the internal voltage divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) * VIN5 and VIN6 are not available if UART6 is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) * Also, temp3 is not available if UART6 is enabled and TEMPIN3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) * is the temperature source. Since we can not read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) * temperature source here, skip_temp is preliminary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) if (uart6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) sio_data->skip_in |= BIT(5) | BIT(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) sio_data->skip_temp |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) sio_data->beep_pin = superio_inb(sioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) IT87_SIO_BEEP_PIN_REG) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) if (sio_data->beep_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) pr_info("Beeping is supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) /* Disable specific features based on DMI strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) board_name = dmi_get_system_info(DMI_BOARD_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) if (board_vendor && board_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) if (strcmp(board_vendor, "nVIDIA") == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) strcmp(board_name, "FN68PT") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) * On the Shuttle SN68PT, FAN_CTL2 is apparently not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) * connected to a fan, but to something else. One user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) * has reported instant system power-off when changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) * the PWM2 duty cycle, so we disable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) * I use the board name string as the trigger in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) * the same board is ever used in other systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) pr_info("Disabling pwm2 due to hardware constraints\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) sio_data->skip_pwm = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) superio_exit(sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) * Some chips seem to have default value 0xff for all limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) * registers. For low voltage limits it makes no sense and triggers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) * alarms, so change to 0 instead. For high temperature limits, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) * means -1 degree C, which surprisingly doesn't trigger an alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) * but is still confusing, so change to 127 degrees C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) static void it87_check_limit_regs(struct it87_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) int i, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) for (i = 0; i < NUM_VIN_LIMIT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) reg = it87_read_value(data, IT87_REG_VIN_MIN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) if (reg == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) for (i = 0; i < NUM_TEMP_LIMIT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) if (reg == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) /* Check if voltage monitors are reset manually or by some reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static void it87_check_voltage_monitors_reset(struct it87_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) reg = it87_read_value(data, IT87_REG_VIN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) if ((reg & 0xff) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) /* Enable all voltage monitors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) /* Check if tachometers are reset manually or by some reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) static void it87_check_tachometers_reset(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) struct it87_data *data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) u8 mask, fan_main_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) mask = 0x70 & ~(sio_data->skip_fan << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) if ((fan_main_ctrl & mask) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) /* Enable all fan tachometers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) fan_main_ctrl |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) fan_main_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) /* Set tachometers to 16-bit mode if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) static void it87_check_tachometers_16bit_mode(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) struct it87_data *data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) if (!has_fan16_config(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) reg = it87_read_value(data, IT87_REG_FAN_16BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) if (~reg & 0x07 & data->has_fan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) "Setting fan1-3 to 16-bit mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) it87_write_value(data, IT87_REG_FAN_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) reg | 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) static void it87_start_monitoring(struct it87_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) it87_write_value(data, IT87_REG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) | (update_vbat ? 0x41 : 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) /* Called when we have found a new IT87. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) static void it87_init_device(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) struct it87_data *data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) int tmp, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) * For each PWM channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) * - If it is in automatic mode, setting to manual mode should set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) * the fan to full speed by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) * - If it is in manual mode, we need a mapping to temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) * channels to use when later setting to automatic mode later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) * Use a 1:1 mapping by default (we are clueless.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) * In both cases, the value can (and should) be changed by the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) * prior to switching to a different mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) * Note that this is no longer needed for the IT8721F and later, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) * these have separate registers for the temperature mapping and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) * manual duty cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) for (i = 0; i < NUM_AUTO_PWM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) data->pwm_temp_map[i] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) data->pwm_duty[i] = 0x7f; /* Full speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) it87_check_limit_regs(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) * Temperature channels are not forcibly enabled, as they can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) * set to two different sensor types and we can't guess which one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) * is correct for a given system. These channels can be enabled at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) * run-time through the temp{1-3}_type sysfs accessors if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) it87_check_voltage_monitors_reset(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) it87_check_tachometers_reset(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) it87_check_tachometers_16bit_mode(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) /* Check for additional fans */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) if (has_five_fans(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) if (tmp & BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) data->has_fan |= BIT(3); /* fan4 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) if (tmp & BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) data->has_fan |= BIT(4); /* fan5 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) if (has_six_fans(data) && (tmp & BIT(2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) data->has_fan |= BIT(5); /* fan6 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) /* Fan input pins may be used for alternative functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) data->has_fan &= ~sio_data->skip_fan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) /* Check if pwm5, pwm6 are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) if (has_six_pwm(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) /* The following code may be IT8620E specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) tmp = it87_read_value(data, IT87_REG_FAN_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) if ((tmp & 0xc0) == 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) sio_data->skip_pwm |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) if (!(tmp & BIT(3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) sio_data->skip_pwm |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) it87_start_monitoring(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) /* Return 1 if and only if the PWM interface is safe to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) static int it87_check_pwm(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) * Some BIOSes fail to correctly configure the IT87 fans. All fans off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) * and polarity set to active low is sign that this is the case so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) * disable pwm control to protect the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) if ((tmp & 0x87) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) if (fix_pwm_polarity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) * The user asks us to attempt a chip reconfiguration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) * This means switching to active high polarity and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) * inverting all fan speed values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) u8 pwm[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) for (i = 0; i < ARRAY_SIZE(pwm); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) pwm[i] = it87_read_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) IT87_REG_PWM[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) * If any fan is in automatic pwm mode, the polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) * might be correct, as suspicious as it seems, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) * better don't change anything (but still disable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) * PWM interface).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) "Reconfiguring PWM to active high polarity\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) it87_write_value(data, IT87_REG_FAN_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) tmp | 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) it87_write_value(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) IT87_REG_PWM[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) 0x7f & ~pwm[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) "PWM configuration is too broken to be fixed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) } else if (fix_pwm_polarity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) "PWM configuration looks sane, won't touch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) static int it87_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) struct it87_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) struct it87_sio_data *sio_data = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) int enable_pwm_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) DRVNAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) (unsigned long)res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) (unsigned long)(res->start + IT87_EC_EXTENT - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) data->addr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) data->sioaddr = sio_data->sioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) data->type = sio_data->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) data->features = it87_devices[sio_data->type].features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) data->peci_mask = it87_devices[sio_data->type].peci_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) * IT8705F Datasheet 0.4.1, 3h == Version G.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) * These are the first revisions with 16-bit tachometer support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) case it87:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) if (sio_data->revision >= 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) data->features &= ~FEAT_OLD_AUTOPWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) case it8712:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) if (sio_data->revision >= 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) data->features &= ~FEAT_OLD_AUTOPWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) FEAT_FIVE_FANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) /* Now, we do the remaining detection. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) it87_read_value(data, IT87_REG_CHIPID) != 0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) /* Check PWM configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) enable_pwm_interface = it87_check_pwm(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) if (!enable_pwm_interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) "Detected broken BIOS defaults, disabling PWM interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) /* Starting with IT8721F, we handle scaling of internal voltages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) if (has_12mv_adc(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) if (sio_data->internal & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) data->in_scaled |= BIT(3); /* in3 is AVCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) if (sio_data->internal & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) data->in_scaled |= BIT(7); /* in7 is VSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) if (sio_data->internal & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) data->in_scaled |= BIT(8); /* in8 is Vbat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) if (sio_data->internal & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) data->in_scaled |= BIT(9); /* in9 is AVCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) sio_data->type == it8783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) if (sio_data->internal & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) data->in_scaled |= BIT(3); /* in3 is VCC5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) if (sio_data->internal & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) data->in_scaled |= BIT(7); /* in7 is VCCH5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) data->has_temp = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) if (sio_data->skip_temp & BIT(2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) if (sio_data->type == it8782 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) data->has_temp &= ~BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) data->in_internal = sio_data->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) data->need_in7_reroute = sio_data->need_in7_reroute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) data->has_in = 0x3ff & ~sio_data->skip_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) if (has_six_temp(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) /* Check for additional temperature sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) if ((reg & 0x03) >= 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) data->has_temp |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) if (((reg >> 2) & 0x03) >= 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) data->has_temp |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) if (((reg >> 4) & 0x03) >= 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) data->has_temp |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) /* Check for additional voltage sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) if ((reg & 0x03) == 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) data->has_in |= BIT(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) if (((reg >> 2) & 0x03) == 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) data->has_in |= BIT(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) if (((reg >> 4) & 0x03) == 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) data->has_in |= BIT(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) data->has_beep = !!sio_data->beep_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) /* Initialize the IT87 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) it87_init_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) if (!sio_data->skip_vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) data->has_vid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) data->vrm = vid_which_vrm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) /* VID reading from Super-I/O config space if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) data->vid = sio_data->vid_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) /* Prepare for sysfs hooks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) data->groups[0] = &it87_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) data->groups[1] = &it87_group_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) data->groups[2] = &it87_group_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) data->groups[3] = &it87_group_fan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) if (enable_pwm_interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) data->has_pwm &= ~sio_data->skip_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) data->groups[4] = &it87_group_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) if (has_old_autopwm(data) || has_newer_autopwm(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) data->groups[5] = &it87_group_auto_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) hwmon_dev = devm_hwmon_device_register_with_groups(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) it87_devices[sio_data->type].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) data, data->groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) static void __maybe_unused it87_resume_sio(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) struct it87_data *data = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) int reg2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) if (!data->need_in7_reroute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) err = superio_enter(data->sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) "Unable to enter Super I/O to reroute in7 (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) superio_select(data->sioaddr, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) if (!(reg2c & BIT(1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) "Routing internal VCCH5V to in7 again");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) reg2c |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) superio_outb(data->sioaddr, IT87_SIO_PINX2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) reg2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) superio_exit(data->sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) static int __maybe_unused it87_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) struct it87_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) it87_resume_sio(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) it87_check_pwm(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) it87_check_limit_regs(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) it87_check_voltage_monitors_reset(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) it87_check_tachometers_reset(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) it87_check_tachometers_16bit_mode(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) it87_start_monitoring(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) /* force update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) data->valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) it87_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) static SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) static struct platform_driver it87_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) .name = DRVNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) .pm = &it87_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) .probe = it87_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) static int __init it87_device_add(int index, unsigned short address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) const struct it87_sio_data *sio_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) struct resource res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) .start = address + IT87_EC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) .name = DRVNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) err = acpi_check_resource_conflict(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) pdev = platform_device_alloc(DRVNAME, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) err = platform_device_add_resources(pdev, &res, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) pr_err("Device resource addition failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) err = platform_device_add_data(pdev, sio_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) sizeof(struct it87_sio_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) pr_err("Platform data allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) err = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) pr_err("Device addition failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) it87_pdev[index] = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) exit_device_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) static int __init sm_it87_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) int sioaddr[2] = { REG_2E, REG_4E };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) struct it87_sio_data sio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) unsigned short isa_address[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) err = platform_driver_register(&it87_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) memset(&sio_data, 0, sizeof(struct it87_sio_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) isa_address[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) err = it87_find(sioaddr[i], &isa_address[i], &sio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) if (err || isa_address[i] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) * Don't register second chip if its ISA address matches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) * the first chip's ISA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) if (i && isa_address[i] == isa_address[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) err = it87_device_add(i, isa_address[i], &sio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) goto exit_dev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) * IT8705F may respond on both SIO addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) * Stop probing after finding one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) if (sio_data.type == it87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) goto exit_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) exit_dev_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) /* NULL check handled by platform_device_unregister */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) platform_device_unregister(it87_pdev[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) exit_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) platform_driver_unregister(&it87_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) static void __exit sm_it87_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) /* NULL check handled by platform_device_unregister */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) platform_device_unregister(it87_pdev[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) platform_device_unregister(it87_pdev[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) platform_driver_unregister(&it87_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) module_param(update_vbat, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) module_param(fix_pwm_polarity, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) MODULE_PARM_DESC(fix_pwm_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) "Force PWM polarity to active high (DANGEROUS)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) module_init(sm_it87_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) module_exit(sm_it87_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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